JP2006004233A - Recording medium control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a recording medium control device enabling respective processors to share a recording medium and access thereto, in a structure where a main processor and a plurality of slave processors share the storage medium, without deteriorating the performance of information transfer between the main processor and the recording medium. <P>SOLUTION: The recording medium control device performing a control for sharing of the recording medium by the main processor and at least one or more slave processor comprises a memory storing information to be exchanged between the slave processors and the recording medium; a memory interface part performing input and output processing to the memory; a memory transfer part responding to the slave processors and transferring information to be exchanged between the slave processors and the memory through the memory interface part; and a recording medium transfer part transferring, according to an instruction from the main processor, the information to be exchanged between the memory and the recording medium. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a recording medium control apparatus that controls a plurality of processors to share a recording medium, and is suitable for application to a moving image recording / reproducing apparatus.

Conventionally, in order for a plurality of CPUs to share a recording medium, a CPU (Central Processing Unit) accessing the recording medium transfers information via a CPU having an IO (input / output) interface with the recording medium. Was common.
FIG. 4 is a block diagram showing a conventional hardware configuration, including a recording medium 20, a CPU 21 having an IO interface with the recording medium 20, a plurality of CPUs 22 having no IO interface with the recording medium 20, and It is comprised by the bus | bath 23 which connects CPU21,22.

  In the case of this configuration, in order for the CPU 22 to access the recording medium 20, it is necessary to transfer information via the CPU 21. Therefore, when a large amount of data transfer is requested from a plurality of CPUs 22, the processing capacity of the CPU 21 becomes a bottleneck. There is a problem that the processing efficiency is lowered.

In order to solve this problem, the information processing system of Patent Document 1 proposes a hardware configuration as shown in FIG. This information processing system includes a recording medium 30, a plurality of CPUs 31, and a bus 32 that connects these CPUs 31.
When this configuration is used, by directly connecting the recording medium 30 to the bus 32, each CPU 31 can access the recording medium 30 without passing through another CPU, and the processing can be performed at high speed.
JP-A-4-52754

  However, when a configuration in which a plurality of CPUs share a recording medium using the technology of Patent Document 1, an existing IO interface with a recording medium included in each CPU cannot be directly connected to the bus. The hardware needs to be modified significantly to accommodate it. The same applies to software for performing IO control to the recording medium.

  Further, when a hardware configuration in which a single main CPU out of a plurality of CPUs controls the entire system according to a plurality of subordinate CPUs is used, the main CPU is configured to transmit information between the subordinate CPU and the recording medium. It is important to have an access right to the recording medium in order to grasp the transmission / reception status in order to efficiently control the transmission / reception of the recording medium and to reduce the seek time of the recording medium.

  The present invention has been made in consideration of the above circumstances, and in a configuration in which a main processor and at least one or more subordinate processors share a recording medium, the performance of information transfer between the main processor and the recording medium. Recording medium that allows each processor to share and access the recording medium without causing the recording medium to seek even when there are simultaneous accesses to the recording medium from a plurality of processors An object is to provide a control device.

In order to solve the above problems, the present invention has the following configuration.
A recording medium control apparatus according to the present invention is a recording medium control apparatus that performs control for sharing a recording medium between a main processor and at least one or more subordinate processors, and includes the subordinate processor and the recording medium. Corresponding to a memory in which information exchanged between them is stored, a memory interface unit that performs input / output processing to the memory, and the slave processor, the slave processor and the memory via the memory interface unit A memory transfer unit for transferring information exchanged between the memory and a recording medium transfer unit for transferring information exchanged between the memory and the recording medium in accordance with an instruction from the main processor. Yes.

  The main processor directly accesses the recording medium without going through the memory, while the subordinate processor accesses the recording medium through the memory under the control of the main processor. Thereby, each processor can be performed without reducing the performance of information transfer between the main processor and the recording medium, and without causing the recording medium to seek even when there are simultaneous accesses to the recording medium from a plurality of processors. Can share and access the recording medium.

  In addition, by providing a memory transfer unit corresponding to each slave processor having an IO interface, it is possible to greatly reduce the amount of hardware and software correction for each slave processor to perform IO control. is there.

  In addition, when there is content to be transmitted to the main processor, the subordinate processor issues a specific processing request to the memory transfer unit, and asserts an interrupt signal to the main processor, thereby informing the main processor to that effect. Can communicate.

  Further, by providing a register accessible from the main processor and the subordinate processor in the memory transfer unit, when there is content to be transmitted from the main processor to the subordinate processor or from the subordinate processor to the main processor, GPIO Even if a communication interface such as I2C or VMI is not used, both processors can communicate with each other by accessing the register.

  Further, when the main processor refers to the register in the memory transfer unit, an interrupt signal to the main processor can be canceled.

  In addition, when there is content to be transmitted to the subordinate processor, the main processor can transmit the fact to the subordinate processor by changing the register in the memory transfer unit from the main processor.

  According to the present invention, in a configuration in which a main processor and at least one or more subordinate processors share a recording medium, it is possible to reduce the performance of information transfer between the main processor and the recording medium, and from a plurality of processors. At the same time, even when there is access to the recording medium, each processor can share and access the recording medium without generating a seek of the recording medium.

  In addition, it is possible to greatly reduce the amount of correction of hardware and software for each subordinate processor to perform IO control.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a preferred embodiment according to a recording medium control device of the invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating a hardware configuration of a recording medium control apparatus according to the present embodiment. In FIG. 1, the recording medium control apparatus 1 includes a main processor 2 and at least the control of the main processor 2. One or more subordinate processors 3 perform control for sharing one recording medium 4.

Further, the recording medium control device 1 includes a memory 13 that stores information exchanged between the slave processor 3 and the recording medium 4, and a memory interface (I / F) unit that performs input / output processing to the memory 13. 14, a memory transfer unit 11 that transfers information exchanged between the slave processor 3 and the memory 13, and a recording medium transfer unit 12 that performs a process of transferring information to the recording medium 4. Yes. Here, in general, the main processor 2 and the plurality of subordinate processors and the recording medium control device 1 are arranged on the same board so that the subordinate processor 3 and the memory transfer unit 11 correspond one-to-one. Is done.
Further, the main processor 2 and the subordinate processor 3 can access the recording medium transfer unit 12 and the memory transfer unit 11 as virtual drives, respectively.

The memory transfer unit 11 includes a transmission / reception unit 111, a control unit 112, and a transfer unit 113. The control unit 112 includes a register 114 that sets data and processing requests for communication between the main processor 2 and the subordinate processor 3.
In the present invention, when the subordinate processor 3 accesses the recording medium 4, information to be exchanged is temporarily stored in the memory 13 in order to suppress frequent access to the recording medium 4. In addition, the transmission / reception unit 111 distributes data access and register access from the subordinate processor 3, and transfers data to the transfer unit 113 if the access is data access, or registers in the control unit 112 if the access is register access. Information is transferred to 114.

  In the above configuration, for example, when an application performs recording on a recording medium or reproduction from the recording medium, the main processor 2 that controls the system is a subordinate processor to which an encoder function, a decoder function, or other functions are assigned. 3, processing contents are transmitted via the communication port, such as whether playback or recording, or what number of contents.

(1) Data writing to a recording medium In the case of processing for writing data to a recording medium from an application, the main processor 2 sends the start address of the main memory storing the data to be written to the subordinate processor 3 having a writing function. The processing contents are transmitted via the communication port by specifying the data length.

Hereinafter, the procedure executed by the processor 3 according to the processing content designated by the main processor 2 will be described with reference to the operation sequence diagram of FIG.
The subordinate processor 3 transmits a register setting request for setting a write command for writing data from the main memory to the recording medium in the register 114 to the memory transfer unit 11 and starts transferring data from the main memory.

The memory transfer unit 11 sets the “write command” in the register 114 by operating the transmission / reception unit 111 in response to the register setting request.
When a value is set in the register 114, the memory transfer unit 11 analyzes the contents of the register 114 and confirms that it is a “write command”. Then, the memory transfer unit 11 transmits information sent from the subsequent processor 3 to the transfer unit 113. Then, the data is transferred to the memory 13 via the memory I / F unit 14.
The memory 13 is controlled by an arbiter on the memory bus, and is shared with the slave processor 3 by executing processing in the order of requests.

  When the transfer to the memory 13 is completed, the subordinate processor 3 requests the memory transfer unit 11 to set the next value in the register 114 in order to transmit the fact to the main processor 2, and the transmission / reception unit 111 Is set in the register 114. At this time, the contents to be transmitted to the setting register can be freely set regardless of the contents of the pre-allocated registers such as the address and data length.

A special command indicating that the transfer to the memory 13 has been completed,
The start address of the storage destination of the memory 13,
・ Data length of transferred data

When a value is set in the register 114, the memory transfer unit 11 confirms that a special command has been issued from the subordinate processor 3, and asserts an interrupt signal from the control unit 112 to the main processor 2.
The main processor 2 has a plurality of external interrupt pins, and can specify which memory transfer unit 11 is the cause of the interrupt.
The main processor 2 detects which memory transfer unit 11 (subordinate processor 3) the interrupt is based on this interrupt factor, refers to the contents of the register 114, confirms the content transmitted from the subordinate processor 3, At the same time, the control unit 112 negates the interrupt signal.
Further, the main processor 2 transfers the data stored in the memory 13 to the recording medium 4 by the recording medium transfer unit 12 according to the transmission contents of the register 114, and ends a series of write processing.

(2) Reading data from the recording medium Next, in the case of reading the content stored in the recording medium from the application, the subordinate processor 3 that has received the processing request via the communication port designates from the content table. The start address of the storage destination of the recording medium 4 corresponding to the content number and the data length thereof are extracted. Here, the content table associates the content number with the start address and data length where the content is stored in the recording medium 4.

Hereinafter, the procedure executed by the processor 3 according to the processing content designated by the main processor 2 will be described with reference to the operation sequence diagram of FIG.
The slave processor 3 transmits a register setting request to the memory transfer unit 11 so as to set the next value in the register 114.
Read command for reading data from the recording medium into the main memory,
・ Start address where content is stored,
・ Content data length

The memory transfer unit 11 operates the transmission / reception unit 111 in response to the register setting request, and sets the above value in the register 114.
When a value is set in the register 114, the memory transfer unit 11 analyzes the contents of the register 114 and, when confirming that the command is a read command from the recording medium, asserts an interrupt signal from the control unit 112 to the main processor 2. .

When the main processor 2 detects an interrupt from the memory transfer unit 11 (subordinate processor 3), the main processor 2 refers to the content of the register 114 to confirm the transmission content, and at the same time, the control unit 112 negates the interrupt signal.
The main processor 2 transfers the information of the recording medium 4 to the memory 13 in accordance with the transmission contents of the register 114. When the transfer to the memory 13 is completed, the main processor 2 stores the information in the The contents to be transmitted such as the start address and data length of 13 storage destinations are set, and a bit is set in the interrupt generation register in the register 114.

When the main processor 2 confirms that a bit is set in the interrupt generation register, the memory transfer unit 11 asserts the interrupt signal from the transmission / reception unit 111 to the subordinate processor 3 through the bus.
When the slave processor 3 detects the interrupt, it recognizes that the transfer of information from the recording medium 4 to the memory 13 has been completed, refers to the contents of the register 114, confirms the transmission contents from the main processor 2, and At the same time, the transmission / reception unit 111 negates an interrupt signal to the subordinate processor 3.

  The slave processor 3 sets the start address of the data read into the memory 13 and the data length of the data in the register 114 according to the transmission contents of the register 114, as in the case of reading to a general drive. When a command is issued, reading from the memory 13 to the main memory is started. After the end of reading, a series of read processing ends.

  With the configuration as described above, the performance of information transfer between the main processor and the recording medium is not deteriorated, and the seek of the recording medium does not occur even when a plurality of processors access the recording medium at the same time. Each processor can share and access the recording medium.

In addition, it is possible to greatly reduce the amount of correction of hardware and software for each subordinate processor to perform IO control.
When there is content to be transmitted to the main processor by the subordinate processor, a specific command is issued to the transmission / reception unit in the memory transfer unit, and an interrupt signal is asserted to the main processor, thereby transmitting the fact to the main processor. be able to.

  In addition, when there is content to be transmitted from the main processor to the subordinate processor or from the subordinate processor to the main processor, both processors can access the shared register without using a communication interface such as GPIO, I2C, and VMI. Thus, communication between processors is possible.

  In addition, after the control unit in the memory transfer unit generates an interrupt to the main processor, the main processor can release the interrupt to the main processor by referring to the shared register.

  If there is content to be transmitted to the slave processor by the main processor, the transfer content is written to the shared register in the control unit in the memory transfer unit, and an interrupt signal is asserted to the slave processor, so that Can be transmitted.

It is a block diagram which shows the hardware constitutions of the recording medium control apparatus which concerns on embodiment. It is an operation | movement sequence diagram which shows the procedure of the write process to the recording medium of the subordinate processor in the recording medium control apparatus which concerns on embodiment. It is an operation | movement sequence diagram which shows the procedure of the read process to the recording medium of the subordinate processor in the recording medium control apparatus which concerns on embodiment. It is a block diagram which shows the conventional hardware constitutions. It is a block diagram which shows the conventional hardware constitutions.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Recording medium control apparatus, 2 ... Main processor, 3 ... Subordinate processor, 4 ... Recording medium, 11 ... Memory transfer part, 111 ... Transmission / reception part, 112 ... Control part, 113 ... Transfer part, 114 ... Register, 12 ... Recording medium transfer unit, 13 ... memory, 14 ... memory interface unit, 20, 30 ... recording medium, 21, 22, 31 ... CPU, 23, 32 ... bus.

Claims (8)

  A recording medium control apparatus for controlling a main processor and at least one or more subordinate processors to share a recording medium, and stores information exchanged between the subordinate processor and the recording medium. Memory, a memory interface unit for performing input / output processing to the memory, and the slave processor, and information exchanged between the slave processor and the memory via the memory interface unit. A recording medium control apparatus comprising: a memory transfer unit for transferring; and a recording medium transfer unit for transferring information exchanged between the memory and the recording medium in accordance with an instruction from the main processor.   2. The recording medium control apparatus according to claim 1, wherein when the memory transfer unit receives a transfer request to the memory from the subordinate processor, the memory interface unit transmits information transmitted from the subordinate processor. The recording medium control apparatus starts transfer to the memory via the recording medium.   3. The recording medium control device according to claim 2, wherein when the memory transfer unit receives the memory transfer request from the subordinate processor, the memory transfer unit sets a transmission content to the main processor in a specific register, and A recording medium control apparatus that asserts an interrupt signal to a main processor.   4. The recording medium control apparatus according to claim 3, wherein the memory transfer unit negates an interrupt signal to the main processor when the specific register is referred to by the main processor, and the main processor A recording medium control apparatus, wherein information stored in the memory is transferred to the recording medium via the recording medium transfer unit in accordance with the transmission contents set in the specific register.   2. The recording medium control device according to claim 1, wherein when the memory transfer unit receives a request for transferring information from the recording medium to the memory from the subordinate processor, the content transmitted to the main processor is transmitted to a specific register. A recording medium control apparatus that sets and asserts an interrupt signal to the main processor.   6. The recording medium control apparatus according to claim 5, wherein when the main processor detects an interrupt from the subordinate processor, information on the recording medium is stored in the recording medium according to a transmission content set in the specific register. The recording medium control apparatus according to claim 1, wherein the memory transfer unit negates an interrupt signal to the main processor when the contents of the specific register are referred to, while transferring to the memory via a transfer unit.   7. The recording medium control apparatus according to claim 6, wherein when the transfer of the information on the recording medium is completed, the main processor sets the content to be transmitted to the subordinate processor to a specific register, and stores in the memory transfer unit. A bit is set in the interrupt generation register for the slave processor, and the memory transfer unit asserts an interrupt signal for the slave processor when detecting that the bit is set in the interrupt generation register. Media control device.   8. The recording medium control device according to claim 7, wherein when the slave processor detects an interrupt, the slave processor starts transfer from the memory according to a transmission content set in the specific register, and the memory transfer unit A recording medium control apparatus characterized by negating an interrupt signal to the slave processor.

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