JP2007079942A - Data recording/reproducing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To continuously execute a plurality of steps to attain high-speed writing to a recording device by incorporating a sequencer-equipped control circuit controlling access to the recording device into a video recording/reproducing device. <P>SOLUTION: This data recording/reproducing device 1 has the sequencer-equipped control circuit 4 receiving access request from a CPU, automatically issuing a command, extending processing only while receiving an IORDY (wait) signal from the recording device 5, and capable of generating an interrupt to the CPU after the IORDY signal is released, so as to improve efficiency of the access when the access is not immediately accepted at power-on or the like. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data recording / reproducing apparatus, and more particularly to a data recording / reproducing apparatus having a control circuit with a sequencer as means for simplifying and speeding up access to a recording apparatus in a video data recording / reproducing apparatus.

  Conventional optical recording devices and magnetic recording devices are generally recording devices for recording data used by a high-speed microprocessor (CPU) such as a personal computer. In order to perform control with a relatively low-speed CPU, it is necessary to perform complicated processing for a long time.

  In recent years, DVD recorders and the like have increased demands for faster access to a recording device and improved responsiveness by performing dubbing at a high speed or simultaneously recording a plurality of television programs.

In order to speed up such processing, there are cases where a large amount of data buffer is provided and a plurality of HDDs (hard disk drives) are parallelized to increase the speed (see Patent Document 1).
JP 2002-354217 A

  In the data recording / reproducing apparatus, access such as writing and status confirmation are complicated, or the accessible unit is different, and it is necessary to simply change the access method without being able to copy. Such a problem has been a problem to simplify and speed up the processing.

  First, a description will be given of a problem when an access is performed immediately after power-on of a recording apparatus in a conventional data recording / reproducing apparatus.

  If the recording device cannot access within the time defined by the standard, it requests extension of the access time by returning an IORDY (wait) signal to the control circuit. Normally, the IORDY signal can be output only for a period determined by the standard. However, during initialization immediately after the power is turned on, it is necessary to continue outputting IORDY for a longer time than that specified by the standard. As a result, the CPU that has issued an access request to the control circuit waits for a very long time. Since the CPU cannot perform other tasks while waiting, the user who wants to perform recording or reproduction as soon as possible after turning on the power will wait.

  Next, a problem when data writing to a conventional recording apparatus and immediate buffer flushing are performed will be described.

  When data is stored in the buffer in the recording device, the recording device returns a response to the completion of data transfer or a response to a command for writing the data in the buffer to the immediate medium to the control circuit. However, the control circuit does not know whether the data stored in the buffer is actually written to the medium. In order to prevent the data in the buffer on the recording device from being lost due to a power failure or the like, it can be dealt with by generating a command for immediately writing the data in the buffer. In order to reliably record data in the recording device, it is only necessary to issue a command for instructing to immediately write the data in the buffer for each data write. On the other hand, if the write end notification or the access completion notification is performed, the data transfer speed becomes slower than when the buffer flush is not performed.

  Next, a description will be given of problems when data writing to the recording device and a writing check thereof are performed in the conventional data recording / reproducing device.

  In order to perform data transfer at high speed, it is necessary to confirm that there is sufficient free space in the buffer of the recording apparatus and then perform data transfer. Therefore, the remaining capacity of the buffer of the recording apparatus is confirmed. In an optical recording device or the like, since it takes a considerably longer time to transfer the buffer data to a DVD or the like, the CPU that issued an access request to the control circuit can only transfer the next data to the buffer of the recording device. Until it is confirmed that there is sufficient space, the remaining amount of the buffer is repeatedly checked. While accessing the control circuit to repeatedly check the free state of the buffer, the CPU cannot perform other operations. In order to transfer the next data as soon as the buffer is empty, if the empty state is frequently checked, the time for the CPU to be occupied for checking the free state becomes long, and data other than data writing The responsiveness of the recording / reproducing apparatus is lowered. Also, if the free state is not checked frequently, the time from when a sufficient free space is made in the buffer to the start of data transfer becomes long, and on average, the data transfer becomes slow.

  Next, a problem in writing data having a size that does not match the writing unit of the recording apparatus when writing data to the recording apparatus in the conventional data recording / reproducing apparatus will be described.

  For example, the recording apparatus can take only an integral multiple of 32 kilobytes as a unit of writing. The CPU tries to write, for example, 30 kilobytes of data stored in the RAM to address 0x0000 of the recording device. However, since the data writing unit of the recording device is 32 kilobytes, 2 kilobytes of data is first read from address 0x7800 of the recording device and stored in 0x7800 of the RAM. After that, 32 kilobytes of data in 0x0000 to 0x7FFF on the RAM is written.

  For example, in a DVD-RW drive which is one of optical recording devices, reading can be performed in units of 2 kilobytes, but writing is performed in units of 32 kilobytes. For this reason, when writing to a DVD-RW at high speed, even if the time required for reading and writing is the same, in order to write 30 kilobytes of data, 32 kilobytes are written after reading 2 kilobytes. Then, 34/30 times longer time is required for data transfer.

  In order to solve the above problems, in the present invention, the recording apparatus is accessed using a control circuit with a sequencer that can cause the recording apparatus to perform a sequential operation.

  More specifically, the invention described in claim 1 automates basic access such as status read access so that processing can be performed even when a wait signal longer than expected from the recording apparatus is generated. This realizes a function of confirming that the drive is accessible. That is, the present invention automatically issues a command in response to an access request from the CPU in order to improve the efficiency of access in a state where access cannot be immediately accepted, such as when the power is turned on, and IORDY from the recording device. A control circuit with a sequencer is provided which can extend the processing only while a (wait) signal is received and can generate an interrupt to the CPU after the IORDY signal is canceled.

  According to the second aspect of the present invention, the data transfer command and the command for operating and confirming the transferred data are stored as a single command by storing a plurality of steps and specifying a series of procedures. It is something to execute. That is, according to the present invention, by implementing means for executing a plurality of steps, for example, a data write command and a data write control / status confirmation command are generated, and an interrupt to the CPU is generated after completion of the command. A control circuit with a sequencer is provided.

  According to the third aspect of the present invention, data is written to the recording apparatus, the buffer state of the recording apparatus is confirmed after the writing, and the state confirmation is repeated until the state of the buffer becomes a specific state. In other words, the present invention checks the buffer status so as to check whether or not the data has been written to the recording device after the data transfer, and transfers the next data when a specific state is reached. It is.

  According to the fourth aspect of the present invention, data writing is performed, the buffer state is confirmed after the writing, and data writing is repeated according to the state of the data buffer until all data is written while confirming the state of the buffer. Is. That is, according to the present invention, after the data transfer, the status of the buffer is checked so as to check whether or not the data is written to the recording device, and the next data is transferred. As the data size to be transferred at that time, an optimum value is automatically selected according to the empty state of the buffer.

  The invention according to claim 5 implements a function of padding data to change the data size to be transferred and writing in order to match the data size to be transferred. That is, the present invention realizes a function of aligning transfer units by adding dummy data to data to be transferred in copying or the like in a recording apparatus in which the unit of data that can be handled cannot be arbitrarily set.

  The invention described in claim 6 realizes a function of merging data to be written with other data in order to fit the data size to be transferred. That is, the present invention realizes a function of aligning the transfer units by adding other data to the data to be transferred in copying or the like in a recording apparatus in which the unit of data that can be handled cannot be arbitrarily set. .

  According to the first aspect of the present invention, it is possible to automatically confirm the end of initialization in the case where the recording apparatus itself cannot satisfy the standard for performing the initializing operation immediately after the power is turned on. In this way, the video recording / reproducing apparatus can be activated at a high speed after the power is turned on.

  According to the second aspect of the present invention, when multiple accesses are made to the recording apparatus, a plurality of commands can be processed together. It makes it possible to lighten the load and achieve high speed access.

  According to the third aspect of the invention, in order to perform the recording operation at a high speed, it is necessary to check the buffer data so that the buffer overflow on the recording apparatus does not occur. Data can be written at high speed by promptly transferring and checking the status of the buffer on the recording device.

  According to the fourth aspect of the present invention, high-speed writing is enabled by continuing data writing when the empty state is in a specific state while checking the empty state of the buffer on the recording apparatus.

  According to the fifth aspect of the present invention, when the data to be transferred does not match the writing unit in the recording apparatus, the meaningless data is padded first from a specific part of the data to be written in the recording apparatus. Thus, the writing unit of the recording apparatus is adjusted. As a result, it is not necessary to perform read-modify-write or the like, so that data can be written at high speed.

  According to the sixth aspect of the present invention, when the data to be transferred does not match the writing unit in the recording apparatus, the data from another transfer source after the specific portion of the data to be written in the recording apparatus To match the writing unit of the recording device. As a result, it is not necessary to perform read-modify-write or the like, so that data can be written at high speed.

  FIG. 1 shows a configuration example of a data recording / reproducing apparatus according to the present invention. The data recording / reproducing apparatus in FIG. 1 includes a video recording / reproducing apparatus 1 and a recording apparatus 5. The video recording / reproducing apparatus 1 is controlled by the CPU 2 and records the recorded data stored in the RAM 3 on the recording apparatus 5 using the control circuit 4 with sequencer. The CPU 2, the RAM 3, and the control circuit with sequencer 4 are connected by a data bus 6 inside the video recording / reproducing apparatus 1. When reproducing, the data read from the recording device 5 using the control circuit 4 with sequencer is stored in the RAM 3. The control circuit with sequencer 4 and the recording device 5 are connected to each other by a standardized protocol called ATA or ATAPI.

  FIG. 2 shows a first configuration example of the control circuit with sequencer 4 in FIG. The control circuit with sequencer 4 in FIG. 2 includes a step execution unit 7 that is in charge of command transmission, data transfer, and response reception to the recording device 5 and a sequence storage unit 8 that stores a sequence set by the CPU 2. . The sequence storage unit 8 includes a first step storage unit 9 and a second step storage unit 10.

  FIG. 3 is a control flow diagram based on the first sequence by the control circuit with sequencer 4 of FIG. Here, it is assumed that the following sequence information is stored in the first step storage unit 9 in FIG.

  First step: Read the status, and wait for the IORDY signal to be released when the IORDY signal is received. After canceling the IORDY signal, the CPU 2 is notified of the completion of status reading as an interrupt.

  According to FIG. 3, the CPU 2 accesses the control circuit 4 with sequencer to set the sequence in the first step storage unit 9 in order to confirm the presence / absence of connection of the recording device 5 and the operating state of the recording device 5. I do. The control circuit with sequencer 4 performs status read access to the recording device 5 based on the sequence stored in the first step storage unit 9. The status register is accessed for the recording apparatus 5 during the initialization operation. At this time, since the recording device 5 is executing the initialization operation, the recording device 5 cannot complete the access within the time defined by the standard with respect to the access from the control circuit with sequencer 4 and outputs the IORDY signal. Delay the response to return the status. When the response from the recording device 5 is returned, the control circuit with sequencer 4 terminates the sequence stored in the sequence storage unit 8 to generate an interrupt to the CPU 2 and sends the status read result to the CPU 2. return.

  FIG. 4 is a control flow diagram based on the second sequence by the control circuit with sequencer 4 of FIG. Here, it is assumed that the following sequence information is stored in the first step storage unit 9 and the second step storage unit 10 in FIG.

  First step: DMA write is performed. When the data transfer is completed, the process proceeds to the second step.

  Second step: A flash cache command is issued. The CPU 2 is notified of the completion of the flash cache command as an interrupt.

  According to FIG. 4, data is written to the recording device 5 as the first step, and when the first step is completed, a buffer on the recording device 5 called flash cache is written as the second step. To do.

  FIG. 5 is a control flow diagram based on the third sequence by the control circuit with sequencer 4 of FIG. Here, it is assumed that the following sequence information is stored in the first step storage unit 9 and the second step storage unit 10 in FIG.

  First step: DMA write is performed. When the data transfer is completed, the process proceeds to the second step.

  Second step: A read buffer capacity command is issued. When the empty information of the buffer on the recording device 5 is confirmed, the CPU 2 is notified as an interrupt.

  According to FIG. 5, data writing to the recording device 5 is performed as the first step, and when the first step is completed, a command called read buffer capacity is issued as the second step, and the buffer on the recording device 5 is vacant. When the status is checked, the CPU 2 is notified.

  6 and 7 are control flowcharts based on the fourth sequence by the control circuit with sequencer 4 of FIG. Here, it is assumed that the following sequence information is stored in the first step storage unit 9 and the second step storage unit 10 in FIG.

  First step: DMA write is performed. If the DMA write ends with OK, the process proceeds to the second step. If the DMA write ends with NG (error), the CPU 2 is interrupted to end.

  Second step: A flash cache command is issued. If the flash cache command is OK and all data to be transferred has been transferred, the CPU 2 is interrupted and the process ends. If the flash cache command is OK and data to be transferred remains, the transfer start address and the transfer length are changed and the process returns to the first step. If the flash cache command ends with NG, the CPU 2 is interrupted to end.

  According to FIG. 6, when an error does not occur when the buffer on the recording device 5 is flushed, the operation is repeated until the condition to be terminated is satisfied according to the setting of the sequence storage unit 8.

  FIG. 7 shows a case where the repetitive operation is interrupted halfway according to the setting of the sequence storage unit 8 when an error occurs as a result of the flush.

  FIG. 8 is a control flow diagram based on the fifth sequence by the control circuit with sequencer 4 of FIG. Here, it is assumed that the following sequence information is stored in the first step storage unit 9 and the second step storage unit 10 in FIG.

  First step: DMA write is performed. When the data transfer is completed, the process proceeds to the second step.

  Second step: Issue a read buffer capacity command. When all the data transfer is completed, the CPU 2 is interrupted to complete the transfer. If there is still data to be transferred, (the next transfer start address) = (the transfer start address in the previous first step) + ( Returning to the first step, assuming (previous data transfer amount), (next transfer data amount) = (free buffer capacity).

  According to FIG. 8, whether or not the transfer data is written to the medium and whether or not there is a buffer available for writing the next data to the buffer is checked by issuing a read capacity command, and the size of the buffer free area is checked. As a response. DMA write is performed again using the available space size. Issuance of a DMA write command and issuance of a read capacity command are repeated until transfer of all data is completed. When transfer of all data is completed, the CPU 2 is interrupted and the process ends.

  FIG. 9 shows a second configuration example of the control circuit with sequencer 4 in FIG. The control circuit with sequencer 4 in FIG. 9 includes a comparator 11 in the sequence storage unit 8 in addition to the first and second step storage units 9 and 10.

  FIG. 10 is a control flow diagram based on the first sequence by the control circuit with sequencer 4 of FIG. Here, it is assumed that the following sequence information is stored in the first step storage unit 9 and the second step storage unit 10 in FIG.

  First step: DMA write is performed. When the data transfer is completed, the process proceeds to the second step.

  Second step: A read buffer capacity command is issued. If the buffer space acquired by the read buffer capacity command becomes larger than the set value, the CPU 2 is interrupted and the process is terminated. If there is less space than the set value, the second step is repeated.

  According to FIG. 10, by writing a read capacity command to check whether there is a buffer available for writing the written data to the medium and writing the next data to the buffer, Get the size of as a response. The available space size obtained is compared with the value set in the sequence storage unit 8 by the comparator 11. The read capacity command is repeatedly issued until the free space size becomes larger than the set value. When the free space size becomes larger than the set value, the CPU 2 is interrupted and notified.

  FIG. 11 is a control flow diagram based on the second sequence by the control circuit with sequencer 4 of FIG. Here, it is assumed that the following sequence information is stored in the first step storage unit 9 and the second step storage unit 10 in FIG.

  First step: DMA write is performed. When the data transfer is completed, the process proceeds to the second step.

  Second step: A read buffer capacity command is issued. When all data transfer is completed, the CPU 2 is interrupted and the process is terminated. If there is still data to be transferred and the free space of the buffer obtained by the read buffer capacity command is larger than the set value, (next transfer start address) = (first previous address) Transfer start address in step) + (previous data transfer amount), (next transfer data amount) = (data amount set by CPU 2) and return to the first step. If data to be transferred remains and if there is less space than the set value, the second step is repeated.

  According to FIG. 11, the written data is written to the medium, and whether or not there is a buffer available for writing the next data to the buffer, the size of the free area of the buffer is determined by issuing a read capacity command. Get it as a response. The available space size obtained is compared with the value set in the sequence storage unit 8 by the comparator 11. If the size of the free area is smaller than the set value, issue of the read capacity command is repeated. When the free area size becomes larger than the set value, the process returns to the first step to execute DMA write. When all the data has been transferred, the CPU 2 is interrupted and the process ends.

  FIG. 12 shows a third configuration example of the control circuit with sequencer 4 in FIG. The sequencer-equipped control circuit 4 of FIG. 12 includes a dummy data switching unit 12 in the sequence storage unit 8 in addition to the first and second step storage units 9 and 10. The recording device 5 uses an integral multiple of 32 kilobytes as the writing block size.

  FIG. 13 is a data transfer diagram from the RAM 3 to the recording device 5 by the control circuit with sequencer 4 of FIG. Here, it is assumed that the following sequence information is stored in the first step storage unit 9 and the second step storage unit 10 in FIG.

  First step: DMA write is performed. When the data transfer is completed up to the set data length, the process proceeds to the second step.

  Second step: Dummy data is written in the recording device 5. When the data has been transferred to the set data length, the CPU 2 is interrupted and the process ends.

  According to FIG. 13, the CPU 2 tried to write the 30 kilobyte data stored in the RAM 3 to the address 0x0000 of the recording device 5. In response to this, 30 kilobytes of data sent from the RAM 3 is written to the recording device 5 in the first step, and 2 kilobytes are written to the recording device 5 as dummy data in the second step.

  Here, the RAM 3 is assumed as the data transfer source, but the transfer source may be another recording device or a circuit that performs some format conversion. This is effective for all cases in which extra data is added when the condition cannot be satisfied with only the data to be written because the device to be written has restrictions.

  FIG. 14 shows a fourth configuration example of the control circuit with sequencer 4 in FIG. The control circuit with sequencer 4 in FIG. 14 includes a transfer source switching unit 13 in the sequence storage unit 8 in addition to the first and second step storage units 9 and 10. The recording device 5 uses an integral multiple of 32 kilobytes as the writing block size.

  FIG. 15 is a data transfer diagram from the RAM 3 to the recording device 5 by the control circuit 4 with sequencer in FIG. Here, it is assumed that the following sequence information is stored in the first step storage unit 9 and the second step storage unit 10 in FIG.

  First step: DMA write is performed. When the data transfer is completed up to the set data length, the process proceeds to the second step.

  Second step: The DMA write is performed by switching the transfer source of the data to be written. When the data has been transferred to the set data length, the CPU 2 is interrupted and the process ends.

  According to FIG. 15, the CPU 2 tried to write 158 kilobytes of data stored in the RAM 3 to the address 0x00000 of the recording device 5, but the data writing unit of the recording device 5 was 32 kilobytes. In addition, 158 kilobytes from the address 0x00000 on the RAM 3 are written to the recording device 5, and then 2 kilobytes from 0x40000 are written to the recording device 5.

  Here, the RAM 3 is assumed as a data transfer source, but the transfer source may be another recording device or a circuit that performs some format conversion. Further, by using the data read from the recording device 5 on the RAM 3 before writing, it can be used like read-modify-write. In addition, a portion to which data of another transfer source is added can be added to the first half instead of being added to the second half of the data to be written. By adding to both the first half, the second half, and both the first half and the second half, it is possible not only to adjust that the transfer data does not match the write unit, but also the write start address is aligned with the boundary of the write unit. Can also be used to adjust when not.

  In each of the above-described embodiments, the configuration example having two step storage units in the control circuit with sequencer 4 is shown. However, in the case of sufficient control by one step, the control circuit 4 with a sequencer is configured by one step storage unit, One step may be executed, or when control is performed in three or more steps, it may be configured by three or more step storage units and three or more steps may be executed. . In the above description, the main purpose is to increase the speed of the dubbing operation. However, even when a plurality of programs are recorded simultaneously, the effect of high speed and high response can be obtained.

  As described above, the data recording / reproducing apparatus according to the present invention has a function of reducing the processing of the processor and realizing high-speed combined processing, and is useful as a home video recording apparatus. It can also be applied to applications such as personal computers, printers, and copiers.

It is a block diagram which shows the structural example of the data recording / reproducing apparatus which concerns on this invention. It is a block diagram which shows the 1st structural example of the control circuit with a sequencer in FIG. FIG. 3 is a control flow diagram based on a first sequence by the control circuit with a sequencer in FIG. 2. FIG. 3 is a control flow diagram based on a second sequence by the control circuit with a sequencer in FIG. 2. It is a control flow figure based on the 3rd sequence by the control circuit with a sequencer of FIG. It is a control flow figure in the case of no error based on the 4th sequence by the control circuit with a sequencer of FIG. It is a control flow figure in the case of an error based on the 4th sequence by the control circuit with a sequencer of FIG. It is a control flow figure based on the 5th sequence by the control circuit with a sequencer of FIG. It is a block diagram which shows the 2nd structural example of the control circuit with a sequencer in FIG. FIG. 10 is a control flow diagram based on a first sequence by the control circuit with a sequencer in FIG. 9. FIG. 10 is a control flow diagram based on a second sequence by the control circuit with a sequencer in FIG. 9. FIG. 4 is a block diagram illustrating a third configuration example of the control circuit with a sequencer in FIG. 1. FIG. 13 is a data transfer diagram from the RAM to the recording device by the control circuit with a sequencer in FIG. 12. FIG. 6 is a block diagram illustrating a fourth configuration example of the control circuit with a sequencer in FIG. 1. FIG. 15 is a data transfer diagram from the RAM to the recording device by the control circuit with a sequencer in FIG. 14.

Explanation of symbols

1 Video recording / reproducing device 2 CPU
3 RAM
4 control circuit with sequencer 5 recording device 6 data bus 7 step execution unit 8 sequence storage unit 9 first step storage unit 10 second step storage unit 11 comparator 12 dummy data switching unit 13 transfer source switching unit

Claims (6)

A recording device for storing data to be reproduced;
A CPU that issues an access request to the recording device;
In response to a status read access request from the CPU, there is provided a control circuit with a sequencer that waits for cancellation of a signal requesting extension of the access time from the recording device and returns a status read result to the CPU. Characteristic data recording / reproducing apparatus. A recording device for storing data to be reproduced;
A CPU that issues an access request to the recording device;
A control circuit with a sequencer for controlling access to the recording device interposed between the CPU and the recording device;
The control circuit with a sequencer is
A sequence storage unit for storing a plurality of steps;
A data recording / reproducing apparatus comprising: a step execution unit that executes the steps stored in the sequence storage unit. A recording device for storing data to be reproduced;
A CPU that issues an access request to the recording device;
A control circuit with a sequencer for controlling access to the recording device interposed between the CPU and the recording device;
The control circuit with a sequencer is
A sequence storage unit for storing a step of writing data and a step of checking a buffer state after writing;
A data recording / reproducing apparatus comprising: a step execution unit that executes the steps stored in the sequence storage unit. A recording device for storing data to be reproduced;
A CPU that issues an access request to the recording device;
A control circuit with a sequencer for controlling access to the recording device interposed between the CPU and the recording device;
The control circuit with a sequencer is
A step of writing data; a step of checking the buffer state of the recording device after writing; and a sequence storage unit having a comparator for comparing the buffer state of the recording device with a set value;
A data recording / reproducing apparatus comprising: a step execution unit that executes the steps stored in the sequence storage unit. A recording device for storing data to be reproduced;
A CPU that issues an access request to the recording device;
A control circuit with a sequencer for controlling access to the recording device interposed between the CPU and the recording device;
The control circuit with a sequencer is
Storing a step of writing data and a step of writing dummy data, and a sequence storage unit having a dummy data switching unit;
A data recording / reproducing apparatus comprising: a step execution unit that executes the steps stored in the sequence storage unit. A recording device for storing data to be reproduced;
A CPU that issues an access request to the recording device;
A control circuit with a sequencer for controlling access to the recording device interposed between the CPU and the recording device;
The control circuit with a sequencer is
A sequence storage unit that stores a step of performing a plurality of data writing and has a transfer source switching unit that switches data to be written,
A data recording / reproducing apparatus comprising: a step execution unit that executes the steps stored in the sequence storage unit.

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