JP2005528717A5 - - Google Patents

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Publication number
JP2005528717A5
JP2005528717A5 JP2003529478A JP2003529478A JP2005528717A5 JP 2005528717 A5 JP2005528717 A5 JP 2005528717A5 JP 2003529478 A JP2003529478 A JP 2003529478A JP 2003529478 A JP2003529478 A JP 2003529478A JP 2005528717 A5 JP2005528717 A5 JP 2005528717A5
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JP
Japan
Prior art keywords
refresh
memory
count
response
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2003529478A
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English (en)
Japanese (ja)
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JP2005528717A (ja
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Publication date
Priority claimed from US10/242,878 external-priority patent/US20030053361A1/en
Application filed filed Critical
Publication of JP2005528717A publication Critical patent/JP2005528717A/ja
Publication of JP2005528717A5 publication Critical patent/JP2005528717A5/ja
Withdrawn legal-status Critical Current

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JP2003529478A 2001-09-20 2002-09-19 Ｅｄｒａｍベースアーキテクチャ Withdrawn JP2005528717A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US32401301P 2001-09-20 2001-09-20
US10/242,878 US20030053361A1 (en) 2001-09-20 2002-09-11 EDRAM based architecture
PCT/US2002/030000 WO2003025947A2 (en) 2001-09-20 2002-09-19 Edram based architecture

Publications (2)

Publication Number Publication Date
JP2005528717A JP2005528717A (ja) 2005-09-22
JP2005528717A5 true JP2005528717A5 (enExample) 2006-01-05

Family

ID=26935419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003529478A Withdrawn JP2005528717A (ja) 2001-09-20 2002-09-19 Ｅｄｒａｍベースアーキテクチャ

Country Status (6)

Country Link
US (1) US20030053361A1 (enExample)
JP (1) JP2005528717A (enExample)
BR (1) BR0212659A (enExample)
CA (1) CA2461018A1 (enExample)
RU (1) RU2004111785A (enExample)
WO (1) WO2003025947A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7590021B2 (en) * 2007-07-26 2009-09-15 Qualcomm Incorporated System and method to reduce dynamic RAM power consumption via the use of valid data indicators
US20090144507A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US8024513B2 (en) * 2007-12-04 2011-09-20 International Business Machines Corporation Method and system for implementing dynamic refresh protocols for DRAM based cache
US7882302B2 (en) * 2007-12-04 2011-02-01 International Business Machines Corporation Method and system for implementing prioritized refresh of DRAM based cache
US7962695B2 (en) * 2007-12-04 2011-06-14 International Business Machines Corporation Method and system for integrating SRAM and DRAM architecture in set associative cache
US20090144504A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US8108609B2 (en) * 2007-12-04 2012-01-31 International Business Machines Corporation Structure for implementing dynamic refresh protocols for DRAM based cache
CN103559142B (zh) * 2013-11-05 2017-03-08 中国科学院声学研究所 动态随机访问存储器的刷新方法
US10811076B1 (en) * 2019-06-29 2020-10-20 Intel Corporation Battery life based on inhibited memory refreshes

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148546A (en) * 1991-04-22 1992-09-15 Blodgett Greg A Method and system for minimizing power demands on portable computers and the like by refreshing selected dram cells
IL121044A (en) * 1996-07-15 2000-09-28 Motorola Inc Dynamic memory device

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