JP2005513612A - 有限状態機械制御コードを選択的に用いるプロセッサアーキテクチャ - Google Patents
有限状態機械制御コードを選択的に用いるプロセッサアーキテクチャ Download PDFInfo
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- JP2005513612A JP2005513612A JP2003553412A JP2003553412A JP2005513612A JP 2005513612 A JP2005513612 A JP 2005513612A JP 2003553412 A JP2003553412 A JP 2003553412A JP 2003553412 A JP2003553412 A JP 2003553412A JP 2005513612 A JP2005513612 A JP 2005513612A
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- 230000015654 memory Effects 0.000 claims description 20
- 230000006870 function Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 3
- 230000004044 response Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims 1
- 238000013459 approach Methods 0.000 abstract description 11
- 238000013461 design Methods 0.000 description 10
- 238000012545 processing Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 3
- 241001076195 Lampsilis ovata Species 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
Abstract
Description
本出願は、概して、デジタルプロセッシングに関し、より詳細には、プロセッサの電力消費を減少させるデジタルプロセッサマイクロアーキテクチャに関する。
本発明の1つの実施形態は、マイクロコード命令(「マイクロ命令」)キャッシュとの組み合わせで有限状態機械を用いる。通常、頻繁にループされる演算の短いシーケンスを生じる選択された命令は、有限状態機械(FSM)で実装される。FSMを使用することは、キャッシュまたはレジスタセットの命令をループさせることよりもよりエネルギー効率が良い。さらに、マイクロコード命令の実行において、キャッシュ、または他のメモリ指向アプローチの柔軟性が依然として利用可能である。
Claims (11)
- マイクロ命令に応答して、演算を実行するデジタルプロセッサであって、該デジタルプロセッサは、
実行されるべき該演算に関連するデータを格納するメモリと、
該演算に関連する関数を実行する有限状態機械(FSM)と、
レジスタにデータを提供して、該マイクロ命令に応答して該FSMの実行を開始する制御回路と
を含む、デジタルプロセッサ。 - 前記メモリに格納された前記データに繰り返してアクセスするループ制御回路をさらに含む、請求項1に記載のデジタルプロセッサ。
- 前記制御回路は、マイクロ命令のうちの少なくとも一部が前記FSMによって実施されているかを決定するID検出回路を含む、請求項1に記載のデジタルプロセッサ。
- 複数のFSMをさらに含み、前記制御回路は、該複数のFSMのうちの1つ以上の演算を選択的に呼び出すFSM実行回路を含む、請求項1に記載のデジタルプロセッサ。
- 設定可能なFSMをさらに含み、前記制御回路は、前記マイクロ命令に関連する所定の関数のために設定されるように該設定可能なFSMを導く設定回路を含む、請求項1に記載のデジタルプロセッサ。
- 前記メモリは、レジスタを含む、請求項1に記載のデジタルプロセッサ。
- 前記メモリは、マイクロ格納装置を含む、請求項1に記載のデジタルプロセッサ。
- 前記メモリは、キャッシュを含む、請求項1に記載のデジタルプロセッサ。
- マイクロ命令を実行するコンピュータプロセッサであって、該コンピュータプロセッサは、
有限状態機械(FSM)と、
反復レジスタと、
該FSMおよび該反復レジスタを制御して、該マイクロ命令のうちの少なくとも1つを実施する制御回路と
を含む、コンピュータプロセッサ。 - 前記FSMおよび前記反復レジスタは、同時に演算される、請求項9に記載のコンピュータプロセッサ。
- マイクロ命令を実行する方法であって、該方法は、有限状態機械と反復レジスタとの両方を用いて、該マイクロ命令によって示された関数のうちの少なくとも一部を1つを実施するステップを包含する、方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/022,776 US7231508B2 (en) | 2001-12-13 | 2001-12-13 | Configurable finite state machine for operation of microinstruction providing execution enable control value |
PCT/US2002/039574 WO2003052591A2 (en) | 2001-12-13 | 2002-12-10 | Processor architecture selectively using finite-state-machine for control code |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008186582A Division JP2009032257A (ja) | 2001-12-13 | 2008-07-17 | 有限状態機械制御コードを選択的に用いるプロセッサアーキテクチャ |
Publications (1)
Publication Number | Publication Date |
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JP2005513612A true JP2005513612A (ja) | 2005-05-12 |
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JP2003553412A Withdrawn JP2005513612A (ja) | 2001-12-13 | 2002-12-10 | 有限状態機械制御コードを選択的に用いるプロセッサアーキテクチャ |
JP2008186582A Pending JP2009032257A (ja) | 2001-12-13 | 2008-07-17 | 有限状態機械制御コードを選択的に用いるプロセッサアーキテクチャ |
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JP2008186582A Pending JP2009032257A (ja) | 2001-12-13 | 2008-07-17 | 有限状態機械制御コードを選択的に用いるプロセッサアーキテクチャ |
Country Status (5)
Country | Link |
---|---|
US (2) | US7231508B2 (ja) |
JP (2) | JP2005513612A (ja) |
AU (1) | AU2002363987A1 (ja) |
TW (1) | TWI289785B (ja) |
WO (1) | WO2003052591A2 (ja) |
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TW200821923A (en) * | 2006-11-08 | 2008-05-16 | Ite Tech Inc | Data processing apparatus for loop operation and method thereof |
ATE463788T1 (de) * | 2007-06-26 | 2010-04-15 | Ericsson Telefon Ab L M | Datenverarbeitungseinheit für anweisungen in geschachtelten schleifen |
TWI432953B (zh) | 2010-12-09 | 2014-04-01 | Ind Tech Res Inst | 具電源管理之超長指令處理器以及其電源管理裝置與方法 |
US9626333B2 (en) | 2012-06-02 | 2017-04-18 | Intel Corporation | Scatter using index array and finite state machine |
US11269643B2 (en) * | 2017-04-09 | 2022-03-08 | Intel Corporation | Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values |
CN114138341B (zh) * | 2021-12-01 | 2023-06-02 | 海光信息技术股份有限公司 | 微指令缓存资源的调度方法、装置、程序产品以及芯片 |
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2002
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TWI289785B (en) | 2007-11-11 |
TW200300904A (en) | 2003-06-16 |
US20030115553A1 (en) | 2003-06-19 |
WO2003052591A2 (en) | 2003-06-26 |
WO2003052591A3 (en) | 2003-12-04 |
JP2009032257A (ja) | 2009-02-12 |
AU2002363987A1 (en) | 2003-06-30 |
US7231508B2 (en) | 2007-06-12 |
AU2002363987A8 (en) | 2003-06-30 |
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