JP2005348040A5 - - Google Patents

Claims (11)

Two-dimensionally arranged pixels;
A first signal output line for reading out signals from a plurality of pixels arranged in the first row among the pixels arranged in the first pixel column;
A second signal output line for reading out signals from a plurality of pixels arranged in a second row among the pixels arranged in the first pixel column;
A first capacitive element for holding a signal from the first signal output line;
A second capacitive element for holding a signal from the second signal output line;
First switch means for electrically connecting one end of the first capacitive element and one end of the second capacitive element on the first and second signal output line sides;
A solid-state imaging device, wherein the other end of the first capacitive element and the other end of the second capacitive element are electrically connected to each other. The solid-state imaging device according to claim 1, wherein the first row is an even row and the second row is an odd row. The first signal output line is connected to one end of the first capacitive element via second switch means, and the second signal output line is connected to the second capacitive element via third switch means. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is connected to one end of the solid-state imaging device. Scanning means for scanning the first, second and third switch means;
The scanning means includes
During the all-row readout operation, scanning is performed so that the second switch unit and the third switch unit are sequentially turned on during the period in which the first switch unit is on. 4. The scanning is performed so as to have a period in which the second switch means and the third switch means are simultaneously turned on while the first switch means is turned off. Solid-state imaging device. An amplifying circuit for amplifying signals held by the first and second capacitive elements;
The amplifier circuit includes an amplifier having a capacitance that capacitively couples an output terminal and an input terminal, and a gain is determined by a capacitance ratio between the first and second capacitance elements and the capacitance. the solid-state imaging device according to any one of claims 1-4. 6. The solid-state imaging device according to claim 5 , further comprising a memory unit that holds an output signal of the amplifier and includes memory cells arranged corresponding to at least some of the plurality of pixels. The memory cell capacitance at least signal is written, a solid according to claim 6, characterized in that the amplification type memory cell comprising transistors, and a transistor for amplifying the signal for writing the signal Imaging device. It is arranged for each column of the amplification type memory cells of the memory unit, and has circuit means for outputting an output offset between the amplifier and the amplification type memory cell and a signal from the amplification type memory cell. The solid-state imaging device according to claim 7 . The circuit means stores a first storage capacitor for storing the output offset, a first transfer transistor for transferring the output offset to the first storage capacitor, and a first storage transistor for storing a signal from the amplification type memory cell. The solid-state imaging device according to claim 8 , further comprising: a storage capacitor of 2 and a second transfer transistor that transfers a signal from the amplification type memory cell to the second storage capacitor. The solid-state imaging device according to claim 9 having means for finding a difference between said output from the circuit means, said signal and said output offset. It has a solid-state imaging device, comprising: a lens system for focusing light to the solid-state imaging device, a signal processing circuit for processing an output signal from the solid-state imaging device in any one of claims 1-10 An imaging system characterized by the above.