JP2005347468A - Nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory, big in a memorizing capacity and low in a bit cost, with a low cost. <P>SOLUTION: The nonvolatile memory is provided with a plurality of electrode layers. A plurality of electrodes 121, 122, 123, 124..., are arranged in parallel with spaces in the substantially same plane on respective electrode layers. The electrodes 121, 123..., arranged on the odd number electrode layers are substantially orthogonal to the electrodes 122, 124..., arranged on the even number electrode layers, while metallic oxides 131, 132..., whose values of electric resistance are changed by an electric means are provided between the electrodes of continuous number electrode layers. Excluding the electrodes on the lowermost stage and the uppermost stage, both of the electrodes 121, 123..., on the odd number electrode layers and the electrodes 122, 124..., on the even number electrode layers are connected to the metallic oxides 131, 132..., provided on both surfaces of these electrodes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electrically operated memory, and more particularly to a non-volatile memory that does not require a power source for recording retention.

  In recent years, due to the rapid development of an advanced information society, the need to handle high-speed and large-capacity data is increasing. In order to store the data, realization of a high-speed nonvolatile memory is expected.

  As a nonvolatile memory, a flash memory and a ferroelectric memory (referred to as FRAM) have already been put on the market, and a memory card used in a mobile phone, a digital camera (referred to as DSC) and the like has been rapidly advanced. Moreover, the unit price per 1 Mbyte has already dropped below 0.15 US dollars, and the capacity has been doubled and the cost has been reduced by half. Until now, the market for memory cards has been expanded as a storage medium for data storage for portable audio devices such as MP3 players and DSCs.

  Recently, for example, it has been used as a bridge medium used for exchanging data between devices such as a program recorded on a DVD recorder or a television set and played back on a mobile phone or portable information device via a memory card. I came. This is a substitute for a wired or wireless network, and can be handled by a user with a more intuitive operation than using a network, and is less expensive than using a paid network such as a mobile phone.

  Furthermore, not only data storage memory but also development of memory cards equipped with application software and most hardware functions has begun to be considered. In this case, it is not necessary to install not only memory and software, but also most of the hardware in the set device, and the device can be made smaller, lighter and thinner.

  Against this background, the nonvolatile memory is required to further reduce the bit cost (larger capacity, lower cost) and higher speed.

  Conventionally, for example, a three-dimensional semiconductor memory having a multi-stage column portion as a memory cell has been taught, as described in, for example, published patent publication “Japanese Patent Publication No. 2002-530850”. The prior art will be described below with reference to the drawings.

  FIG. 7 is a cross-sectional view of a conventional three-dimensional semiconductor nonvolatile memory. A second conductor 42 is disposed orthogonal to the first conductor 41 of FIG. 7, and the column portion 43 of the memory cell is located in all vertical portions where the first conductor 41 and the second conductor 42 intersect. It is formed. A third conductor 44 is disposed perpendicular to the second conductor 42, and the column portion 43 of the memory cell is formed everywhere the second conductor 42 and the third conductor 44 intersect. Similarly, odd-numbered conductors extend in one direction, even-numbered conductors extend in a direction perpendicular thereto, and the memory cell pillar portion is formed three-dimensionally between these conductors.

FIG. 8 shows a perspective view of the memory cell 50 of this conventional three-dimensional semiconductor nonvolatile memory. A column portion 53 of the memory cell sandwiched between mutually perpendicular conductors 51 and 52 is constituted by a steering portion 54 made of a diode or the like and a state change portion 55 made of an antifuse or the like.
Japanese translation of PCT publication No. 2002-530850

  However, in the conventional three-dimensional nonvolatile memory, the memory cell of the pillar portion is configured by the steering unit and the state change unit, so that the process cost is high and it is difficult to reduce the bit cost.

  An object of the present invention is to provide a nonvolatile memory with an increased recording capacity at a low cost.

  The nonvolatile memory according to the present invention includes a substrate, a first electrode layer provided on the substrate, a first recording layer provided on the first electrode layer, and the first recording layer. A second electrode layer provided on the second layer, a second recording layer provided on the second electrode layer, and a third electrode layer provided on the second recording layer And a third recording layer provided on the third electrode layer, and a fourth electrode layer provided on the third recording layer, wherein the first to fourth electrodes Each of the layers includes a plurality of conductors arranged in parallel to each other, and each of the first to third recording layers includes a metal oxide whose electrical resistance value changes in response to a given electrical means. The plurality of conductors included in the first electrode layer are electrically connected to the metal oxide included in the first recording layer, and the second electrode layer The plurality of conductors included are electrically connected to the metal oxide included in the first recording layer and the metal oxide included in the second recording layer, and are included in the third electrode layer. The plurality of conductors electrically connected to the metal oxide included in the second recording layer and the metal oxide included in the third recording layer are included in the fourth electrode layer. The plurality of conductors are electrically connected to a metal oxide included in the third recording layer.

  When recording information in the non-volatile memory, one of the plurality of conductors (first conductor) included in one electrode layer (for example, the second electrode layer) is selected, and this electrode layer One of the plurality of conductors (second conductor) included in the electrode layer immediately above or immediately below (for example, the third electrode layer) is selected, and an electric current is generated between the first conductor and the second conductor. Give the right means. In response to this electrical means, the metal oxide included in the recording layer (for example, the second recording layer) provided between these two electrode layers is sandwiched between the first conductor and the second conductor. The electrical resistance value of the region (the region where the perpendicular from the first conductor intersects the second conductor) changes. Information is recorded using the change in the electrical resistance value. That is, a region sandwiched between the first conductor and the second conductor functions as a memory cell (memory region). As described above, in the nonvolatile memory, since the memory cell (memory region) is formed only of the metal oxide layer, an effect of increasing the storage capacity at a low cost (lowering the bit cost) can be obtained.

  In the non-volatile memory, one of a plurality of conductors (first conductor) included in one electrode layer among the first to fourth electrode layers, and immediately above the one electrode layer Alternatively, the electrical means is provided between one of the plurality of conductors (second conductor) included in the electrode layer immediately below, and the first conductor of the first to fourth electrode layers is One of the plurality of conductors (third conductor) included in the electrode layer immediately above or immediately below the included electrode layer includes the first conductor and the third conductor among the first to third recording layers. A voltage is applied to prevent the metal oxide contained in the recording layer provided between the first and fourth electrode layers from being affected by the electrical means, and the second of the first to fourth electrode layers. One of the plurality of conductors included in the electrode layer immediately above or immediately below the electrode layer including the conductor (the fourth conductor). ), The metal oxide contained in the recording layer provided between the second conductor and the fourth conductor among the first to third recording layers is affected by the electrical means. It is preferable to apply a voltage to prevent this.

  In the nonvolatile memory, the plurality of conductors included in the first electrode layer and the plurality of conductors included in the second electrode layer intersect each other, and a plurality of conductors included in the second electrode layer The conductor and the plurality of conductors included in the third electrode layer intersect each other, and the plurality of conductors included in the third electrode layer and the plurality of conductors included in the fourth electrode layer are mutually It is preferable that they intersect.

  The nonvolatile memory includes an insulating layer instead of the second recording layer, and the insulating layer includes a plurality of conductors included in the second electrode layer and a plurality of conductors included in the third electrode layer. Are preferably electrically insulated from each other.

  In the nonvolatile memory, the electrical means is preferably a voltage pulse or a current pulse.

  In the non-volatile memory, the electrical means is preferably a DC voltage or a DC current.

  In the non-volatile memory, the electrical means is preferably an alternating voltage or an alternating current.

  In the above nonvolatile memory, it is preferable that the metal oxide contained in at least one of the first to third recording layers is composed of one film.

  In the above nonvolatile memory, the metal oxide included in at least one of the first to third recording layers is composed of a plurality of films that are spaced apart from each other in substantially the same plane. Is preferable.

  In the nonvolatile memory, the metal oxide preferably has a perovskite structure.

  The metal oxide having a perovskite structure is preferably one of a ferroelectric material, a super giant magnetoresistive (CMR) material, and a high temperature superconducting (HTSC) material.

  The metal oxide having a perovskite structure is preferably any one of strontium barium titanate, strontium zirconate, calcium praseodymium manganate, and barium calcium gadolinium cobaltate.

  The metal oxide having a perovskite structure preferably contains at least one additive element of chromium, vanadium, scandium, or other transition metals.

  In the nonvolatile memory, the metal oxide preferably has an ilmenite structure.

  The metal oxide having an ilmenite structure is preferably a ferroelectric material.

  The metal oxide having an ilmenite structure is preferably lithium niobate or lithium tantalate containing at least one additive element of magnesium, indium, scandium, zinc, copper, and iron.

  The concentration of the additive element is preferably more than 0 mol% and 10 mol% or less.

  In the nonvolatile memory, the metal oxide preferably has a spinel structure.

  The metal oxide having the spinel structure is preferably any of magnesium titanate, chromium magnesium acid, aluminum magnesium acid, and iron cobaltate.

  In the above nonvolatile memory, the plurality of conductors are preferably made of a material that does not form a compound with the metal oxide.

  In the nonvolatile memory, it is preferable that the plurality of conductors are made of a material that does not diffuse or chemically react with the metal oxide.

  In the nonvolatile memory, it is preferable that the plurality of conductors are made of any one of platinum, silver, and iridium.

  In the nonvolatile memory, the substrate is preferably made of silicon.

  In the non-volatile memory, the surface of the substrate is preferably covered with silicon oxide.

  The nonvolatile memory preferably further includes an adhesion layer formed between the substrate and the first electrode layer.

  The adhesion layer is preferably composed of any one of titanium, tantalum, titanium oxide, and tantalum oxide.

  In the nonvolatile memory, the uppermost electrode layer is preferably covered with an insulator.

  The insulator is preferably aluminum oxide or silicon oxide.

  According to the nonvolatile memory of the present invention, since the memory cell (memory region) is formed only of the metal oxide layer, an effect of increasing the storage capacity at a low cost (lowering the bit cost) can be obtained.

  Hereinafter, a nonvolatile memory according to an embodiment of the present invention will be described with reference to the drawings. In the drawings, substantially the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing the configuration of the nonvolatile memory 10 according to the first embodiment. In this three-dimensional nonvolatile memory 10, an electrode layer 1 is formed on a substrate 11 made of silicon or silicon whose surface is covered with silicon oxide. In the electrode layer 1, a plurality of electrodes (conductors) 121 are arranged in parallel at intervals in a substantially same plane. A recording layer 1 is formed on the electrode layer 1. The recording layer 1 is composed of a continuous layer (one film) 131 of metal oxide whose electric resistance value changes in response to an applied electrical means. An electrode layer 2 is formed on the recording layer 1. In the electrode layer 2, a plurality of electrodes (conductors) 122 are arranged in parallel and spaced apart in substantially the same plane. The plurality of electrodes 121 disposed on the electrode layer 1 and the plurality of electrodes 122 disposed on the electrode layer 2 are substantially orthogonal to each other.

  On the electrode layer 2, a recording layer 2, an electrode layer 3, a recording layer 3, an electrode layer 4, a recording layer 4,. The recording layers 2, 3,... Are composed of continuous layers (one film) 132, 133,... Of metal oxide whose electric resistance changes in response to an applied electrical means. A plurality of electrodes (conductors) 123, 124,... Are arranged on the electrode layers 3, 4,. The plurality of electrodes 123,... Arranged in the odd-numbered electrode layers and the plurality of electrodes 122, 124,... Arranged in the even-numbered electrode layers are generally orthogonal to each other, Metal oxide continuous layers 132, 133, 134,..

  With the exception of the lowermost electrode 121 and the uppermost electrode, both the electrodes in the odd-numbered electrode layers and the electrodes in the even-numbered electrode layers are metal oxides provided on both surfaces (upper and lower recording layers) of these electrodes. It is electrically connected to the object.

  The thickness of each electrode 121,122, ... and each metal oxide film 131,132, ... is preferably 10 nm to 1 µm, and the thickness of the silicon oxide is preferably 0.1 to 1 µm.

  The metal oxides 131, 132,... Are metal oxides whose electrical resistance value is changed by applying electrical means such as voltage pulse or current pulse, DC voltage or DC current, AC voltage or AC current. Those having a crystal structure such as a perovskite structure, an ilmenite structure, or a spinel structure are preferable.

  In the case of having a perovskite structure, it is at least one of a ferroelectric material, a supergiant magnetoresistive (CMR) material, and a high temperature superconducting (HTSC) material. It is preferably at least one of calcium praseodymium oxide and barium calcium gadolinium cobaltate. Further, it may contain at least one additional element of chromium, vanadium, scandium, or other transition metals.

  When it has an ilmenite structure, it is preferably a ferroelectric material, and is lithium niobate or lithium tantalate containing at least one additional element of magnesium, indium, scandium, zinc, copper, and iron. Is preferred.

  Further, when the metal oxides 131, 132,... Have a perovskite type structure or an ilmenite type structure, the concentration of the additive element is preferably more than 0 mol% and not more than 10 mol%.

  Moreover, when it has a spinel type structure, it is preferable that it is at least any one among magnesium titanate, chromium magnesium acid, aluminum magnesium acid, and iron cobaltate.

  The electrodes 121, 122,... Are a material that does not form a compound with the metal oxides 131, 132,..., Or a material that does not diffuse or chemically react with the metal oxide, and are at least one of platinum, silver, and iridium. Is preferred.

  These electrodes 121, 122,... Themselves are word lines or bit lines, or are connected to word lines or bit lines. When the electrodes 121, 123,... In the odd-numbered electrode layers are word lines or connected to the word lines, are the electrodes 122, 124,. Connected to bit line. In the opposite case, the electrodes 121, 123,... In the odd-numbered electrode layers are bit lines themselves or connected to the bit lines, and the electrodes 122, 124,. Or connected to a word line.

  Then, by applying an electric means such as a voltage pulse or a current pulse between the electrodes, the electric resistance value of the metal oxide in the region in contact with these electrodes is changed, and the high resistance state is changed to logic “0”. Save the digital information by associating the low resistance state with a logic “1”. That is, continuous layers 131, 132, 133, 134. . . The area in contact with each other becomes a memory cell.

  2A, for example, as shown in FIG. 2B, in the metal oxide film 131 of the recording layer 1, the electrode 121 of the electrode layer 1 and the electrode 122 of the electrode layer 2 are shown. Of the recording layer 2, the region M 2 of the recording layer 2 in contact with both the electrode 122 of the electrode layer 2 and the electrode 123 of the electrode layer 3. In the metal oxide film 133, each region M3 in contact with both the electrode 123 of the electrode layer 3 and the electrode 124 of the electrode layer 4 is a memory cell. The memory cells M1 to M3 and the electrodes 121 to 124 can be simplified as shown in FIG. An example of the recording / reading operation will be described using this simplified notation.

  When information is recorded in the memory cell M2, as shown in FIG. 3A, the ground voltage GND is applied to the electrodes 121 and 124, and the voltage (−Ecc) is applied to the electrode 123. In this state, a storage pulse having an amplitude (+ Ecc) is applied to the electrode 122. As a result, a voltage pulse having an amplitude (2 Ecc) is applied to the memory cell M2 (metal oxide film region M2). The metal oxide film in the present embodiment has a characteristic that its electric resistance value changes when a voltage pulse having an amplitude larger than a predetermined threshold value Th (Ecc <Th <2Ecc) is given. Therefore, the electric resistance value of the memory cell M2 (metal oxide film region M2) is changed by this voltage pulse. Alternatively, as shown in FIG. 3B, a ground voltage GND may be applied to the electrodes 121 and 124, a voltage Ecc may be applied to the electrode 123, and a storage pulse having an amplitude (−Ecc) may be applied to the electrode 122 in this state. . 3A and 3B, a voltage pulse having an amplitude (2 Ecc) is applied to the memory cell M2 (metal oxide film region M2), but the polarity of the voltage pulse is different. The relationship between the polarity of the voltage pulse to be applied and the change (increase / decrease) in the resistance value, the amplitude of the voltage pulse, and the like are described in detail in the prior application “Japanese Patent Application No. 2003-435269” by the applicant of the present application. In FIGS. 3A and 3B, since the ground voltage GND is applied to the electrodes 121 and 124, the voltage applied to the memory cells M1 and M3 (metal oxide film regions M1 and M3) is as described above. It becomes smaller than the threshold value Th. As a result, the inconvenience that the memory cells M1 and M3 are affected by the application of the voltage pulse to the memory cell M2 (such as the resistance value changing) can be avoided.

  On the other hand, when information is read from the memory cell M2, the ground voltage GND is applied to the electrodes 123 and 124 and the voltage Ecc is applied to the electrodes 121 and 122, as shown in FIG. In this state, information is read from the memory cell M2 by reading the voltage or current level between the electrodes 122 and 123. Alternatively, as shown in FIG. 3D, the ground voltage GND is applied to the electrodes 123 and 124, the voltage (-Ecc) is applied to the electrodes 121 and 122, and the voltage or current level between the electrodes 122 and 123 is read in this state. As a result, information is read from the memory cell M2. The voltage applied at the time of reading is also described in detail in the prior application “Japanese Patent Application No. 2003-435269” by the present applicant. 3C and 3D, since the voltage Ecc or -Ecc is applied to the electrode 121 and the ground voltage GND is applied to the electrode 124, the memory cells M1, M3 (metal oxide film regions M1, M3) are applied. No voltage or current is applied to. This avoids the disadvantage that the voltage or current level between the electrodes 122 and 123 is changed by the voltage and / or current applied to the memory cells M1 and M3.

  As described above, unlike the conventional three-dimensional nonvolatile memory, the nonvolatile memory according to the first embodiment does not require the pillar portion memory cell to be configured by the steering portion and the state change portion, and is made of a metal oxide. Since it can be formed of a continuous layer, the process cost can be further reduced and the bit cost can be reduced.

(Embodiment 2)
FIG. 4 is a cross-sectional view showing a configuration of the nonvolatile memory 20 according to the second embodiment. In this nonvolatile memory 20, the recording layers 1, 2, 3,... Are composed of discontinuous layers 231, 232, 233, etc. of metal oxides whose electrical resistance values change in response to given electrical means. This is different from the nonvolatile memory 10 of FIG. As shown in FIG. 4, each recording layer 1, 2, 3,... Is a region sandwiched between a plurality of electrodes included in the electrode layer immediately above and a plurality of electrodes included in the electrode layer immediately below (the electrode layer immediately above The metal oxide film is formed only in a region where the perpendicular from the electrode included in the electrode intersects the electrode included in the electrode layer immediately below.

  Thus, by comprising a metal oxide by a discontinuous layer, compared with the case of the metal oxide which consists of a continuous layer of Embodiment 1, the space | interval of the several electrode arrange | positioned in parallel substantially in the same plane Even when the voltage becomes extremely narrow, the effect of crosstalk between memory cells can be reduced.

(Embodiment 3)
FIG. 5 is a cross-sectional view showing the configuration of the nonvolatile memory 30 according to the third embodiment. In the nonvolatile memory 30, an adhesion layer 34 made of titanium, tantalum, titanium oxide, tantalum oxide, or the like is formed between the substrate 11 and the lowermost electrode layer 1. The thickness of the adhesion layer 34 is preferably 10 nm to 100 nm. The uppermost electrode layer (n + 1) is covered with an insulator 35 such as aluminum oxide or silicon oxide. This is different from the nonvolatile memory 10 of FIG.

  As described above, since the adhesion layer 34 is provided in the nonvolatile memory 30 of Embodiment 3, the adhesion strength between the substrate 11 and the electrode 121 of the lowermost electrode layer 1 is improved, and the uppermost electrode layer is increased. Since (n + 1) is covered with the insulator 35, the reliability of the nonvolatile memory element can be improved.

  Although the case where the metal oxide is a continuous layer has been described here, the same effect can be obtained even when the metal oxide is a discontinuous layer as described in Embodiment 2.

(Embodiment 4)
FIG. 6A is a cross-sectional view showing the configuration of the nonvolatile memory 40 according to the fourth embodiment. In this nonvolatile memory 40, an electrode layer 1, a recording layer 1, and an electrode layer 2 are formed on a substrate 11. An insulating layer 36 is formed on the electrode layer 2. On this insulating layer 36, the electrode layer 3, the recording layer 2, and the electrode layer 4 are formed. As described above, the nonvolatile memory 40 according to Embodiment 4 has a configuration in which the insulating layer 36 is formed every time the unit of (electrode layer−recording layer−electrode layer) is repeated. 6A, the electrodes 122 and 123 of the electrode layers 2 and 3 adjacent to the upper and lower sides of the insulating layer 36 are orthogonal to each other, but are adjacent to the upper and lower sides of the insulating layer 36 as shown in FIG. 6B. The electrodes 122 and 123 of the electrode layers 2 and 3 may be arranged in parallel to each other.

  By providing the insulating layer 36 in this manner, the metal oxide 132 of another recording layer (for example, the recording layer 2) is applied by applying electrical means to the metal oxide (131) of a certain recording layer (for example, the recording layer 1). Can be avoided (for example, the resistance value changes).

  As shown in the third embodiment, an adhesion layer such as titanium, tantalum, titanium oxide, tantalum oxide or the like is preferably formed between the substrate 11 and the lowermost electrode layer 1. The uppermost electrode layer (n + 1) is preferably covered with an insulator such as aluminum oxide or silicon oxide.

  Although the case where the metal oxide is a continuous layer has been described here, the same effect can be obtained even when the metal oxide is a discontinuous layer as described in Embodiment 2.

  According to the present invention, a low-cost and large-capacity (low bit cost) nonvolatile memory can be realized. If this nonvolatile memory is used, a set device can be reduced in size, weight, and thickness.

It is sectional drawing which shows the structure of the non-volatile memory which concerns on Embodiment 1 of this invention. FIG. 2 is a diagram for explaining a recording / reading operation of the nonvolatile memory shown in FIG. 1. FIG. 2 is a diagram for explaining a recording / reading operation of the nonvolatile memory shown in FIG. 1. It is sectional drawing which shows the structure of the non-volatile memory which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the structure of the non-volatile memory which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the structure of the non-volatile memory which concerns on Embodiment 4 of this invention. It is sectional drawing of the conventional three-dimensional semiconductor non-volatile memory. FIG. 8 is a perspective view of the memory cell of FIG.

Explanation of symbols

10, 20, 30, 40 Nonvolatile memory 11 Substrate 121, 122, 123, 124 Electrode 131, 132, 133, 134, 231, 232, 233, 234 Metal oxide 34 Adhesion layer 35 Insulator

Claims (28)

A substrate,
A first electrode layer provided on the substrate;
A first recording layer provided on the first electrode layer;
A second electrode layer provided on the first recording layer;
A second recording layer provided on the second electrode layer;
A third electrode layer provided on the second recording layer;
A third recording layer provided on the third electrode layer;
A fourth electrode layer provided on the third recording layer,
Each of the first to fourth electrode layers includes:
Including a plurality of conductors arranged parallel to each other;
Each of the first to third recording layers is
Including a metal oxide whose electrical resistance value changes in response to a given electrical means,
The plurality of conductors included in the first electrode layer are electrically connected to the metal oxide included in the first recording layer,
The plurality of conductors included in the second electrode layer are electrically connected to the metal oxide included in the first recording layer and the metal oxide included in the second recording layer,
The plurality of conductors included in the third electrode layer are electrically connected to the metal oxide included in the second recording layer and the metal oxide included in the third recording layer,
The plurality of conductors included in the fourth electrode layer are electrically connected to the metal oxide included in the third recording layer.
A non-volatile memory characterized by that. In claim 1,
One of a plurality of conductors (first conductor) included in one electrode layer among the first to fourth electrode layers, and an electrode layer directly above or immediately below the one electrode layer Providing the electrical means to one of the plurality of included conductors (second conductor);
Of the first to fourth electrode layers, one of the plurality of conductors (third conductor) included in the electrode layer immediately above or directly below the electrode layer including the first conductor includes the first conductor layer. To a voltage for preventing the metal oxide contained in the recording layer provided between the first conductor and the third conductor of the third recording layer from being affected by the electrical means. Give,
Among the first to fourth electrode layers, one of the plurality of conductors (fourth conductor) included in the electrode layer immediately above or immediately below the electrode layer including the second conductor is the first conductor. To a voltage for preventing the metal oxide contained in the recording layer provided between the second conductor and the fourth conductor of the third recording layer from being affected by the electrical means. give,
A non-volatile memory characterized by that. In claim 1,
The plurality of conductors included in the first electrode layer and the plurality of conductors included in the second electrode layer intersect each other,
The plurality of conductors included in the second electrode layer and the plurality of conductors included in the third electrode layer intersect each other,
A plurality of conductors included in the third electrode layer and a plurality of conductors included in the fourth electrode layer cross each other;
A non-volatile memory characterized by that. In claim 1,
An insulating layer instead of the second recording layer;
The insulating layer is
The plurality of conductors included in the second electrode layer and the plurality of conductors included in the third electrode layer are electrically insulated.
A non-volatile memory characterized by that. In claim 1,
The electrical means is
Voltage pulse or current pulse,
A non-volatile memory characterized by that. In claim 1,
The electrical means is
DC voltage or DC current,
A non-volatile memory characterized by that. In claim 1,
The electrical means is
AC voltage or AC current,
A non-volatile memory characterized by that. In claim 1,
The metal oxide contained in at least one of the first to third recording layers is composed of one film.
A non-volatile memory characterized by that. In claim 1,
The metal oxide contained in at least one of the first to third recording layers is composed of a plurality of films that are spaced apart from each other in substantially the same plane.
A non-volatile memory characterized by that. In claim 1,
The metal oxide has a perovskite structure;
A non-volatile memory characterized by that. In claim 10,
The metal oxide is
One of a ferroelectric material, a giant magnetoresistive (CMR) material, a high temperature superconducting (HTSC) material,
A non-volatile memory characterized by that. In claim 10 or 11,
The metal oxide is
It is one of strontium barium titanate, strontium zirconate, praseodymium calcium manganate, barium calcium gadolinium cobaltate,
A non-volatile memory characterized by that. In claim 12,
The metal oxide is
Containing at least one additional element of chromium, vanadium, scandium or other transition metals,
A non-volatile memory characterized by that. In claim 1,
The metal oxide has an ilmenite type structure,
A non-volatile memory characterized by that. In claim 14,
The metal oxide is a ferroelectric material;
A non-volatile memory characterized by that. In claim 14 or 15,
The metal oxide is
Lithium niobate or lithium tantalate containing at least one additive element of magnesium, indium, scandium, zinc, copper, iron,
A non-volatile memory characterized by that. In claim 13 or 16,
The concentration of the additive element is more than 0 mol% and not more than 10 mol%.
A non-volatile memory characterized by that. In claim 1,
The metal oxide has a spinel structure,
A non-volatile memory characterized by that. In claim 18,
The metal oxide is
It is one of magnesium titanate, chromium magnesium oxide, aluminum magnesium acid, iron cobaltate,
A non-volatile memory characterized by that. In claim 1,
The plurality of conductors are:
Composed of a material that does not form a compound with the metal oxide,
A non-volatile memory characterized by that. In claim 1,
The plurality of conductors are:
Composed of a material that does not diffuse or chemically react with the metal oxide,
A non-volatile memory characterized by that. In claim 1,
The plurality of conductors are:
Composed of either platinum, silver or iridium,
A non-volatile memory characterized by that. In claim 1,
The substrate is made of silicon;
A non-volatile memory characterized by that. In claim 1 or 23,
The surface of the substrate is coated with silicon oxide;
A non-volatile memory characterized by that. In claim 1,
An adhesive layer formed between the substrate and the first electrode layer;
The non-volatile memory according to claim 1. In claim 25,
The adhesion layer is composed of any one of titanium, tantalum, titanium oxide, and tantalum oxide.
A non-volatile memory characterized by that. In claim 1,
The uppermost electrode layer is covered with an insulator,
A non-volatile memory characterized by that. In claim 27,
The insulator is aluminum oxide or silicon oxide;
A non-volatile memory characterized by that.

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