JP2007149170A - Nonvolatile memory circuit and its drive method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile memory in which influence of read-out disturbance and write-in disturbance in a nonvolatile memory having three dimensional structure is prevented and reliability is high, and which has high speed, large memory capacity, and a low bit cost. <P>SOLUTION: A potential of voltage applied to word lines and bit lines connected to memory cells is decided considering voltage threshold in which an electric resistance of a valuable resistance material constituting memory cells is changed rapidly. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electrically operated memory, and more particularly, to a nonvolatile memory circuit that does not require a power source for recording and a driving method thereof.

  In recent years, due to the rapid development of an advanced information society, the need to handle high-speed and large-capacity data is increasing. In order to store the data, realization of a high-speed nonvolatile memory is expected.

  As a nonvolatile memory, a flash memory and a ferroelectric memory (referred to as FRAM) have already been put on the market, and a memory card used in a mobile phone, a digital camera (referred to as DSC) and the like has been rapidly advanced. Moreover, the unit price per 1 Mbyte has already dropped below 0.15 US dollars, and the capacity has been doubled and the cost has been reduced by half. Until now, the market for memory cards has been expanded as a storage medium for data storage for portable audio devices such as MP3 players and DSCs.

  Recently, for example, it has been used as a bridge medium used for exchanging data between devices such as a program recorded on a DVD recorder or a television set and played back on a mobile phone or portable information device via a memory card. I came. This is a substitute for a wired or wireless network, and can be handled by a user with a more intuitive operation than using a network, and is less expensive than using a paid network such as a mobile phone.

  Furthermore, not only data storage memory but also development of memory cards equipped with application software and most hardware functions has begun to be considered. In this case, it is not necessary to install not only the memory and software, but also most of the hardware in the set device, and the device can be made smaller, lighter and thinner.

  Against this background, the nonvolatile memory is required to further reduce the bit cost (larger capacity, lower cost) and higher speed.

  Conventionally, a cross-point memory array with high integration and a three-dimensional memory array with high density and high integration by vertically stacking cross-point memories have been proposed. For example, it is described in “Patent No. 3639786” As described above, a three-dimensional semiconductor memory having a multi-stage column portion as a memory cell is taught. The prior art will be described below with reference to the drawings.

  FIG. 12 is a cross-sectional view of a conventional three-dimensional semiconductor nonvolatile memory 40. A second conductor 42 is arranged orthogonal to the first conductor 41 of FIG. 12, and the column portion 43 of the memory cell is formed in all vertical portions where the first conductor 41 and the second conductor 42 intersect. Is done. A third conductor 44 is disposed orthogonal to the second conductor 42, and the column portion 43 of the memory cell is formed at all locations where the second conductor 42 and the third conductor 44 intersect. Similarly, odd-numbered conductors extend in one direction, even-numbered conductors extend in a direction orthogonal thereto, and a column portion of the memory cell is formed three-dimensionally between these conductors.

FIG. 13 shows a perspective view of the memory cell 50 of this conventional three-dimensional semiconductor nonvolatile memory. The column portion 53 of the memory cell sandwiched between the conductors 51 and 52 orthogonal to each other includes a steering portion 54 made of a diode or the like and a state change portion 55 made of an antifuse or the like.
Japanese Patent No. 3639786

  However, in the conventional three-dimensional nonvolatile memory, the memory cell of the pillar portion is configured by the steering portion and the state change portion, so that the process cost is high and it is difficult to reduce the bit cost.

  The cost can be reduced by removing the steering part from the memory cell in the pillar part and only the state change part. However, the memory cell can be reduced only by the state change part by removing the steering part made of a diode or the like. In a write / read operation, a leakage current path to a memory cell adjacent to the memory cell to be accessed (particularly, a memory cell immediately above or immediately below the memory cell adjacent to the memory cell to be accessed) occurs. There is a problem in that a write disturb occurs during a write operation and a correct write operation cannot be performed, and a read disturb occurs during a read operation, and a correct current value cannot be evaluated during the read operation.

  Therefore, as shown in FIG. 14, in order to avoid a leakage current path to the memory cell immediately above or directly below the memory cell to be accessed (memory cell-conductor composed only of the conductor-state change portion) A nonvolatile memory in which an insulator is formed each time a unit is repeated has been proposed.

  FIG. 14A is a cross-sectional view showing a configuration of the nonvolatile memory 60 in which an insulator is formed. In the nonvolatile memory 60, a conductor 1, a memory cell 1, and a conductor 2 are formed on a substrate 11. An insulator 61 is formed on the conductor 2. On the insulator 61, the conductor 3, the memory cell 2, and the conductor 4 are formed. As described above, the nonvolatile memory 60 is configured such that the insulator 61 is formed every time the unit of (memory cell-conductor formed only of the conductor-state change portion) is repeated.

  In FIG. 14A, the conductors 2 and 3 adjacent to the top and bottom of the insulator 61 are orthogonal to each other. However, as shown in FIG. 14B, the conductors 2 and 3 adjacent to the top and bottom of the insulator 61 are You may arrange | position in parallel.

  By providing the insulator 61 in this manner, the variable resistance material 622 of another memory cell (for example, the memory cell 2) is affected by the application of electrical means to the variable resistance material 621 of a certain memory cell (for example, the memory cell 1). Inconvenience (such as resistance value changes) can be avoided.

  Leakage current paths to the memory cell immediately above or directly below the memory cell adjacent to the memory cell to be accessed by forming an insulator each time the unit of (memory-conductor composed of only the conductor-state change portion-conductor) is repeated However, in this case, since it is necessary to form an insulator, there arises a problem that the process cost becomes high and it is difficult to reduce the bit cost.

  In view of the above problems, the object of the present invention is to avoid the influence of read disturb and write disturb in a three-dimensional memory using a variable resistance material such as a metal oxide or a chalcogenide compound, write operation, reset operation, And a driving method capable of performing a read operation using a similar voltage control circuit, and providing a highly reliable, high-speed, large-capacity nonvolatile memory at low cost.

  The nonvolatile memory circuit of the present invention includes a plurality of first electrodes including bit lines arranged at intervals in substantially the same plane, and a plurality of word lines arranged at intervals in substantially the same plane. Of the first electrode and the variable resistance material sandwiched between the first electrode and the second electrode, the first electrode and the second electrode intersecting each other and arranged in a plurality of stages Memory array having original structure, word line drive circuit connected to memory array and applying voltage to word line of memory array, and bit line drive circuit connected to memory array and applying voltage to bit line of memory array And a control circuit that is connected to the word line driving circuit and the bit line driving circuit and controls the word line driving circuit and the bit line driving circuit, wherein the control circuit has a first specified value in the selected variable resistance material. Apply voltage, The resistance value of the selected variable resistance material is increased / decreased by controlling the word line driving circuit and the bit line driving circuit so as to apply the voltage of the second specified value to the variable resistance material that is not selected. It is characterized by making it.

  Here, the “variable resistance material” has a characteristic that the resistance value of the variable resistance material changes when a voltage such as a DC voltage or a pulse voltage under a predetermined condition (polarity, amplitude, pulse width, etc.) is applied. Material.

  The nonvolatile memory circuit of the present invention includes a plurality of first electrodes including bit lines arranged at intervals in substantially the same plane, and word lines arranged at intervals in substantially the same plane. A plurality of second electrodes and a variable resistance material sandwiched between the first electrodes and the second electrodes, and the first electrodes and the second electrodes are arranged in a plurality of stages so as to cross each other. A memory array having a three-dimensional structure, a word line driving circuit connected to the memory array and applying a voltage to the word line of the memory array, and a bit line driving connected to the memory array and applying a voltage to the bit line of the memory array And a control circuit connected to the word line driving circuit and the bit line driving circuit for controlling the word line driving circuit and the bit line driving circuit, wherein the control circuit has a third regulation for the selected variable resistance material. Mark the value voltage And by controlling the word line driving circuit and the bit line driving circuit so as not to apply a voltage to the unselected variable resistance material connected to the word line to which the selected variable resistance material is connected. The resistance value of the selected variable resistance material is read.

  Furthermore, a word line driving circuit of a nonvolatile memory circuit according to the present invention includes a pulse generation circuit that generates a pulse voltage, a specified value setting circuit that sets a first specified value, a second specified value, and a third specified value, The word line driving circuit or the bit line driving circuit preferably further includes a current detection circuit for detecting a current flowing through the variable resistance material.

  The nonvolatile memory circuit driving method of the present invention is characterized in that the variable resistance material constituting the memory cell is a metal oxide or a chalcogenide compound, and the metal oxide has a perovskite structure, an ilmenite structure, and a spinel structure. Preferably, the chalcogenide compound contains germanium, antimony, and tellurium, and further contains germanium, antimony, and tellurium, and indium, gallium, bismuth. More preferably, it contains at least one additive element among aluminum, tin, lead, boron, carbon, silicon, and lanthanoid elements.

  When the metal oxide has a perovskite structure, it is preferably at least one of a ferroelectric material, a super giant magnetoresistive (CMR) material, and a high temperature superconducting (HTSC) material. Strontium titanate More preferably, it is at least one of barium strontium titanate, strontium zirconate, praseodymium calcium manganate, and barium calcium gadolinium cobaltate.

  Furthermore, the metal oxide having a perovskite structure may contain at least one or more additive elements of niobium, chromium, vanadium, scandium or other transition metals.

  Further, when the metal oxide has an ilmenite structure, it is preferably a ferroelectric material, and niobic acid containing at least one additional element of magnesium, indium, scandium, zinc, copper, and iron. More preferably, it is lithium or lithium tantalate.

  When the metal oxide has a spinel structure, magnesium titanate, chromium magnesium oxide, nickel chromate, aluminum magnesium oxide, aluminum vanadate, iron cobaltate, iron oxide, copper / iron oxide (copper ferrite) ), Zinc / iron oxide, manganese / iron oxide, or nickel / iron oxide.

  Further, the metal oxide is iron oxide, copper oxide, nickel oxide, cobalt oxide, titanium oxide, niobium oxide, zirconium oxide, tungsten oxide, hafnium oxide, aluminum oxide, It is preferably at least one of them.

  A method of driving a nonvolatile memory circuit according to the present invention includes a plurality of first electrodes including bit lines arranged at intervals in substantially the same plane, and word lines arranged at intervals in substantially the same plane. A plurality of second electrodes, and a variable resistance material sandwiched between the first electrode and the second electrode, the first electrode and the second electrode intersecting each other to form a plurality of stages In a non-volatile memory circuit having a three-dimensional structure, a voltage having a first specified value is applied to a selected variable resistance material, and a voltage having a second specified value is applied to a non-selected variable resistance material. By applying, the resistance value of the selected variable resistance material is increased / decreased.

  At this time, the voltage applied to the word line connected to the selected variable resistance material and the bit line other than the bit line connected to the selected variable resistance material have the same potential, and the selected variable resistance The bit line connected to the material is connected to the selected variable resistance material by applying a voltage whose potential difference from the word line connected to the selected variable resistance material is the first specified value. It is preferable to apply a voltage at which a potential difference with respect to a voltage applied to the bit line connected to the selected variable resistance material is the second specified value to a word line other than the word line.

  The voltage applied to the word line connected to the selected variable resistance material and the bit line other than the bit line connected to the selected variable resistance material have the same potential, and the selected variable resistance material The voltage potential applied to the word line connected to the selected variable resistance material is set to be lower than the voltage potential applied to the bit line connected to the selected variable resistance material. The voltage applied to the bit line other than the bit line connected to the word line connected to the selected variable resistance material and the bit line connected to the selected variable resistance material is reduced to a value, and the selected The voltage potential applied to the word line connected to the variable resistance material is set higher than the voltage potential applied to the bit line connected to the selected variable resistance material. It is preferable to increase the resistance of the variable resistance material said selected.

  At this time, the word line connected to the selected variable resistance material is set to 0 V (GND level) to reduce the resistance value of the selected variable resistance material, and is connected to the selected variable resistance material. It is preferable to set the bit line to 0 V (GND level) to increase the resistance value of the selected variable resistance material.

  In addition, the driving method of the nonvolatile memory circuit of the present invention is arranged with a plurality of first electrodes including bit lines arranged at intervals in substantially the same plane and at intervals in substantially the same plane. A plurality of second electrodes including a word line; and a variable resistance material sandwiched between the first electrode and the second electrode, wherein the first electrode and the second electrode intersect each other In a non-volatile memory circuit having a three-dimensional structure arranged in stages, a voltage of a third specified value is applied to a selected variable resistance material and connected to a word line to which the selected variable resistance material is connected The resistance value of the selected variable resistance material is read by applying no voltage to the unselected variable resistance material.

  At this time, the voltage applied to the word line to which the selected variable resistance material is connected and the unselected variable resistance material connected to the word line to which the selected variable resistance material is connected are connected. The voltage applied to the selected bit line has the same potential, the voltage applied to the word line adjacent to the word line to which the selected variable resistance material is connected, and the selected variable resistance material The voltage applied to the bit line connected to the same is the same potential, and the word line connected to the selected variable resistance material has a potential difference from the bit line connected to the selected variable resistance material. It is preferable to read the resistance value of the selected variable resistance material by applying a voltage that is the third specified value.

  At this time, it is preferable to set the bit line connected to the selected variable resistance material to 0 V (GND level) and read the resistance value of the variable resistance material.

  Further, the first specified value is a voltage value equal to or higher than a threshold at which the electric resistance value of the variable resistance material rapidly changes, and the second specified value is an electric resistance value of the variable resistance material. Preferably, the third specified value is a voltage value less than the threshold at which the electric resistance value of the variable resistance material changes abruptly. The voltage is preferably a pulse voltage.

  According to the nonvolatile memory circuit and the driving method of the nonvolatile memory circuit according to the present invention, in a three-dimensional memory using a metal oxide or chalcogenide compound having a structure such as perovskite, ilmenite, and spinel as a variable resistance material, A highly reliable high-speed and large-capacity nonvolatile memory that avoids the effects of read disturb and write disturb can be provided at low cost.

  Furthermore, according to the nonvolatile memory circuit and the driving method of the nonvolatile memory according to the present invention, the write operation, the reset operation, and the read operation can be performed using the same voltage control circuit.

Hereinafter, a nonvolatile memory circuit and a nonvolatile memory according to embodiments of the present invention will be described with reference to the drawings. In the drawings, substantially the same members are denoted by the same reference numerals, and the description thereof will not be repeated.
(Embodiment 1)
FIG. 1 is a cross-sectional view showing the configuration of the nonvolatile memory 10 according to the first embodiment. In this nonvolatile memory 10, the electrode layer 1 is formed on a substrate 11 such as silicon or silicon whose surface is covered with silicon oxide. In the electrode layer 1, a plurality of electrodes (conductors) 121 are arranged in parallel at intervals in a substantially same plane. A recording layer 1 made of a variable resistance material is formed on the electrode layer 1. The recording layer 1 is composed of a continuous layer (one film) 131 of a variable resistance material such as a metal oxide or a chalcogenide compound whose electric resistance value changes in response to an applied electrical means. An electrode layer 2 is formed on the recording layer 1. In the electrode layer 2, a plurality of electrodes (conductors) 122 are arranged in parallel and spaced apart in substantially the same plane. The plurality of electrodes 121 disposed on the electrode layer 1 and the plurality of electrodes 122 disposed on the electrode layer 2 are substantially orthogonal to each other.

  On the electrode layer 2, a recording layer 2, an electrode layer 3, a recording layer 3, an electrode layer 4, a recording layer 4,. The recording layers 2, 3,... Are composed of continuous layers (one film) 132, 133,... Of a variable resistance material such as a metal oxide or a chalcogenide compound whose electrical resistance value changes in response to given electrical means. ing. A plurality of electrodes (conductors) 123, 124,... Are arranged on the electrode layers 3, 4,. The plurality of electrodes 123,... Arranged in the odd-numbered electrode layers and the plurality of electrodes 122, 124,... Arranged in the even-numbered electrode layers are generally orthogonal to each other, Are provided with continuous layers 132, 133, 134,...

  Except for the lowermost electrode 121 and the uppermost electrode, both the electrodes in the odd-numbered electrode layers and the electrodes in the even-numbered electrode layers are variable resistors provided on both surfaces (upper and lower recording layers) of these electrodes. It is electrically connected to the material.

  These electrodes 121, 122,... Themselves are word lines or bit lines, or are connected to word lines or bit lines. When the electrodes 121, 123,... In the odd-numbered electrode layers are word lines or connected to the word lines, are the electrodes 122, 124,. Connected to bit line. In the opposite case, the electrodes 121, 123,... In the odd-numbered electrode layers are bit lines themselves or connected to the bit lines, and the electrodes 122, 124,. Or connected to a word line.

  Then, by applying an electric means such as a voltage pulse or a current pulse between any electrodes, a memory cell (continuous layer 131 of electrodes and variable resistance material) in a region located at the intersection of both electrodes to which the electric field is applied. , 132, 133, 134... Are in contact with memory cells), and the electric resistance value of the variable resistance material constituting the memory cell is changed, and information (data) writing, resetting, and reading operations are performed. .

  Further, the thickness of each electrode 121, 122,... And each variable resistance material 131, 132,... Is preferably 10 nm to 1 μm, and the thickness of the silicon oxide is preferably 0.1 to 1 μm.

  The substrate is not limited to silicon, but can be any suitable substrate material that is either lanthanum aluminate, lithium niobate, titanium nitride, or any other material amorphous, polycrystalline or single crystal. is there.

  The variable resistance material 131, 132,... Is a variable resistance material whose electrical resistance value changes by applying an electric means such as a voltage pulse or current pulse, DC voltage or DC current, AC voltage or AC current. A metal oxide having a crystal structure such as a perovskite structure, an ilmenite structure, or a spinel structure, or a chalcogenide compound such as a Ge—Sb—Te system is preferable.

  In the case of having a perovskite type structure, it is at least one of a ferroelectric material, a super giant magnetoresistive (CMR) material, and a high temperature superconducting (HTSC) material, in particular, strontium titanate, barium titanate titanate, It is preferably at least one of strontium zirconate, praseodymium manganate, and barium calcium gadolinium cobaltate. Furthermore, at least one or more additive elements may be contained among niobium, chromium, vanadium, scandium or other transition metals.

  When it has an ilmenite structure, it is preferably a ferroelectric material, and is lithium niobate or lithium tantalate containing at least one additional element of magnesium, indium, scandium, zinc, copper, and iron. Is preferred.

  In the case of a spinel structure, magnesium titanate, chromium magnesium oxide, nickel chromate, aluminum magnesium oxide, aluminum vanadate, iron cobaltate, iron oxide, copper / iron oxide (copper ferrite), zinc / It is preferably at least one of iron oxide, manganese / iron oxide, and nickel / iron oxide.

  The metal oxide may be iron oxide, copper oxide, nickel oxide, cobalt oxide, titanium oxide, niobium oxide, tantalum oxide, zirconium oxide, tungsten oxide, hafnium oxide, aluminum oxide. It is preferable that it is at least any one of things.

  FIG. 2 is a cross-sectional view showing another configuration of the nonvolatile memory 20 according to the first embodiment. In this nonvolatile memory 20, the recording layers 1, 2, 3,... Are composed of discontinuous layers 231, 232, 233... Of variable resistance material whose electric resistance value changes in response to given electrical means. This is different from the nonvolatile memory 10 of FIG. As shown in FIG. 2, each recording layer 1, 2, 3,... Is a region sandwiched between a plurality of electrodes included in the electrode layer immediately above and a plurality of electrodes included in the electrode layer immediately below (the electrode layer directly above The variable resistance material is formed only in a region where the perpendicular from the electrode included in the electrode intersects the electrode included in the electrode layer immediately below.

  By configuring the variable resistance material as a discontinuous layer in this manner, the distance between the plurality of electrodes arranged in parallel in substantially the same plane is extremely small compared to the case of the variable resistance material consisting of the continuous layers in FIG. Even when it becomes narrow, it has the effect that the influence of crosstalk between memory cells can be reduced.

  FIG. 3 is a cross-sectional view showing another configuration of the nonvolatile memory 30 according to the first embodiment. In the nonvolatile memory 30, an adhesion layer 34 made of titanium, tantalum, titanium oxide, tantalum oxide, or the like is formed between the substrate 11 and the lowermost electrode layer 1. The thickness of the adhesion layer 34 is preferably 10 nm to 100 nm. The uppermost electrode layer (n + 1) is covered with an insulator 35 such as aluminum oxide or silicon oxide. This is different from the nonvolatile memory 10 of FIG.

  3 is provided with the adhesion layer 34, the adhesion strength between the substrate 11 and the electrode 121 of the lowermost electrode layer 1 is improved, and the uppermost electrode layer ( Since n + 1) is covered with the insulator 35, the reliability of the nonvolatile memory element can be improved.

  Although the case where the variable resistance material is a continuous layer has been described here, the same effect can be obtained even when the variable resistance material is a discontinuous layer as shown in FIG. Moreover, although the example in which the plurality of electrodes are substantially orthogonal is shown, it is not always necessary to be orthogonal, and they may be arranged in parallel to each other.

Hereinafter, as an example, a case where a nonvolatile memory having a three-dimensional structure formed using a PCMO (calcium manganate praseodymium) material which is a metal oxide having a thickness of 300 nm as a variable resistance material will be described. This PCMO material can reduce the electrical resistance value by applying a positive voltage pulse and then increase the electrical resistance value by applying a negative voltage pulse. The write operation, reset operation, and read operation of the present invention will be described in the case where the applied low resistance state is the reset state and the high resistance state to which the negative pulse is applied is the write state.
(Write operation)
FIG. 4 is a circuit diagram for explaining a write operation to the memory cell according to the first embodiment of the present invention. Consider a memory array in which variable resistance materials (memory cells) Rc in a region located at the intersection of both electrodes are arranged in five stages in a 4 × 4 matrix.

FIG. 4A shows that the variable resistance material Rc constituting the memory cell of the second-stage recording layer 3 in the nonvolatile memory having the three-dimensional structure described with reference to FIGS. 1 to 3 is 4 × 4. FIG. 4B shows a circuit diagram in a state of being arranged in a matrix. As shown in FIG. 5, the variable resistance material Rc constituting ten memory cells is stacked in the vertical direction to form one stack. A circuit diagram of the state is shown. Incidentally, FIG. 4 (a) and 4 in the (b) the word line W ₂₃ and the bit line B ₂₃ are the same product.

  One terminal of the variable resistance material Rc constituting each memory cell is connected to a word line, and the other terminal is connected to a bit line. In FIG. 4, peripheral circuits adjacent to the memory array are omitted.

  The amplitude of the voltage pulse in which the electric resistance value of the PCMO material according to the present invention changes abruptly, that is, the threshold (threshold value) was 3.5 V (pulse width 100 ns). Therefore, data can be written into the memory cell (variable resistance material) by applying a voltage pulse having an amplitude exceeding 3.5 V between the electrodes sandwiching the variable resistance material.

  When this memory array is inactive (precharge state), all bit lines are set to 0V (GND level) and all word lines are set to 0V (GND level).

In order to execute the write operation to the selected memory cell (increase the resistance value of the variable resistance material Rca in the selected memory cell), the word line W connected to the variable resistance material Rca forming the selected memory cell. _{23 is set} to 0 V (GND level), and the bit lines other than the bit line B ₂₃ connected to the selected memory cell are set to 0 V (GND level) so as to have the same potential.

Then, the selected variable resistance material bit line B ₂₃ connected to Rca forming the memory cell, as between electrodes sandwiching a variable resistive material Rca is potential difference exceeds the threshold voltage of the first specified value As a positive voltage pulse of 4V is applied. On the other hand, in order to apply the voltage of the second specified value to the variable resistance material other than the variable resistance material Rca, each memory cell is formed on the word line that is not connected to the variable resistance material Rca forming the selected memory cell. A voltage pulse of 2V is applied as the voltage of the second specified value so that the potential difference between the electrodes sandwiching the variable resistance material Rc is less than the threshold. The potential of each word line is determined by a word line driving circuit (not shown).

Under this input condition, as shown in FIG. 4, between the bit line B ₂₃ for specifying the selected memory cell and the word line W ₂₃ , the variable resistance material Rca in the selected memory cell passes from the bit line B _23. The voltage higher than the threshold can be applied as the first specified voltage only to the variable resistance material Rca in the selected memory cell by the current path that passes through the word voltage application driver indicated by the arrow A. In addition, since a voltage less than the threshold is applied as a second specified voltage to variable resistance materials other than the variable resistance material Rca, the electrical resistance value of the variable resistance material Rca forming the selected memory cell is several The voltage rises to 100 kΩ to 1 MΩ, and the write operation to the selected memory cell can be executed.
(Reset operation)
FIG. 6 is a circuit diagram illustrating the reset operation of the memory cell according to the first embodiment of the present invention. 6 (a) and 6 (b) are the same as FIG. 4, and FIG. 6 (a) shows that the variable resistance material Rc constituting the memory cell of the second recording layer 3 in the nonvolatile memory having a three-dimensional structure is 4 ×. 4B is a circuit diagram in a state where four variable resistance materials Rc constituting ten memory cells are stacked vertically to form one stack. Show. The word line W ₂₃ and the bit line B ₂₃ in FIGS. 6A and 6B are the same.

In order to reset the resistance value of the variable resistance material Rca in the selected memory cell, the bit line B ₂₃ connected to the variable resistance material Rca in the selected memory cell is set to 0 V (GND level) and has the same potential as this. as such, the word lines other than the word line W ₂₃ connected to the selected memory cell and 0V (GND level).

Then, a positive 4V voltage pulse is applied to the word line W ₂₃ connected to the variable resistance material Rca forming the selected memory cell so that the potential difference between the electrodes sandwiching the variable resistance material Rca exceeds the threshold. Is applied to the bit line that is not connected to the variable resistance material Rca forming the selected memory cell, so that the potential difference between the electrodes sandwiching the variable resistance material Rc constituting each memory cell is less than the threshold. Apply a voltage pulse.

Under this input condition, as shown in FIG. 6, between the bit line B ₂₃ specifying the selected memory cell and the word line W ₂₃ , the variable resistance material Rca in the selected memory cell passes through the word line W _23. , by a current path passing the bit voltage application driver shown by the arrow a passing the bit line B _23, applying a variable resistance material Rca only the first threshold voltage higher than a specified voltage value in the selected memory cell Can do. In addition, since a voltage less than the threshold is applied as a second specified voltage to variable resistance materials other than the variable resistance material Rca, the electrical resistance value of the variable resistance material Rca forming the selected memory cell is several It is reduced to one hundred Ω to several kΩ. By this series of operations, the write information (data) is reset only in the selected memory cell.
(Read operation)
FIG. 7 is a circuit diagram illustrating a read operation of the memory cell according to the first embodiment of the present invention. FIGS. 7A and 7B are circuit diagrams similar to FIGS.

  When this memory array is inactive (precharge state), all bit lines are set to 0V (GND level) and all word lines are set to 0V (GND level), as in the write operation.

In order to execute the read operation of the selected memory cell, the bit line B ₂₃ connected to the variable resistance material Rca in the selected memory cell is set to 0 V (GND level) and is selected so as to have the same potential. Word lines other than the word line W ₂₃ connected to the memory cell are set to 0V (GND level).

Then, the word line W ₂₃ connected to the variable resistance material Rca forming the selected memory cell has a voltage of the third specified value so that the potential difference between the electrodes sandwiching the variable resistance material Rca is less than the threshold. As a positive voltage of 1V is applied to the bit lines not connected to the variable resistance material Rca forming the selected memory cell, the potential difference between the electrodes sandwiching the variable resistance material Rc constituting each memory cell is 0V. A voltage of 1V is applied so that

Under this input condition, as shown in FIG. 7, between the bit line B ₂₃ and the word line W ₂₃ for specifying the selected memory cell, the variable resistance material Rca in the selected memory cell passes from the word line W _23. , by a current path passing the bit voltage application driver shown by the arrow a passing the bit line B _23, voltage can be applied to the third predetermined value only to the variable resistance material Rca in the selected memory cell. As a result, a read operation for only the selected memory cell can be executed. That is, when a current flows through a variable resistance material other than the variable resistance material Rca connected to the word line W ₂₃ , a current flows from the word line W ₂₃ through the variable resistance material Rca in the selected memory cell to the bit line B _23. since the exact value of the current flowing through the path can not be measured, is connected to the word line W _23, so that no current flows through the variable resistance material the variable resistance material other than Rca, upper and lower bit lines sandwiching the word line W ₂₃ ( B ₂₃ excluding) B _2n and B _1n (n was set to be the same potential integer of 1 or more) to the word line W _23.
(Embodiment 2)
Hereinafter, another embodiment will be described in the case where the high resistance state is a writing state and the low resistance state is a reset state using the non-volatile memory having the three-dimensional structure described in the first embodiment.
(Write operation)
FIG. 8 is a circuit diagram illustrating a write operation to a memory cell according to the second embodiment of the present invention. Similar to the first embodiment, consider a memory array in which variable resistance materials (memory cells) Rc in a region located at the intersection of both electrodes are arranged in five stages in a 4 × 4 matrix.

FIGS. 8A and 8B are circuit diagrams similar to those in the first embodiment. Further, the word line W ₂₃ and the bit line B ₂₃ shown in FIGS. 8A and 8B are the same.

  One terminal of the variable resistance material Rc constituting each memory cell is connected to a word line, and the other terminal is connected to a bit line. In FIG. 8, peripheral circuits adjacent to the memory array are omitted.

  The amplitude of the voltage pulse in which the electric resistance value of the PCMO material according to the present invention changes abruptly, that is, the threshold (threshold value) was 3.5 V (pulse width 100 ns). Therefore, data can be written into the memory cell (variable resistance material) by applying a voltage pulse having an amplitude exceeding 3.5 V between the electrodes sandwiching the variable resistance material.

  When this memory array is inactive (precharge state), all bit lines are set to 0V (GND level) and all word lines are set to 0V (GND level).

In order to execute the write operation to the selected memory cell (increase the resistance value of the variable resistance material Rca in the selected memory cell), the word line W connected to the variable resistance material Rca forming the selected memory cell. A voltage pulse of −4V is applied to ₂₃ . Then, a voltage pulse −4 V having the same polarity and the same potential is applied to the bit lines other than the bit line B ₂₃ connected to the selected memory cell.

The bit line B ₂₃ connected to the variable resistance material Rca forming the selected memory cell is set to 0 V (GND level) so that the potential difference between the electrodes sandwiching the variable resistance material Rca exceeds the threshold. . Then, −2 V is applied to the word lines not connected to the variable resistance material Rca forming the selected memory cell so that the potential difference between the electrodes sandwiching the variable resistance material Rc constituting each memory cell is less than the threshold. To do. The potential of each word line is determined by a word voltage application driver (not shown).

Under this input condition, as shown in FIG. 8, between the bit line B ₂₃ specifying the selected memory cell and the word line W ₂₃ , the variable resistance material Rca in the selected memory cell is passed from the bit line B _23. The voltage higher than the threshold can be applied only to the variable resistance material Rca in the selected memory cell by the current path that passes through the word voltage application driver indicated by the arrow A, and the variable resistance material that forms the selected memory cell The electric resistance value of Rca rises to several hundred kΩ to 1 MΩ, and a write operation to the selected memory cell can be executed.
(Reset operation)
FIG. 9 is a circuit diagram illustrating the reset operation of the memory cell according to the second embodiment of the present invention. To reset the resistance value of the variable resistance material Rca in the selected memory cell applies a voltage pulse of positive polarity 5V to the word line W ₂₃ which is connected to the variable resistance material Rca in the selected memory cell. Then, 1 V is applied to the bit line B ₂₃ connected to the variable resistance material Rca forming the selected memory cell so that the potential difference between the electrodes sandwiching the variable resistance material Rca exceeds the threshold. the pulse voltage 1V having the same potential with the same polarity is applied to the word lines other than the word line W ₂₃ identifying the selected memory cell. Further, 2 V is applied to the other bit lines not connected to the selected memory cell so that the potential difference between the electrodes sandwiching the variable resistance material Rc is less than the threshold.

Under this input condition, as shown in FIG. 9, between the bit line B ₂₃ and the word line W ₂₃ for specifying the selected memory cell, the variable resistance material Rca in the selected memory cell passes through the word line W _23. , by a current path passing the bit voltage application driver shown by the arrow a passing the bit line B _23, can be applied to the variable resistance material Rca only a threshold voltage higher than in the selected memory cell, the selected memory cell The electric resistance value of the variable resistance material Rca that forms the film is reduced to several hundred Ω to several kΩ. By this series of operations, the write information (data) is reset only in the selected memory cell.
(Read operation)
FIG. 10 is a circuit diagram illustrating the read operation of the memory cell according to the second embodiment of the present invention. When this memory array is inactive (precharge state), all bit lines are set to 0V (GND level) and all word lines are set to 0V (GND level), as in the write operation.

To perform a read operation of the selected memory cell, a voltage of 2V to the word line W ₂₃ which is connected to the variable resistance material Rca in the selected memory cell. Then, a positive 1V voltage is applied to the bit line B ₂₃ connected to the variable resistance material Rca forming the selected memory cell so that the potential difference between the electrodes sandwiching the variable resistance material Rca is less than the threshold. Then, a voltage 1 V having the same polarity and the same potential is applied to word lines other than the word line W ₂₃ specifying the selected memory cell. Further, 2 V is applied to the other bit lines not connected to the selected memory cell so that the potential difference between the electrodes sandwiching the variable resistance material Rc is less than the threshold.

Under this input condition, as shown in FIG. 10, between the bit line B ₂₃ and the word line W ₂₃ for specifying the selected memory cell, the variable resistance material Rca in the selected memory cell passes through the word line W _23. , by a current path passing the bit voltage application driver shown by the arrow a passing the bit line B _23, it is possible to perform a read operation of only the selected memory cell.
(Embodiment 3)
Hereinafter, using the nonvolatile memory having the three-dimensional structure described in the first and second embodiments, the same voltage control is performed after the writing operation in the case where the high resistance state is the writing state and the low resistance state is the reset state. An embodiment in which a read operation is performed using a circuit will be described.

  Since the amplitude of the voltage pulse in which the electric resistance value of the PCMO material according to the present invention changes rapidly, that is, the threshold (threshold) is 3.5 V (pulse width 100 ns), the variable resistance material of the selected memory cell is selected. A voltage pulse having an amplitude exceeding 3.5 V was applied between the sandwiched electrodes, and the writing operation described in the first or second embodiment was performed.

  Subsequently, a voltage of 2 V is applied to the word line connected to the variable resistance material in the selected memory cell, and the variable resistance material is applied to the bit line connected to the variable resistance material forming the selected memory cell. A positive voltage of 1V is applied so that the potential difference between the electrodes across the electrode is less than the threshold, and a voltage of 1V having the same polarity and the same potential is applied to a word line not connected to the selected memory cell. The read operation of only the selected memory cell is executed by applying a positive 2V voltage to the bit line not connected to the selected memory cell so that the potential difference between the electrodes sandwiching the variable resistance material is 0V. did.

  Further, a positive 5V voltage pulse is applied to the word line connected to the variable resistance material in the selected memory cell, and the bit line connected to the variable resistance material forming the selected memory cell has a variable resistance. 1 V is applied so that the potential difference between the electrodes across the material exceeds the threshold, and a pulse voltage 1 V having the same polarity and the same potential is applied to a word line not connected to the selected memory cell, and the selected memory For other bit lines not connected to the cell, 2 V is applied so that the potential difference between the electrodes sandwiching the variable resistance material is less than the threshold, thereby resetting the write information (data) of the selected memory cell. went.

In the above-described embodiment (write operation), it is also possible to realize (reset operation) by reversing the polarity of the voltage applied to the word line and the bit line. That is, the word line W ₂₃ connected to the variable resistance material Rca forming the selected memory cell is set to 0 V (GND level), and other than the bit line B ₂₃ connected to the selected memory cell so as to have the same potential. of the bit line and 0V (GND level), the selection variable resistance material Rca bit line is connected to the B ₂₃ to form a memory cell, so that between the electrodes sandwiching the variable resistance material Rca is potential difference exceeds threshold In addition, a negative voltage pulse of −4 V is applied to a word line that is not connected to the variable resistance material Rca forming the selected memory cell, and the threshold between the electrodes sandwiching the variable resistance material Rc constituting each memory cell is A voltage pulse of −2 V may be applied so that the potential difference is less than the hold.
<< Other Embodiments >>
Embodiments 1 to 3 may be configured as follows.

  The variable resistance material may be a non-volatile memory having a three-dimensional structure using a chalcogenide compound, and the chalcogenide compound preferably contains germanium, antimony, and tellurium.

  This chalcogenide compound is phase-changed into an amorphous state in a high resistance state and a crystalline state in a low resistance state by electrical means. When Joule heat is generated by voltage application, it changes from a high resistance amorphous state to a low resistance crystalline state. On the other hand, Joule heat generation by voltage application causes a temperature above the melting point of the crystal once. When the crystal is melted and the applied voltage is lowered to the GND level at that time, the crystalline state changes to the amorphous state by rapid cooling from a high temperature.

  In other words, the mutual switching between the high-resistance amorphous state and the low-resistance crystalline state is controlled by the applied pulse voltage, and when the high-resistance state is the writing state and the low-resistance state is the reset state, The write operation, reset operation, and read operation of the present invention can be performed using a similar voltage control circuit.

Furthermore, the chalcogenide compound containing germanium, antimony, and tellurium contains at least one or more additive elements among indium, gallium, bismuth, aluminum, tin, lead, boron, carbon, silicon, and lanthanoid elements. Since the melting point is lowered, the melting temperature can be lowered and the power consumption can be reduced.
(Embodiment 4)
FIG. 11 is a diagram illustrating a configuration including peripheral circuits of the nonvolatile memory circuit described in the first to third embodiments. The nonvolatile memory circuit includes a memory array 1000, a word line driving circuit 1100, a bit line driving circuit 1200, a control unit 1300, a pulse generation circuit 1400, a level shift circuit 1500, and a voltage generation circuit 1600. ing.

  The memory array 1000 includes the nonvolatile memory cell array having the three-dimensional structure described in the first to third embodiments.

  The word line driving circuit 1100 applies a predetermined voltage (pulse voltage, ground voltage, etc.) to each word line at the time of writing / reading / resetting the memory cells in the memory array 1000. The method for applying the voltage is as described in the first to third embodiments. A plurality of selectors 1101 are provided in the word line driving circuit 1100. Each selector 1101 corresponds to each word line in the memory array 1000, selects a voltage corresponding to the control signal a from the control unit 1300, and applies it to the corresponding word line.

  The bit line driving circuit 1200 applies a predetermined voltage (pulse voltage, ground voltage, etc.) to each bit line at the time of writing / reading / resetting to the memory cells in the memory array 1000, and at the time of reading, the bit corresponding to the selected memory cell Detect the current flowing through the wire. The method for applying the voltage is as described in the first to third embodiments. In the bit line driving circuit 1200, a plurality of selectors 1201 and a plurality of current detection circuits 1202 are provided. Each selector 1201 corresponds to each bit line in the memory array 1000, selects a voltage corresponding to the control signal b from the control unit 1300, and applies it to the corresponding bit line. Each current detection circuit 1202 corresponds to each bit line in the memory array 1000, and detects a current flowing through the corresponding bit line at the time of reading.

  The pulse voltage generated by the pulse generation circuit 1400 is adjusted in amplitude by a plurality of level shift circuits 1500, and a plurality of pulse voltages V1 to V3 having different amplitudes are generated. The number and amplitude level of the pulse voltage are determined according to the voltage applied to the word line and the bit line when accessing the memory cell in the memory array 1000. The method for applying the voltage is as described in the first to third embodiments. The control unit 1300 performs control such as timing of pulse output from the pulse generation circuit 1400 by the control signal c.

  Voltage generation circuit 1600 generates voltages VR1 to VR2 applied to word lines and / or bit lines when data is read from memory cells in memory array 1000. The voltage level and number to be generated are determined according to the voltage applied to the word line and / or the bit line when accessing the memory cell in the memory array 1000. The method of applying the voltage at the time of reading is as described in the first to third embodiments. The control unit 1300 controls the timing of voltage output from the voltage generation circuit 1600 using the control signal d.

  The pulse voltages V1 to V3 from the level shift circuit 1500, the voltages VR1 to VR2 from the voltage generation circuit 1600, and the ground voltage GND are supplied to each selector 1101 in the word line driving circuit 1100 and each selector 1201 in the bit line driving circuit 1200. Given. The control unit 1300 selects which voltage is selected for each of the selectors 1101 and 1201 to be output to the word line and the bit line according to the voltage applied to the word line and the bit line when accessing the memory cell in the memory array 1000. Designated by control signals a and b. The method for applying the voltage is as described in the first to third embodiments.

  In the example of FIG. 11, the current detection circuit 1202 is provided in the bit line driving circuit 1200. However, a plurality of current detection circuits are provided in the word line driving circuit 1100 corresponding to each word line, and at the time of reading. The current flowing through the corresponding word line may be detected by this current detection circuit.

  According to the present invention, a highly reliable, high-speed, large-capacity nonvolatile memory that avoids the effects of read disturb and write disturb can be realized at a low cost. Can be made smaller, lighter and thinner.

Sectional drawing which shows the structure of the non-volatile memory which concerns on Embodiment 1, 2, or 3 of this invention. Sectional drawing which shows the structure of the non-volatile memory which concerns on Embodiment 1, 2, or 3 of this invention. Sectional drawing which shows the structure of the non-volatile memory which concerns on Embodiment 1, 2, or 3 of this invention. FIG. 3 is a circuit diagram illustrating a write operation to the memory cell according to the first embodiment of the present invention. Sectional drawing which shows the state in which the variable resistance material which comprises the memory cell which concerns on Embodiment 1, 2, or 3 of this invention is piled up perpendicularly, and is one stack. FIG. 3 is a circuit diagram illustrating a reset operation of the memory cell according to the first embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a read operation of the memory cell according to the first embodiment of the present invention. FIG. 6 is a circuit diagram for explaining a write operation to a memory cell according to a second embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a reset operation of a memory cell according to a second embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a read operation of a memory cell according to a second embodiment of the present invention. The figure which shows the structure of the non-volatile memory circuit including a peripheral circuit. Sectional drawing of the non-volatile memory which has the conventional three-dimensional structure. FIG. 13 is a perspective view of the memory cell of FIG. 12. Sectional drawing of the non-volatile memory which has the conventional three-dimensional structure.

Explanation of symbols

10, 20, 30 Nonvolatile memory 11 Substrate 121, 122, 123, 124, 125, 126, 127 Electrode 131, 132, 133, 134, 231, 232, 233, 234, 235, 236 Variable resistance material 34 Adhesion layer 35 Insulator 1000 Memory array 1100 Word line drive circuit 1101, 1201 Selector 1200 Bit line drive circuit 1202 Current detection circuit 1300 Control unit 1400 Pulse generation circuit 1500 Level shift circuit 1600 Voltage generation circuit

Claims (26)

A plurality of first electrodes including bit lines arranged at intervals in substantially the same plane; a plurality of second electrodes including word lines arranged at intervals in substantially the same plane; A memory array having a three-dimensional structure composed of a variable resistance material sandwiched between one electrode and the second electrode, wherein the first electrode and the second electrode intersect with each other and are arranged in a plurality of stages;
A word line driving circuit connected to the memory array and applying a voltage to the word lines of the memory array;
A bit line driving circuit connected to the memory array and applying a voltage to the bit lines of the memory array;
A word line driving circuit and a control circuit connected to the bit line driving circuit and controlling the word line driving circuit and the bit line driving circuit;
The control circuit applies a voltage having a first specified value to the selected variable resistance material, and applies a voltage having a second specified value to the unselected variable resistance material. The resistance value of the selected variable resistance material is increased / decreased by controlling a driving circuit,
Nonvolatile memory circuit. A plurality of first electrodes including bit lines arranged at intervals in substantially the same plane; a plurality of second electrodes including word lines arranged at intervals in substantially the same plane; A memory array having a three-dimensional structure composed of a variable resistance material sandwiched between one electrode and the second electrode, wherein the first electrode and the second electrode intersect with each other and are arranged in a plurality of stages;
A word line driving circuit connected to the memory array and applying a voltage to the word lines of the memory array;
A bit line driving circuit connected to the memory array and applying a voltage to the bit lines of the memory array;
A word line driving circuit and a control circuit connected to the bit line driving circuit and controlling the word line driving circuit and the bit line driving circuit;
The control circuit applies a voltage of a third specified value to the selected variable resistance material, and applies a voltage to the unselected variable resistance material connected to the word line to which the selected variable resistance material is connected. The resistance value of the selected variable resistance material is read by controlling the word line driving circuit and the bit line driving circuit so as not to apply
Nonvolatile memory circuit. The word line drive circuit includes a pulse generation circuit that generates a pulse voltage, and
It further has a specified value setting circuit for setting the first specified value, the second specified value, and the third specified value,
The nonvolatile memory circuit according to claim 1. The word line drive circuit or the bit line drive circuit further includes a current detection circuit that detects a current flowing through the variable resistance material.
The nonvolatile memory circuit according to claim 1.   The nonvolatile memory circuit according to claim 1, wherein the variable resistance material is a metal oxide.   The nonvolatile memory circuit according to claim 1, wherein the variable resistance material is a chalcogenide compound.   6. The nonvolatile memory circuit according to claim 5, wherein the metal oxide has a crystal structure of any one of a perovskite structure, an ilmenite structure, and a spinel structure.   Metal oxide is iron oxide, copper oxide, nickel oxide, cobalt oxide, titanium oxide, niobium oxide, tantalum oxide, zirconium oxide, tungsten oxide, hafnium oxide, aluminum oxide, 6. The nonvolatile memory circuit according to claim 5, wherein the nonvolatile memory circuit is at least one of them.   The metal oxide having a perovskite structure is at least one of a ferroelectric material, a super giant magnetoresistive (CMR) material, and a high temperature superconducting (HTSC) material. Nonvolatile memory circuit.   8. The metal oxide having a perovskite structure is at least one of strontium titanate, strontium barium titanate, strontium zirconate, calcium praseodymium manganate, and barium calcium gadolinium cobaltate. Or the nonvolatile memory circuit according to 9;   11. The nonvolatile memory circuit according to claim 10, wherein the metal oxide having a perovskite structure contains at least one additional element of niobium, chromium, vanadium, scandium, or other transition metals. .   8. The nonvolatile memory circuit according to claim 7, wherein the metal oxide having an ilmenite structure is a ferroelectric material.   13. The metal oxide having an ilmenite structure is lithium niobate or lithium tantalate containing at least one additive element of magnesium, indium, scandium, zinc, copper, and iron. The non-volatile memory circuit described in 1.   Metal oxides with a spinel structure are magnesium titanate, chromium magnesium oxide, nickel chromate, aluminum magnesium oxide, aluminum vanadate, iron cobaltate, iron oxide, copper / iron oxide (copper ferrite), zinc / The nonvolatile memory circuit according to claim 7, wherein the nonvolatile memory circuit is any one of iron oxide, manganese / iron oxide, and nickel / iron oxide.   The nonvolatile memory circuit according to claim 6, wherein the chalcogenide compound contains germanium, antimony, and tellurium.   The chalcogenide compound contains germanium, antimony, and tellurium, and contains at least one additional element of indium, gallium, bismuth, aluminum, tin, lead, boron, carbon, silicon, and lanthanoid elements. The nonvolatile memory circuit according to claim 6. A plurality of first electrodes including bit lines arranged at intervals in substantially the same plane; a plurality of second electrodes including word lines arranged at intervals in substantially the same plane; A non-volatile memory circuit having a three-dimensional structure, which is composed of a variable resistance material sandwiched between one electrode and the second electrode, and wherein the first electrode and the second electrode intersect with each other and are arranged in a plurality of stages Driving method,
A resistance of the selected variable resistance material is applied by applying a voltage of a first specified value to the selected variable resistance material and applying a voltage of a second specified value to the unselected variable resistance material. Characterized by increasing / decreasing the value,
A method for driving a nonvolatile memory circuit. The voltage applied to the bit line other than the word line connected to the selected variable resistance material and the bit line connected to the selected variable resistance material is the same potential,
A bit line connected to the selected variable resistance material is applied with a voltage at which a potential difference from the word line connected to the selected variable resistance material is the first specified value;
For word lines other than the word line connected to the selected variable resistance material, the potential difference from the voltage applied to the bit line connected to the selected variable resistance material becomes the second specified value. A voltage is applied,
The method for driving a nonvolatile memory circuit according to claim 17. The voltage applied to the bit line other than the word line connected to the selected variable resistance material and the bit line connected to the selected variable resistance material has the same potential, and is connected to the selected variable resistance material. The potential of the voltage applied to the selected word line is set lower than the potential of the voltage applied to the bit line connected to the selected variable resistance material, thereby setting the resistance value of the selected variable resistance material. Decrease,
The voltage applied to the bit line other than the word line connected to the selected variable resistance material and the bit line connected to the selected variable resistance material has the same potential, and is connected to the selected variable resistance material. The potential of the voltage applied to the selected word line is set higher than the potential of the voltage applied to the bit line connected to the selected variable resistance material, thereby setting the resistance value of the selected variable resistance material. Characterized by increasing,
The method for driving a nonvolatile memory circuit according to claim 17 or 18. A word line connected to the selected variable resistance material is set to 0 V (GND level) to reduce the resistance value of the selected variable resistance material;
The bit line connected to the selected variable resistance material is set to 0 V (GND level) to increase the resistance value of the selected variable resistance material.
The method for driving a nonvolatile memory circuit according to claim 17. A plurality of first electrodes including bit lines arranged at intervals in substantially the same plane; a plurality of second electrodes including word lines arranged at intervals in substantially the same plane; A non-volatile memory circuit having a three-dimensional structure composed of a variable resistance material sandwiched between one electrode and the second electrode, wherein the first electrode and the second electrode intersect with each other and are arranged in a plurality of stages. A driving method comprising:
A voltage of the third specified value is applied to the selected variable resistance material, and no voltage is applied to the unselected variable resistance material connected to the word line to which the selected variable resistance material is connected. By reading the resistance value of the selected variable resistance material,
A method for driving a nonvolatile memory circuit. A voltage applied to a word line to which the selected variable resistance material is connected is connected to an unselected variable resistance material connected to the word line to which the selected variable resistance material is connected. The voltage applied to the bit line is the same potential,
The voltage applied to the word line adjacent in the vertical direction to the word line to which the selected variable resistance material is connected and the voltage applied to the bit line to which the selected variable resistance material is connected have the same potential. Yes,
The word line connected to the selected variable resistance material is applied with a voltage at which the potential difference from the bit line connected to the selected variable resistance material is the third specified value. ,
The method for driving a nonvolatile memory circuit according to claim 21. The bit line connected to the selected variable resistance material is set to 0 V (GND level) and the resistance value of the variable resistance material is read.
The method for driving a nonvolatile memory circuit according to claim 21 or 22. The first specified value is a voltage value equal to or higher than a threshold at which the electric resistance value of the variable resistance material rapidly changes,
The second specified value is a voltage value less than a threshold at which the electric resistance value of the variable resistance material changes rapidly,
The method for driving a nonvolatile memory circuit according to claim 17 or 18. The third specified value is a voltage value less than a threshold at which the electric resistance value of the variable resistance material changes rapidly,
The method for driving a nonvolatile memory circuit according to claim 21 or 22. The voltage is a pulse voltage,
The method for driving a nonvolatile memory circuit according to claim 17.

Images