JP2011233211A - Variable resistance element driving method and nonvolatile memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable resistance element driving method permitting realization of stable multi-value memory actions.SOLUTION: A writing process of applying one writing voltage pulse out of writing voltage pulses, having a plurality of voltages in a first polarity, to a variable resistance element 10 (S101, S102) and a reading process of sequentially providing the variable resistance element 10 in the ascending order of voltage value with reading voltage pulses having a plurality of voltages in a second polarity different from the first polarity (S205 to S209) are executed. In this reading process, it is determined which voltage of the write voltage pulse has been used according to a variation in the resistance status of the variable resistance element when the read voltage pulses were sequentially provided (S210).

Description

  The present invention relates to a resistance change element driving method in which a resistance value changes according to voltage pulses having different polarities, and a nonvolatile memory device that implements the method.

  In recent years, with the advancement of digital technology, electronic devices such as portable information devices and information home appliances have become more sophisticated. As these electronic devices have higher functions, the semiconductor elements used have been rapidly miniaturized and increased in speed. Among them, the use of a large-capacity nonvolatile storage device represented by a flash memory is rapidly expanding. Further, as a next-generation nonvolatile memory device that replaces the flash memory, research and development of a nonvolatile memory device including a resistance change element having a property that a resistance value is reversibly changed by an electrical signal is progressing.

  In the nonvolatile memory device including the variable resistance element as described above, an attempt has been made to increase the number of values in order to increase the storage capacity per unit area. For example, in Patent Document 1 and Patent Document 2, the resistance change element is set to one of a plurality of different resistance states by changing the value of the current flowing through the resistance change element, and the resistance value varies depending on the resistance value in each resistance state. A nonvolatile storage device that realizes value conversion is disclosed.

US Pat. No. 7,269,050 International Publication No. 2006/137111

  However, even if a current having the same current value is applied to the variable resistance element, the resistance value is not stabilized at a constant value, and variation occurs. Therefore, in the case of a conventional nonvolatile memory device that realizes multi-value by current control as disclosed in Patent Document 1 and Patent Document 2, there is a problem that a read error may occur.

  The present invention has been made in view of such circumstances, and a main object thereof is to provide a resistance change element driving method capable of realizing a stable multi-value storage operation and a nonvolatile memory device that implements the method. There is to do.

  In order to solve the above-described problem, a resistance change element driving method according to one embodiment of the present invention uses a resistance change element whose resistance value reversibly changes in response to an electric pulse having a different polarity as a multi-value storage element. A driving method of a resistance change element to be driven, wherein one write electric pulse of a plurality of write electric pulses having a first polarity with different magnitudes is applied to the resistance change element, thereby causing the resistance change element to A writing process for changing from one resistance state to a second resistance state, and a plurality of read electrical pulses having different second polarities different from the first polarity in order of decreasing the resistance A read process applied to the element, and in the read process, when the read electrical pulse is sequentially applied, the resistance change element is moved from the second resistance state to the first resistance. Depending on which of the plurality of different magnitudes of the read electrical pulse initially changed in the direction of the state, the write electrical pulse of the plurality of different magnitudes of the write electrical pulse causes the It is determined whether the writing process has been performed.

  In this way, multi-value storage is performed more stably by comparing the multi-value by the difference in the magnitude of the write electrical pulse, compared to the case of multi-value by the difference in resistance value of the resistance change element as in the past. Can be realized.

  That is, the resistance change element changes from the second resistance state to the first resistance state according to the magnitude of the write electric pulse applied when the resistance change element is changed from the first resistance state to the second resistance state. Since the characteristic of the bipolar variable resistance element that determines the minimum size of the readout electrical pulse necessary for the reading is used, stable multi-value storage is realized.

  “Electric pulse” is a concept including “voltage pulse” and “current pulse”. Further, “the magnitude of the electric pulse” means “the voltage of the voltage pulse” or “the current of the current pulse”.

  Here, the driving method (writing method) may be voltage driving (voltage writing) or current driving (current writing). In other words, in the writing step, by applying one write electric pulse among the plurality of write electric pulses having different voltages of the first polarity to the resistance change element, the resistance change element is moved from the first resistance state. Transition to the second resistance state, and in the reading step, when the reading electrical pulses of a plurality of different voltages having the second polarity are sequentially applied to the variable resistance element from the smallest absolute value of the voltage, Writing the plurality of different voltages depending on which of the plurality of different voltages is the voltage of the read electrical pulse that first changed the changing element from the second resistance state to the first resistance state. It may be determined by which writing electric pulse of the electric pulses the writing step is performed, and in the writing step, the first electrode The resistance change element is caused to transition from the first resistance state to the second resistance state by applying one of the plurality of different current write electric pulses to the resistance change element. In the reading step, when the plurality of different electric current reading electric pulses having the second polarity are sequentially applied to the variable resistance element from the smaller current magnitude, the variable resistance element is moved from the second resistance state. Depending on which of the plurality of different currents the current of the read electrical pulse first changed in the direction of the first resistance state, which write electrical pulse of the plurality of different current write electrical pulses It may be determined whether the writing step has been performed.

  In this aspect, in the writing step, the variable resistance element is changed from a high resistance state to a low resistance state, and in the reading step, when the read electrical pulse is sequentially applied, the variable resistance element is changed to a low resistance state. Depending on which of the plurality of different magnitudes of the read electrical pulse initially changed from the state to the high resistance state, which of the plurality of different magnitudes of the write electrical pulse It is preferable to determine whether the writing process has been performed by an electric pulse. In general, in a resistance change element, the resistance value variation is smaller and more stable in the low resistance state than in the high resistance state, and when writing is performed by reducing the resistance of the resistance change element, the resistance change element is higher. As compared with the case where writing is performed by making the resistance, better retention characteristics can be obtained.

  Further, in the above aspect, the method further includes a rewriting step of applying a writing electric pulse having the same magnitude as the writing electric pulse applied to the variable resistance element in the writing step after the reading step. May be. Thereby, even after the read process, the resistance state of the resistance change element before the read is restored, and a treatment for destructive read is performed.

  A nonvolatile memory device according to one embodiment of the present invention includes an electric pulse having a polarity different from that provided between a first electrode, a second electrode, and the first electrode and the second electrode. And a selection circuit for selecting at least one memory cell from the memory cell array, and a memory cell array including a plurality of resistance change elements having a resistance change layer whose resistance value reversibly changes according to And a control unit that controls the selection circuit to select at least one memory cell from the memory cells, and executes a writing process or a reading process for the selected memory cell, and the control unit includes the writing In the process, one of the plurality of different-sized write electric pulses having the first polarity is included in the selected memory cell. By applying between the two electrodes of the variable resistance element, the resistance state of the variable resistance layer is changed from the first resistance state to the second resistance state, and in the reading step, the second polarity different from the first polarity. When a plurality of read electrical pulses having different polarities are sequentially applied between the electrodes in order from a smaller magnitude, and the read electrical pulses are sequentially applied between the two electrodes, the resistance change layer is provided in the second layer. Depending on which of the plurality of different magnitudes of the read electrical pulse initially changed in the direction from the resistance state to the first resistance state, the plurality of write electrical pulses of different magnitudes It is determined by which of the write electrical pulses the write process is performed.

  In this aspect, the control unit changes the resistance change layer from a high resistance state to a low resistance state in the writing step, and the reading electric pulse is sequentially applied between both electrodes in the reading step. In addition, depending on which of the plurality of different magnitudes of the read electrical pulse that first changed the resistance change layer from the low resistance state to the high resistance state, the plurality of different magnitudes. It is preferable to determine which of the writing electrical pulses the writing process is performed by.

  Further, in the above aspect, the control unit may apply the write electrical pulse between the electrodes having the same magnitude as the write electrical pulse applied between the electrodes in the write process after the read process. The rewriting process for changing the resistance state of the change layer may be further executed.

In the above aspect, the variable resistance layer may include an oxygen-deficient transition metal oxide. In this case, the transition metal oxide includes a first region containing a first oxygen-deficient transition metal oxide having a composition represented by MO _x , and MO _y (where x <y). And a second region containing a second oxygen-deficient transition metal oxide having a composition. Furthermore, in this case, the first region includes a tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9), and the second region includes A tantalum oxide having a composition represented by TaO _y (where 2.1 ≦ y ≦ 2.5) may be included.

  In the above aspect, each of the plurality of memory cells may further include a load element electrically connected to the resistance change layer, and the load element may be a diode or a transistor.

  According to the resistance change element driving method of the present invention, a stable multilevel storage operation can be realized by utilizing the resistance change phenomenon of the resistance change element. Further, according to the nonvolatile memory device according to the present invention that implements this driving method, a memory device capable of a stable multi-value memory operation can be realized.

The schematic diagram which shows an example of a structure of the resistance change element of Embodiment 1 of this invention. (A)-(f) is a figure which shows the resistance-voltage characteristic of the resistance change element of Embodiment 1 of this invention. (A)-(f) is a figure which shows the current-voltage characteristic of the resistance change element of Embodiment 1 of this invention. The figure which shows the principle of the multi-value storage in Embodiment 1 of this invention The figure which shows the relationship between the write-voltage pulse and read-out voltage pulse in Embodiment 1 of this invention The flowchart which shows an example of the procedure of the drive method of the resistance change element which concerns on Embodiment 1 of this invention. The flowchart which shows the other example of the procedure of the drive method of the resistance change element which concerns on Embodiment 1 of this invention. (A) And (b) is a figure which shows the result of the experiment example of the write-in and read-in in Embodiment 1 of this invention. The flowchart which shows an example of the procedure of the drive method of the resistance change element which concerns on Embodiment 2 of this invention. The flowchart which shows the other example of the procedure of the drive method of the resistance change element which concerns on Embodiment 2 of this invention. The figure which shows the relationship between the write-in electric current pulse and read-out voltage pulse in Embodiment 3 of this invention. The flowchart which shows an example of the procedure of the drive method (electric current writing) of the resistance change element which concerns on Embodiment 3 of this invention. The block diagram which shows an example of a structure of the non-volatile storage device of Embodiment 5 of this invention The block diagram which shows an example of a structure of the non-volatile storage device of Embodiment 6 of this invention (A)-(f) is a figure which shows the resistance-voltage characteristic of the resistance change element of other embodiment of this invention. (A)-(f) is a figure which shows the current-voltage characteristic of the resistance change element of other embodiment of this invention.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
[Configuration of variable resistance element]
First, the configuration of the variable resistance element according to Embodiment 1 of the present invention will be described.

  FIG. 1 is a schematic diagram showing an example of the configuration of the variable resistance element 10 according to Embodiment 1 of the present invention. As shown in FIG. 1, the resistance change element 10 of the present embodiment is formed on a substrate 1, a lower electrode 2 that is an example of a first electrode formed on the substrate 1, and the lower electrode 2. The resistance change layer 3 and the upper electrode 4 which is an example of the second electrode formed on the resistance change layer 3 are provided. The lower electrode 2 and the upper electrode 4 are connected to the resistance change layer 3.

The substrate 1 is composed of, for example, a silicon substrate. The resistance change layer 3 is interposed between the lower electrode 2 and the upper electrode 4, and its resistance value reversibly changes according to electric pulses (voltage pulse or current pulse) having different polarities given between the two electrodes. A first tantalum oxide layer 3a, which is an example of a first region having a characteristic and containing a first oxygen-deficient transition metal oxide having a composition represented by MO _x , and MO _y (where x A second tantalum oxide layer 3b which is an example of the second region including the second transition metal oxide having the composition represented by <y) is laminated. Here, the oxygen content rate y of the second tantalum oxide layer 3b is higher than the oxygen content rate x of the first tantalum oxide layer 3a. The oxygen-deficient type refers to a state in which the oxygen content is less than the composition of the transition metal oxide stoichiometry. In the case of the tantalum in the above example, the composition of the tantalum oxide stoichiometry is Ta _2. since the O _5, the value of x of tantalum oxide TaO _x oxygen-deficient is less than 2.5 (0 <x <2.5) . Note that as the second transition metal oxide, a transition metal oxide layer having a stoichiometric composition may be used.

When the composition of the first tantalum oxide layer 3a is TaO _x , x is 0.8 or more and 1.9 or less, and when the composition of the second tantalum oxide layer 3b is TaO _y , y is 2 It has been confirmed that the resistance value of the resistance change layer 3 can be stably changed at a high speed when it is 1 or more and 2.5 or less. Therefore, x and y are preferably within the above range.

  If the thickness of the resistance change layer 3 is 1 μm or less, a change in resistance value is recognized, but it is preferably 200 nm or less. This is because, when patterning process lithography is used, it is easy to process and the voltage value of the voltage pulse required to change the resistance value of the resistance change layer 3 can be lowered. On the other hand, the thickness of the resistance change layer 3 is preferably at least 5 nm or more from the viewpoint of more reliably avoiding breakdown (dielectric breakdown) during voltage pulse application.

  Further, the thickness of the second tantalum oxide layer 3b is disadvantageous in that the initial resistance value becomes too high if it is too large, and if it is too small, there is a disadvantage that a stable resistance change cannot be obtained. About 8 nm or less is preferable.

  With such a configuration, it is possible to stably cause a resistance change phenomenon in the second tantalum oxide layer 3b.

  In addition to tantalum, hafnium, zirconium, and the like can cause a resistance change stably with the same configuration.

  The upper electrode 4 disposed so as to be in contact with the second tantalum oxide layer 3b is, for example, Au (gold), Pt (platinum), Ir (iridium), Pd (palladium), Cu (copper), and Ag (silver). A material having a standard electrode potential higher than the standard electrode potential of the transition metal M is used, and the lower electrode 2 is a material lower than the standard electrode potential of the material constituting the upper electrode 4. (For example, W, Ni, or TaN).

  With such a configuration, it is possible to stably cause a resistance change phenomenon in the second tantalum oxide layer 3b in contact with the upper electrode 4.

  The laminated structure and electrode arrangement described above may be employed individually, but by using a combination of the two, a more stable resistance change phenomenon can be caused. As a matter of course, the above-described laminated structure and electrode may be disposed upside down. Moreover, it may replace with the arrangement | positioning of an up-down direction, and may arrange | position in the left-right direction.

  When operating the variable resistance element 10 configured as described above, the lower electrode 2 and the upper electrode 4 are electrically connected to different terminals of the power supply 5. The power source 5 functions as an electric pulse applying device for driving the resistance change element 10, and applies an electric pulse (voltage / current pulse) having a predetermined polarity, voltage / current, and time width to the lower electrode 2 and the upper electrode. 4 is configured to be able to be applied between.

  In the following description, unless otherwise specified, the resistance change element 10 assumes that the resistance value is reversibly changed by the voltage pulse among the voltage pulse and the current pulse, and the voltage of the voltage pulse applied between the electrodes is It is specified by the potential of the upper electrode 4 with respect to the lower electrode 2.

  In addition, “the resistance state of the resistance change element 10 changes” strictly means that the resistance state of the resistance change layer 3 included in the resistance change element 10 changes.

[Method of manufacturing variable resistance element]
Next, a method for manufacturing the variable resistance element 10 will be described.

  First, the lower electrode 2 having a thickness of 0.2 μm is formed on the substrate 1 by sputtering. Thereafter, an oxygen-deficient tantalum oxide layer is formed on the lower electrode 2 by a so-called reactive sputtering method in which a Ta target is sputtered in argon gas and oxygen gas. Here, the oxygen content in the tantalum oxide layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas. The substrate temperature can be set to room temperature without any particular heating.

  Next, the surface of the tantalum oxide layer formed as described above is modified by oxidizing it. Thereby, a region (second region) having a higher oxygen content than the region (first region) where the tantalum oxide layer was not oxidized is formed on the surface of the tantalum oxide layer. These first region and second region correspond to the first tantalum oxide layer 3a and the second tantalum oxide layer 3b, respectively, and the first tantalum oxide layer 3a and the second tantalum oxide formed in this way. The variable resistance layer 3 is configured by the layer 3b.

  If a region having a high oxygen content is to be formed on the lower side, a film containing a high oxygen content may be formed first by sputtering, CVD, or an ALD (Atomic Layer Deposition) method instead of oxidizing. Good.

  Next, the variable resistance element 10 is obtained by forming the upper electrode 4 having a thickness of 0.2 μm by sputtering on the variable resistance layer 3 formed as described above.

In addition, the magnitude | size and shape of the lower electrode 2, the upper electrode 4, and the resistance change layer 3 can be adjusted with a mask and lithography. In the present embodiment, the size of the upper electrode 4 and the resistance change layer 3 is 0.5 μm × 0.5 μm (area 0.25 μm ² ), and the size of the portion where the lower electrode 2 and the resistance change layer 3 are in contact is also 0. 0.5 μm × 0.5 μm (area 0.25 μm ² ).

In the present embodiment, the composition of the first tantalum oxide layer 3a is TaO _x (x = 1.54), and the composition of the second tantalum oxide layer 3b is TaO _y (y = 2.47). . Furthermore, the thickness of the resistance change layer 3 is 30 nm, the thickness of the first tantalum oxide layer 3a is 25 nm, and the thickness of the second tantalum oxide layer 3b is 5 nm.

  As described above, in this embodiment, x = 1.54 and y = 2.47, but the values of x and y are not limited to this. As described above, the value of x is in the range of 0.8 to 1.9 (0.8 ≦ x ≦ 1.9), and the value of y is in the range of 2.1 to less than 2.5 (2 .Ltoreq.y.ltoreq.2.5), a stable resistance change can be realized in the same manner as the resistance change characteristic in the present embodiment.

[Characteristics of variable resistance element]
Next, characteristics of the variable resistance element 10 according to the present embodiment configured as described above will be described.

  2A to 2F are diagrams showing resistance-voltage characteristics of the variable resistance element according to Embodiment 1 of the present invention. The data shown in FIGS. 2A to 2F is that a predetermined voltage pulse is applied to the variable resistance element 10 with a load resistance having a resistance value of 1 kΩ connected in series to the variable resistance element 10. It was obtained by. Here, the load resistance has an effect of making it easy to set the voltage by reducing the rapid progress of the resistance change phenomenon when the variable resistance element is changed from the high resistance state to the low resistance state.

2A to 2F show the case where the write voltage pulse V _REC is −1.00V, −1.25V, −1.50V, −1.75V, −2.00V and −2.25V, respectively. The resistance-voltage characteristic of the resistance change element 10 of this Embodiment in is shown, respectively. Here, the write voltage pulse V _REC means a voltage pulse (here, a pulse width of 100 ns) applied between the lower electrode 2 and the upper electrode 4 in the configuration of the resistance change element in FIG. By applying these write voltage pulses V _REC between the lower electrode 2 and the upper electrode 4, the resistance value of the resistance change element 10 decreases, and the resistance change element 10 is a high resistance which is an example of the first resistance state. The state is changed to a low resistance state which is an example of the second resistance state.

Referring to FIG. 2A, when the write voltage pulse V _REC is −1.00 V, that is, a voltage pulse of −1.00 V is applied between the lower electrode 2 and the upper electrode 4, and the resistance change element 10 has a high resistance. When the state changes from the low resistance state to the low resistance state, the resistance change element 10 changes from the low resistance state to the high resistance state when a voltage pulse greater than +1.00 V is applied between the lower electrode 2 and the upper electrode 4. It can be seen that it is. Similarly, referring to FIGS. 2B to 2F, when the write voltage pulse V _REC is −1.25V, −1.50V, −1.75V, −2.00V and −2.25V, respectively. Then, when a voltage pulse larger than + 1.25V, + 1.50V, + 1.75V, + 2.00V and + 2.25V is applied between the lower electrode 2 and the upper electrode 4, respectively, the resistance change element 10 is changed from a low resistance state to a high resistance state. It turns out that it changes to the direction of a resistance state.

As described above, by applying a voltage pulse having a reverse polarity with a voltage value larger in absolute value than the write voltage pulse V _REC between the lower electrode 2 and the upper electrode 4, the resistance change element 10 is changed from the low resistance state to the high resistance state. It can be said that it can be changed. The existence of such a characteristic in the variable resistance element can be confirmed from the current-voltage characteristic.

  3A to 3F are diagrams showing current-voltage characteristics of the variable resistance element according to Embodiment 1 of the present invention. 3A to 3F, the data shown in FIGS. 3A to 3F are obtained in a state in which a load resistance having a resistance value of 1 kΩ is connected in series to the variable resistance element 10, as in FIGS. 2A to 2F. This is obtained by applying a predetermined voltage pulse to the variable resistance element 10.

FIGS. 3A to 3F show the current flowing through the resistance change element 10 when the voltage shown in the figure is applied between the lower electrode 2 and the upper electrode 4, respectively. The current-voltage characteristics of the variable resistance element 10 of the present embodiment when −1.00 V, −1.25 V, −1.50 V, −1.75 V, −2.00 V, and −2.25 V are shown, respectively. ing. Referring to FIG. 3A, when the lower limit voltage on the negative side is −1.00 V (corresponding to the write voltage), the resistance change occurs when a voltage pulse of +1.00 V is applied between the lower electrode 2 and the upper electrode 4. The value of the current flowing through the element 10 shows a peak. Similarly, referring to FIGS. 3B to 3F, when the write voltage pulse V _REC is −1.25V, −1.50V, −1.75V, −2.00V and −2.25V, When the voltage pulses of + 1.25V, + 1.50V, + 1.75V, + 2.00V, and + 2.25V are applied between the lower electrode 2 and the upper electrode 4, respectively, the current value flowing through the resistance change element 10 peaks. You can see that

As described above, the resistance change element is applied until the voltage pulse V ′ _REC (= −V _REC ) having the same polarity as the negative write voltage pulse V _REC is applied between the lower electrode 2 and the upper electrode 4. 10 indicates a low resistance state, and it is understood that the resistance change element 10 changes from the low resistance state to the high resistance state when a voltage pulse having a reverse polarity larger than the write voltage pulse V _REC is applied.

In the present invention, as described above, the resistance change element 10 changes from the low resistance state to the high resistance state when a voltage pulse having a polarity greater than the write voltage pulse V _REC is applied between the lower electrode 2 and the upper electrode 4. Multi-value storage is realized by utilizing the characteristic of the resistance change element that changes in the direction.

[Principle of multi-level memory]
FIG. 4 is a diagram showing the principle of multilevel storage in Embodiment 1 of the present invention. In FIG. 4, the vertical axis represents the resistance value of the resistance change element 10, and the horizontal axis represents the voltage value of the voltage pulse applied between the lower electrode 2 and the upper electrode 4. As described above, the reverse polarity (second polarity, here positive) of the voltage value larger than the write voltage pulse V _REC (here, -V1, -V2, -V3...) Having the first polarity (here negative). ) Voltage pulses (here, V1, V2, V3...) Are applied between the lower electrode 2 and the upper electrode 4 so that the resistance change element 10 changes from the second resistance state (here, the low resistance state) to the second resistance state. It changes in the direction of 1 resistance state (here, high resistance state). Therefore, as shown in FIG. 4, when the write voltage pulse V _REC = −V1, the resistance value of the variable resistance element 10 increases when a voltage pulse larger than the voltage value + V1 is applied to the upper electrode 4. Similarly, when the write voltage pulse V _REC = −V2, when a voltage pulse larger than the voltage value + V2 is applied to the upper electrode 4, when the write voltage pulse V _REC = −V3, the voltage pulse larger than the voltage value + V3. When the is applied to the upper electrode 4, the resistance value increases.

If such characteristics are used, when a high voltage pulse is applied between the lower electrode 2 and the upper electrode 4 in order from the smaller voltage, the resistance change element 10 changes from the low resistance state to the high resistance state. By specifying the voltage value V of the voltage pulse applied to the upper electrode 4 when it is first changed, the voltage value of the write voltage pulse V _REC can be estimated. That is, when V1 <V ≦ V2 is satisfied can the voltage value of the write voltage pulse V _REC is estimated to be -V1. Further, when V2 <V ≦ V3 is satisfied can the voltage value of the write voltage pulse V _REC is estimated to be -V2. Furthermore, if V3 <V is satisfied can the voltage value of the write voltage pulse V _REC is estimated to be -V3. Here, the write voltage pulse V _REC = −V 1 corresponds to the data “1”, the write voltage pulse V _REC = −V 2 corresponds to the data “2”, and the write voltage pulse V _REC = −V 3 corresponds to the data “3”. When V1 <V ≦ V1 is satisfied, it is determined that the written data is data “1”. When V2 <V ≦ V3 is satisfied, it is determined that the written data is data “2”. If V3 <V holds, it can be determined that the written data is data “3”. That is, the resistance change element 10 can be handled as a nonvolatile multi-value storage element.

Thus, by specifying the voltage value V, it is possible to read out the written data. For this reason, after the writing process is performed by the writing voltage pulse V _REC , a plurality of voltage pulses having different voltage values are sequentially applied between the two electrodes in ascending order, and the resistance change element 10 is in a low resistance state in the process. The data can be read out by specifying whether the current has changed from the low resistance state to the high resistance state (that is, the voltage when the low resistance state first changed to the high resistance state). Hereinafter, a voltage pulse applied between the lower electrode 2 and the upper electrode 4 in the reading process will be referred to as a read voltage pulse V _READ . The relationship between the read voltage pulse V _READ and the write voltage pulse V _REC will be further described in detail.

FIG. 5 shows write voltage pulses V _REC (1), V _REC (2),..., V _REC (m) and read voltage pulses V _READ (1), V _READ (2) according to the first embodiment of the present invention. ,..., V _READ (n). The voltages V ′ _REC (1), V ′ _REC (2),..., V ′ _REC (m) are written voltage pulses V _REC (1), V _REC (2) _{,. This} is a reverse polarity voltage (= −V _REC (1), −V _REC (2),..., −V _REC (m)) whose voltage value is almost the same as _REC (m). Here, m and n are each a positive integer. In FIG. 5, the vertical axis represents the value of the current flowing through the resistance change element 10, and the horizontal axis represents the voltage value of the voltage pulse applied between the lower electrode 2 and the upper electrode 4. Note that the data shown in FIG. 5 is a predetermined voltage pulse in a state where a load resistance having a resistance value of 1 kΩ is connected in series to the resistance change element 10 as in the cases of FIGS. Is given to the variable resistance element 10.

In the present embodiment, the write voltage pulse V _REC (m) is set in advance so that the voltage value increases as the value of m increases. In addition, as the value of n increases, the voltage value also increases and the read voltage pulse V _READ (n) is preset so that V ′ _REC (m) <V _READ (n) ≦ V ′ _REC (m + 1) is satisfied. ing. Then, after applying the write voltage pulse V _REC (m) between both electrodes, the read voltage pulse V _READ (n) is applied between both electrodes in order from the smallest value of n. The relationship between the write voltage pulse V _REC (m) (or V ′ _REC (m)) and the read voltage pulse V _READ (n) at this time is as shown in FIG. Here, when the variable resistance element 10 first changes from the low resistance state to the high resistance state when n = 1 (when the value of the current flowing through the variable resistance element 10 decreases), it is determined that m = 1. If n = 2 and the first change occurs, it can be determined that m = 2. In this way, by specifying the value of m, it is possible to know which voltage value of the write voltage pulse was used for writing.

[Embodiment 1 of Driving Method of Resistance Change Element]
FIG. 6 is a flowchart showing an example of the procedure of the method of driving the variable resistance element according to Embodiment 1 of the present invention. Hereinafter, the writing process, the reading process, and the rewriting process will be described separately. Here, the rewriting process is necessary because the resistance change element 10 changes from the low resistance state to the high resistance state as a result of performing the reading process, and therefore it is necessary to return this to the original low resistance state. It is. In other words, since reading in this embodiment mode is so-called destructive reading, a rewriting step is necessary. Therefore, if it is not necessary to perform reading again, it is not necessary to perform a rewriting process.

In the following, the voltage value of m write voltage pulses V _REC (m) and n read voltage pulses V _READ are expressed as V ′ _REC (m) <V _READ (n) ≦ V ′ _REC (m + 1). It is assumed that it is set in advance so that

(1) Write Step First, in the write step, the value of m (m ≧ 1) of the write voltage pulse V _REC (m) is determined according to the value of data to be stored (S101). Then, the write voltage pulse V _REC (m) is applied between the lower electrode 2 and the upper electrode 4 (S102), and the write process is completed. As a result of this writing step, the resistance change element 10 changes from a high resistance state to one of a plurality of low resistance states.

(2) Read process In the read process executed after the completion of the above write process, the confirmation voltage pulse V _{CHECK to the} extent that the resistance change element 10 does not change in resistance (voltage smaller than the write threshold voltage, for example, +0.5 V or less). Is applied between both electrodes (S201), and the value of the current flowing through the resistance change element 10 at that time is measured using a sense amplifier or the like (S202). Then, the current value measured in step S202 is set to a specified value used to determine whether the resistance change element 10 is in a high resistance state or a low resistance state (S203). That is, in order to detect that the resistance change element 10 has first changed from the low resistance state to the high resistance state, the resistance state before the change is measured and stored in advance as a specified value.

Next, n of the read voltage pulse V _READ (n) is set to 1 (S204), and the read voltage pulse V _READ (n) is applied between both electrodes (S205). Thereafter, a confirmation voltage pulse V _CHECK is applied between both electrodes (S206), and the value of the current flowing through the resistance change element 10 at that time is measured using a sense amplifier or the like (S207).

  Next, the current value measured in step S207 is compared with the specified value set in step S203, and whether or not the current value is smaller than the specified value (the resistance change element 10 is changed from the low resistance state to the high resistance value). It is determined whether or not the state has changed (S208). If it is determined that the current value is not smaller than the specified value (NO in S208), n is incremented by 1 (S209), and the process returns to step S205. On the other hand, if it is determined that the current value is smaller than the specified value (YES in S208), that is, it is determined that the resistance change element has first changed from the low resistance state to the high resistance state, and the value of n is m (S210) and the reading process is terminated.

  Since the value of m can be specified by this reading process, it is possible to determine at which voltage value the writing voltage pulse has been written, and reading the multi-value data written by the writing process. Is realized.

Thus, in the read process, when the read voltage pulse is sequentially applied from the smaller one, the magnitude of the read voltage pulse that first changed the resistance change element 10 from the low resistance state to the high resistance state is: Depending on which of the plurality of different magnitudes V _READ (1) to V _READ (m), which of the plurality of different magnitudes of write voltage pulses V _REC (1) to V _REC (m) is written It is determined whether the writing process has been performed by the voltage pulse.

(3) Rewriting Step After performing step S210 in the reading step, a writing voltage pulse V _REC (m) is applied between the lower electrode 2 and the upper electrode 4 for rewriting (S102). Thereby, the same data as the data written in the previous writing process is written.

By the above operation, m of the write voltage pulse V _REC (m) used in the write process can be specified, and therefore it is determined that data corresponding to the write voltage pulse V _REC (m) has been stored. Can do. Thereby, multi-value storage of m values can be realized.

  As described above, in the present embodiment, the variable resistance element is changed to the second resistance depending on the magnitude of the write electric pulse applied when the variable resistance element is changed from the first resistance state to the second resistance state. Since the characteristic of the bipolar variable resistance element that determines the magnitude of the minimum read electrical pulse required to change from the state to the first resistance state is utilized, stable multi-value storage is realized. .

[Second Embodiment of Driving Method of Resistance Change Element]
In the first embodiment of the driving method of the resistance change element, the case where the resistance change element 10 is changed from the high resistance state to the low resistance state by writing is illustrated. In general, the resistance change element is more stable in the low resistance state than the high resistance state with less variation in resistance value, and writing is performed by reducing the resistance of the resistance change element 10 as described above. As compared with the case where writing is performed by increasing the resistance, better retention characteristics can be obtained. However, conversely, the case where the resistance change element 10 is changed by writing from a low resistance state, which is another example of the first resistance state, to a high resistance state, which is another example of the second resistance state. However, multi-level storage can be realized by the same procedure. The operation in that case will be described with reference to FIG.

  FIG. 7 is a flowchart showing another example of the procedure of the variable resistance element driving method according to Embodiment 1 of the present invention. 7 is different from FIG. 6 only in step S308 executed after step S207. Therefore, processes other than step S308 are denoted with the same reference numerals as in FIG.

  By step S102 in the writing process, the resistance change element 10 changes from the low resistance state (here, the first resistance state) to the high resistance state (here, the second resistance state). In the subsequent reading process, after executing steps S201 to S207 in the same manner as described above, the current value measured in step S207 is compared with the specified value set in step S203, and the current value is determined as the specified value. Whether or not the resistance change element 10 has changed from the high resistance state (here, the second resistance state) to the low resistance state (here, the first resistance state). Determination is made (S308). Then, as in the case described above, the process proceeds to step S209 or S210 depending on the result of the determination, and the process proceeds to the rewriting process after step S210 is completed.

  With the above operation, even when writing is performed by changing the resistance change element 10 from the high resistance state to the low resistance state, writing is performed by changing the resistance change element 10 from the low resistance state to the high resistance state. Multi-level storage can be realized.

  In the above two examples, the value of the current flowing through the resistance change element 10 is measured in steps S202 and S207. However, the resistance value of the resistance change element 10 may be measured based on this current value. In this case, in step S208, it is determined whether or not the resistance value measured in step S207 is larger than the default value. In step S308, whether or not the resistance value measured in step S207 is smaller than the default value. It will be determined whether or not.

[Experimental example]
Next, an experimental example in which writing and reading are performed according to the procedure described with reference to FIG. 6 will be described. In this experimental example, the voltage values V _REC (m, m = 1, 2,..., 7) of the write voltage pulse are −1V, −1.25V, −1.5V, −1.75V, and −2V, respectively. , -2.25V and -2.5V. Further, the voltage value of the read voltage pulse V _READ (n, n = 1, 2,..., 7) is set so that V ′ _REC (m) <V _READ (n) ≦ V ′ _REC (m + 1). They were + 1.2V, + 1.45V, + 1.7V, + 1.95V, + 2.2V, + 2.45V and + 2.7V, respectively. The lower electrode 2 of the variable resistance element 10 used in this experimental example is made of tantalum nitride (TaN), and the upper electrode 4 is made of iridium (Ir).

FIGS. 8A and 8B are diagrams showing the results of an experimental example of writing and reading in the first embodiment of the present invention. FIG. 8A shows a change in resistance value of the resistance change element 10 when a write voltage pulse and a read voltage pulse are repeatedly applied between the lower electrode 2 and the upper electrode 4, and FIG. The evaluation of the result is shown. In this experimental example, the write process is repeatedly executed while increasing m of the write voltage pulse V _REC (m) sequentially from 1 to 7. In this experimental example, the rewriting process is not executed. Hereinafter, description will be made with reference to the flowchart of FIG.

As shown in FIG. 8A, a write voltage pulse V _REC (1) of −1 V is applied between both electrodes in the write process (S102), and the resistance change element 10 is changed from the high resistance state to the low resistance state. ing. Next, as a result of applying a read voltage pulse V _READ (1) of _+1.2 V between both electrodes in the read process (S205), the resistance change element 10 changes from the low resistance state to the high resistance state. Thereafter, a write voltage pulse V _REC (2) of −1.25 V is applied between both electrodes in the write process (S102). As a result, the resistance change element 10 changes from the high resistance state to the low resistance state again. Next, when a read voltage pulse V _READ (1) of _+1.2 V is applied between both electrodes in the read process (S205), it is not determined that the current value is smaller than the specified value (NO in S208), and as a result n is incremented by 1 (S209), and a read voltage pulse V _READ (2) of +1.45 V is applied between both electrodes (S205). In this case, as shown in FIG. 8A, the resistance change element 10 changes from the low resistance state to the high resistance state.

  Thereafter, when the writing process is executed while incrementing m by 1, similarly, n is similarly incremented by 1 in the reading process. This is shown in FIGS. 8A and 8B. In FIG. 8B, the case where the reading is successful, that is, the case where it is determined in step S208 that the current value is smaller than the predetermined value and step S210 is executed is indicated by ○, and the current value is determined in step S208. The case where it is determined that the value is not smaller than the predetermined value and the process proceeds to step S209 is indicated by x.

  As described above, in this experimental example, reading and writing of 7-value data is realized. By setting the voltage values of the write voltage pulse and the read voltage pulse more finely, it is possible to realize reading and writing of data with a larger amount of information.

(Embodiment 2)
In the first embodiment, as shown in FIGS. 6 and 7, the confirmation voltage pulse V _CHECK is applied between the lower electrode 2 and the upper electrode 4 in the reading process, but this process is not essential to the present invention. Absent. The second embodiment is a method of driving a resistance change element in which the application of the confirmation voltage pulse V _CHECK in such a reading process is omitted. The configuration of the variable resistance element is the same as that in the first embodiment, and thus the description thereof is omitted.

  FIG. 9 is a flowchart showing an example of the procedure of the resistance change element driving method according to the second embodiment of the present invention. FIG. 9 shows a procedure in the writing process, the reading process, and the rewriting process. Of these, the writing process and the rewriting process are the same as those in the first embodiment, and thus the same reference numerals are given. Description is omitted.

In the reading step, first, n of the reading voltage pulse V _READ (n) is set to 0 (S401), and the reading voltage pulse V _READ (n) is applied between the lower electrode 2 and the upper electrode 4 (S402). At this time, the current value I _READ (n) flowing through the resistance change element 10 is measured using a sense amplifier or the like (S403).

Next, it is determined whether n is 0 (S404). If it is determined that n is 0 (YES in S404), n is incremented by 1 (S405), and the process returns to step S402. On the other hand, if it is determined that n is not a 0 (NO in S404), the current value I _READ (n) whether smaller than the current value I _READ (n-1) (the variable resistance element 10 from the low resistance state It is determined whether or not the direction has changed to the high resistance state (S406).

If it is determined in step S406 that the current value I _READ (n) is not smaller than the current value I _READ (n−1) (NO in S406), n is incremented by 1 (S405), and the process returns to step S402. On the other hand, when it is determined that the current value I _READ (n) is smaller than the current value I _READ (n−1) (YES in S406), it is determined that the value of n is the value of m (S407). The reading process is terminated. In the determination of the magnitude between the current value I _READ (n) and the current value I _READ (n−1), the current value I _READ exceeds a predetermined margin (change amount) in order to absorb the variation in the measured value. It is determined whether or not (n) is smaller than the current value I _READ (n−1), that is, whether or not the resistance value of the resistance change element has changed more than a predetermined amount of change.

  As described above, in the read process, when the read voltage pulse is sequentially applied from the smaller one, the resistance value of the resistance change element is larger than the predetermined change amount from the resistance value when the read voltage pulse is applied immediately before. When a large change is detected, it is detected that the resistance change element has first changed from the low resistance state to the high resistance state.

  Since the value of m can be specified by this reading process, it is possible to determine at which voltage voltage the writing voltage pulse has been written, and reading the multi-value data written by the writing process. Is realized.

  As in the case of the first embodiment, the method for driving the resistance change element according to the second embodiment also changes the resistance change element 10 from the low resistance state, which is another example of the first resistance state, by writing. It can be used even when changing to a high resistance state, which is another example of the resistance state. The operation in that case will be described with reference to FIG.

  FIG. 10 is a flowchart showing another example of the procedure of the variable resistance element driving method according to Embodiment 2 of the present invention. 10 is different from FIG. 9 only in step S506 executed after step S404. Therefore, processes other than step S506 are denoted by the same reference numerals as in FIG.

By step S102 in the writing process, the resistance change element 10 changes from the low resistance state (here, the first resistance state) to the high resistance state (here, the second resistance state). In the subsequent reading step, after performing the steps S401 to S405 in the same manner as described above, whether the current value I _READ (n) is greater than the current value I _READ (n-1) (the variable resistance element 10 Is changed from the high resistance state (here, the second resistance state) to the low resistance state (here, the first resistance state)) (S506). Then, as in the case described above, the process proceeds to step S405 or S407 depending on the result of the determination, and the process proceeds to the rewriting process after step S407 is completed.

  With the above operation, even when writing is performed by changing the resistance change element 10 from the high resistance state to the low resistance state, writing is performed by changing the resistance change element 10 from the low resistance state to the high resistance state. Multi-level storage can be realized.

(Embodiment 3)
In the first embodiment, the multi-value storage by voltage driving in which the voltage pulse is applied to the resistance change element has been described. However, the resistance change element driving method and the nonvolatile memory element according to the present invention change the current pulse to resistance change. Multi-value storage by current drive applied to the element may be employed. Hereinafter, multi-value storage by current drive will be described.

[Third Embodiment of Driving Method of Resistance Change Element]
FIG. 11 is a diagram showing a relationship between the write current pulse I _REC and the read voltage pulse V _{READ in the} multi-value storage by current driving according to the third embodiment (however, reading is performed by voltage driving / current reproduction). This diagram corresponds to FIG. 5 showing the same relationship in multi-value storage in voltage drive. The current I ′ _REC is a reverse polarity current (= −I _REC ) having the same current value as the write current pulse I _REC . Voltage V _'REC, a current I' voltage corresponding to the _REC, i.e., the value of the voltage drop across the variable resistance element 10 when the current I _'REC is applied to the variable resistance element. In FIG. 11, the vertical axis represents the current value flowing through the resistance change element 10, and the horizontal axis represents the voltage value of the voltage pulse applied between the lower electrode 2 and the upper electrode 4. Note that the data shown in FIG. 11 is a predetermined current in a state where a load resistance having a resistance value of 1 kΩ is electrically connected to the resistance change element 10 as in the cases of FIGS. Although it is obtained by applying a pulse to the variable resistance element 10, in the case of current driving, it is easy to control to a predetermined current value when the resistance is reduced without load resistance. Is not necessarily required.

In the present embodiment, the write current pulse I _REC (m) is set in advance so that the current value increases as the value of m increases. In addition, as the value of n increases, the voltage value also increases and the read voltage pulse V _READ (n) is preset so that V ′ _REC (m) <V _READ (n) ≦ V ′ _REC (m + 1) is satisfied. ing.

Then, after applying a write current pulse I _REC (m) between both electrodes, a read voltage pulse V _READ (n) is applied to the upper electrode 4 in order from the smallest value of n. The relationship between the write current pulse I _REC (m) and the voltage V ′ _REC (m) at this time is as shown in FIG. Here, when the variable resistance element 10 first changes from the low resistance state to the high resistance state when n = 1 (when the value of the current flowing through the variable resistance element 10 decreases), it is determined that m = 1. If n = 2 and the first change occurs, it can be determined that m = 2. In this way, by specifying the value of m, it is possible to know at which current value the write current pulse was used for writing.

  FIG. 12 is a flowchart showing an example of a procedure of a resistance change element driving method in multi-value storage by current driving (however, reading is performed by voltage driving / current regeneration). This figure corresponds to FIG. 6 showing the procedure of the driving method in multi-value storage by voltage driving. Differences from the flowchart shown in FIG. 6 are as follows.

In the write process, first, the value of m (m ≧ 1) of the write current pulse I _REC (m) is determined according to the value of data to be stored (S601). Then, the write current pulse I _REC (m) is applied to the variable resistance element 10 (S602), and the write process is completed. As a result of this writing process, the resistance change element 10 changes from the high resistance state to the low resistance state.

The reading process (S201 to S210) is the same as the procedure in the voltage driving shown in FIG. However, the current value of m write current pulses I _REC (m) is determined in advance, and n corresponding read voltage pulses V _READ are V ′ _REC (m) <V _READ (n) ≦ V ′. _The point set in advance to be _REC (m + 1) is different from the case of voltage driving. Since the value of m can be specified by this reading process, it is possible to determine at which current value the writing current pulse was written, and reading the multi-value data written by the writing process. Is realized.

Thus, in the read process, when the read voltage pulse is sequentially applied from the smaller one, the magnitude of the read voltage pulse that first changed the resistance change element 10 from the low resistance state to the high resistance state is: Depending on which of a plurality of different magnitudes V _READ (1) to V _READ (n), which of the plurality of different magnitudes of write current pulses I _REC (1) to V _REC (m) is written It can be determined whether the writing process has been performed by the current pulse.

In the rewriting process, after executing step S210 in the reading process, a write current pulse I _REC (m) is applied to the variable resistance element 10 for rewriting (S602). Thereby, the same data as the data written in the previous writing process is written.

By the above operation, m of the write current pulse I _REC (m) used in the write process can be specified, and therefore it is determined that data corresponding to the write current pulse I _REC (m) has been stored. Can do. Thereby, multi-value storage of m values can be realized.

Note that in the read process of multi-value storage by current driving, reading is performed by voltage driving (current regeneration), but reading may be performed by current driving. At that time, in the read process, the read current pulse I _READ (n) is applied to the resistance change element 10, and the current value increases as the value of n increases, and I ′ _REC (m) <I _A read current pulse I _READ (n) is applied to the resistance change element 10 so that _READ (n) ≦ I ′ _REC (m + 1) is satisfied.

[Embodiment 4 of Driving Method of Resistance Change Element]
Further, in Example 3 of the driving method of the resistance change element, a current pulse that changes from the high resistance state to the low resistance state is applied at the time of writing, but an example of the driving method of the resistance change element of the first embodiment is used. As shown in FIG. 2, a current pulse that changes from a low resistance state to a high resistance state at the time of writing may be applied to the selected memory cell. In that case, in the reading step of the flowchart shown in FIG. 12, the criterion for determining the measured current value in S208 is “current value> specified value?”.

(Embodiment 4)
As shown in the second embodiment described above, also in the third embodiment, the processes from the application step (S201) of the confirmation voltage pulse V _CHECK to the setting step (S203) of the specified value in the reading step of FIG. It is not essential to the present invention. The fourth embodiment omits from the application of the confirmation voltage pulse V _CHECK to the setting of the specified value in such a reading process, and includes the writing process of the third embodiment and the reading process of the second embodiment. This is a driving method of the resistance change element. Since the driving operation and the flowchart are the same as those described in the above-described embodiments, the detailed description thereof is omitted.

(Embodiment 5)
The fifth embodiment is a cross-point type nonvolatile memory device including the variable resistance element described in the first to fourth embodiments and a peripheral circuit that realizes the driving method thereof. Here, the cross-point type nonvolatile memory device is a memory device in which a resistance change element is arranged at an intersection (a three-dimensional intersection) between a word line and a bit line.

  Hereinafter, the configuration and operation of the nonvolatile memory device according to Embodiment 5 will be described.

[Configuration of non-volatile storage device]
FIG. 13 is a block diagram showing an example of the configuration of the nonvolatile storage device (here, storage device 100) according to the fifth embodiment of the present invention. As shown in FIG. 13, the cross-point type storage device 100 includes a memory cell array 101 including memory cells each including the variable resistance element according to the present application arranged in a plurality of arrays, an address buffer 102, and a control A unit 103, a row decoder 104, a word line driver 105, a column decoder 106, and a bit line driver 107 are provided.

  As shown in FIG. 13, the memory cell array 101 includes a plurality of word lines W1, W2, W3,... Formed in parallel to each other and extending in the first direction, and these word lines W1, W2, W3,. ... and a plurality of bit lines B1, B2, B3, ... formed so as to extend in the second direction in parallel with each other. Here, the word lines W1, W2, W3,... Are formed in a first plane parallel to the main surface of the substrate (not shown), and the bit lines B1, B2, B3,. It is formed in a second plane located above the one plane and substantially parallel to the first plane. Therefore, the word lines W1, W2, W3,... And the bit lines B1, B2, B3,... Are three-dimensionally crossed, and a plurality of memory cells MC11, MC12, MC13, MC21, MC22 correspond to the three-dimensional intersections. , MC23, MC31, MC32, MC33,... (Hereinafter referred to as “memory cells MC11, MC12,...”).

  Each memory cell MC includes resistance change elements connected in series and current control elements D11, D12, D13, D21, D22, D23, D31, D32, D33,. The resistance change elements are connected to the bit lines B1, B2, B3,..., And the current control elements are connected to the resistance change elements and the word lines W1, W2, W3,. The current control element has a threshold voltage in each of a positive applied voltage region and a negative applied voltage region, and is turned on when the absolute value of the applied voltage is larger than the absolute value of each threshold voltage. When the voltage value is in a region other than that (when the absolute value of the applied voltage is smaller than the absolute value of the corresponding threshold value), it has a non-linear characteristic so as to be in a cutoff (off) state.

  As the resistance change element, the resistance change element 10 according to the first embodiment can be used. The current control element (in this case, a bidirectional diode) may also serve as a load element connected in series to the resistance change layer included in the resistance change element constituting the memory cell.

  The address buffer 102 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 104 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 106. . Here, the address signal ADDRESS is a signal indicating the address of the selected memory cell among the memory cells MC11, MC12,. The row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS, and the column address signal COLUMN is a signal similarly indicating a column address.

  In response to the mode selection signal MODE received from the external circuit, the control unit 103 selects one of the write mode (corresponding to the above-described writing process and the rewriting process) and the read mode (corresponding to the above-described reading process). Select a mode and execute.

In the write mode, the control unit 103 responds to output the write voltage pulse V _REC (m) or the write current pulse I _REC (m) to the selected word line according to the input data Din received from the external circuit. The word line driver 105 to be controlled is controlled.

In the read mode, the control unit 103 outputs the read voltage pulse V _READ (n), the read current pulse I _READ (n), or the confirmation voltage pulse V _CHECK to the selected word line. The driver 105 is controlled. In this read mode, the control unit 103 is further based on a read signal I _READ (when V _READ (n) is applied) or V _READ (when I _READ (n) is applied) output from a sense amplifier (not shown). Output data Dout indicating the bit value of the selected memory cell corresponding to the specified write voltage pulse V _REC (m) or write current pulse I _REC (m) is output to an external circuit. The read signal I _READ or V _READ is a signal indicating a current value or a voltage value flowing through the word lines W1, W2, W3,... Or a voltage generated at both ends of the resistance change element in the read mode.

When it is desired to generate a plurality of different voltage pulses, the word line driver 105 includes, for example, a ladder resistor circuit in its power supply unit. By using this ladder resistor circuit, m write voltage pulses V having different voltage values are provided. _REC (m) and n read voltage pulses V _READ (n) having different voltage values can be output. In addition, when it is desired to generate a plurality of different current pulses, for example, a plurality of driver circuits of different sizes are provided, and a plurality of different current pulses are generated by appropriately combining them, or the gate voltage of the transistors constituting the driver circuit This can be realized by providing a circuit for controlling the above.

  The row decoder 104 receives the row address signal ROW output from the address buffer 102, and selects any one of the word lines W1, W2, W3,... According to the row address signal ROW. The word line driver 105 applies an activation voltage to the word line selected by the row decoder 104 based on the output signal of the row decoder 104.

  The column decoder 106 receives the column address signal COLUMN output from the address buffer 102, and selects any one of the bit lines B1, B2, B3,... According to the column address signal COLUMN. The bit line driver 107 sets the bit line selected by the column decoder 106 to the ground state based on the output signal of the column decoder 106.

  The address buffer 102, the row decoder 104, the word line driver 105, the column decoder 106, and the bit line driver 107 are an example of a selection circuit that selects at least one memory cell from the memory cell array 101, and are controlled by the control unit 103. Works under.

  Note that although this embodiment is a single-layer cross-point storage device, the nonvolatile storage device according to the present invention may be a multi-layer cross-point storage device by stacking memory cell arrays. Further, the positional relationship between the resistance change element and the current control element may be interchanged. That is, the word line may be connected to the resistance change element, and the bit line may be connected to the current control element. Further, the bit line and / or the word line may be configured to also serve as power in the variable resistance element.

[Operation of non-volatile storage device]
The storage device 100 configured as described above has the write voltage pulse V _REC (m) or the write current pulse I _REC (m), the read voltage pulse V _READ (n) or the following procedure described with reference to FIG. The write process, the read process, and the rewrite process described in the first to fourth embodiments are performed by applying the read current pulse I _READ (n) or the confirmation voltage pulse V _CHECK as occasion _demands to the selected memory cell. . Hereinafter, an example in which a writing process and a reading process are performed on the memory cell MC22 will be described with reference to the flowchart of FIG. 6 as appropriate.

[Write mode]
When data representing data “1” is written in the memory cell MC22, the bit line driver 107 grounds the bit line B2, and the word line driver 105 electrically connects the word line W2 and the control unit 103. Then, the write voltage pulse V _REC (1) is applied to the word line W2 by the control unit 103 (S102). Here, the voltage value of the write voltage pulse V _REC (1) is set to −1.0 V, for example, and the pulse width is set to 100 ns. By such an operation, the write voltage pulse V _REC (1) is applied to the resistance change element of the memory cell MC22, and the resistance change element of the memory cell MC22 enters the low resistance state corresponding to the data “1”.

Further, when data representing data “2” is written in the memory cell MC22, the write voltage pulse V _REC (2) is applied to the word line W2 by the control unit 103 in the same manner. Here, the voltage value of the write voltage pulse V _REC (2) is set to −1.25 V, for example, and the pulse width is set to 100 ns. By such an operation, the write voltage pulse V _REC (2) is applied to the resistance change element of the memory cell MC22, and the resistance change element of the memory cell MC22 enters the low resistance state corresponding to the data “2”.

Further, when data representing data “3” is written in the memory cell MC22, for example, a write voltage pulse V _REC (3) of −1.5 V is written, and when data representing data “4” is written into the memory cell MC22. For example, a write voltage pulse V _REC (4) of −1.75 V is applied to each resistance change element of the memory cell MC22. As a result, the resistance change element of the memory cell MC22 is in a low resistance state corresponding to data “3” and data “4”, respectively.

  Note that, here, the resistance change element of the memory cell MC22 is expressed for convenience when it becomes a low resistance state corresponding to “1” to “4”, but the resistance value of the resistance change element in the low resistance state is almost the same in any case. Are the same.

As described above, by applying the write voltage pulse V _REC (m) to the resistance change element of the selected memory cell, m-value multi-value data (for example, 2 bits for 4 values) is applied to one memory cell. Can be written).

[Read mode]
When reading data written in the memory cell MC22, the bit line B2 is grounded by the bit line driver 107, and the word line W2 and the control unit 103 are electrically connected by the word line driver 105. Then, while the n is incremented by 1 (S209), the controller 103 applies the read voltage pulse V _READ (n) and the confirmation voltage pulse V _CHECK to the word line W2 (S205 and S206). Here, the voltage value of the read voltage pulse V _READ (n) is set to satisfy V ′ _REC (m) <V _READ (n) ≦ V ′ _REC (m + 1).

When the confirmation voltage pulse V _CHECK is applied to the memory cell MC22, a current having a current value corresponding to the resistance value of the resistance change layer of the memory cell MC22 flows between the bit line B2 and the word line W2. Control unit 103 measures this current value using a sense amplifier (S207), and based on the comparison result between the current value and a predetermined specified value, is the resistance change element of memory cell MC22 in a high resistance state? It is determined whether the resistance state is low (S208). When it is determined that the variable resistance element is in a high resistance state, it is determined that n = m, and m of the write voltage pulse V _REC (m) is specified (S210). In this example, if the specified m is 1, it can be seen that the data written in the memory cell MC22 is “1”. If the specified m is 2 to 4, it can be seen that the data written in the memory cell MC22 is “2” to “4”, respectively.

  As described above, in the memory device 100 according to the present embodiment, in the writing process, one resistance voltage change is applied to the resistance change element by applying one of the writing voltage pulses of a plurality of different voltages having the first polarity to the resistance change element. The element is changed from the first resistance state to the second resistance state. On the other hand, in the reading process, read voltage pulses of a plurality of different voltages having a second polarity different from the first polarity are sequentially applied from the smaller voltage. Depending on whether the magnitude of the read voltage pulse that first changed the resistance change element in the direction from the second resistance state to the first resistance state was a plurality of different magnitudes, It is determined which of the write voltage pulses of different magnitudes has been used for the write process.

  By operating as described above, the storage device 100 can realize a stable multi-value storage operation.

  7 (flow chart of the first embodiment), FIG. 9 and FIG. 10 (flow chart of the second embodiment), FIG. 12 (flow chart of the third embodiment), and a flowchart of the fourth embodiment (not shown). In the memory device 100, the operation described in each flowchart is executed by the peripheral circuit of the nonvolatile memory device including the control unit 103, the word line driver, the bit line driver, etc. A memory operation can be realized.

(Embodiment 6)
The sixth embodiment includes the variable resistance element described in the first exemplary embodiment, and a 1T1R type nonvolatile memory in which a unit memory cell includes one transistor and one nonvolatile memory unit (resistance variable element). Device. The configuration and operation of this nonvolatile memory device will be described below.

[Configuration of non-volatile storage device]
FIG. 14 is a block diagram showing an example of the configuration of the nonvolatile storage device (here, storage device 200) according to the sixth embodiment of the present invention. As shown in FIG. 14, the 1T1R type storage device 200 includes a memory cell array 201 including a plurality of resistance change elements arranged in an array, an address buffer 202, a control unit 203, a row decoder 204, A word line driver 205, a column decoder 206, and a bit line / plate line driver 207 are provided.

  As shown in FIG. 14, the memory cell array 201 includes two word lines W1 and W2 extending in the first direction and two bit lines B1 extending in the second direction across the word lines W1 and W2. , B2 and two plate lines P1, P2 provided in one-to-one correspondence with the bit lines B1, B2 and extending in the second direction, and each intersection of the word lines W1, W2 and the bit lines B1, B2 Corresponding to the four transistors T211, T212, T221, and T222, and the four transistors T211, T212, T221, and T222 are connected in series in a one-to-one correspondence and provided in a matrix. The resistance change elements MC211, MC212, MC221, and MC222 are provided, and the corresponding transistors and resistance change elements respectively constitute memory cells. That.

  Note that the number or number of these components is not limited to the above. For example, the memory cell array 201 includes four memory cells as described above, but this is an example, and a configuration including five or more memory cells may be employed.

  The variable resistance elements MC211, MC212, MC221, and MC222 described above correspond to the variable resistance element 10 in the first embodiment. The configuration of the memory cell array 201 will be further described with reference to FIG. 1. The transistor T211 and the resistance change element MC211 are provided between the bit line B1 and the plate line P1, and the resistance of the transistor T211 and the resistance change The terminals connected to the upper electrode 4 of the element MC211 are arranged in series to be connected. More specifically, the transistor T211 is connected to the bit line B1 and the resistance change element MC211 between the bit line B1 and the resistance change element MC211. The resistance change element MC211 is connected to the transistor T211 and the plate line P1. In the meantime, it is connected to the transistor T211 and the plate line P1. The gate of the transistor T211 is connected to the word line W1.

  The connection state of the other three transistors T212, T221, T222 and the three resistance change elements MC212, MC221, MC222 arranged in series with the transistors T212, T221, T222 is the transistor T211 and the resistance change element. Since it is the same as that of MC211, description is abbreviate | omitted. These transistors T211, T212, T221, and T222 may also serve as load elements that are electrically connected to the resistance change elements constituting the memory cell.

  With the above configuration, when a predetermined voltage (activation voltage) is supplied to the gates of the transistors T211, T212, T221, and T222 via the word lines W1 and W2, the transistors T211, T212, T221, and T222 Conduction is established between the drain and the source. Actually, the activation voltage is supplied only to the word line of the selected memory cell.

  The address buffer 202 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 204 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 206. . Here, the address signal ADDRESS is a signal indicating the address of the selected variable resistance element among the variable resistance elements MC211, MC212, MC221, and MC222. The row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS, and the column address signal COLUMN is a signal similarly indicating a column address.

  The control unit 203 selects one of a writing mode (corresponding to the writing process and the rewriting process) and a reading mode (corresponding to the reading process) according to the mode selection signal MODE received from the external circuit. Select a mode and execute.

  In the write mode, the control unit 203 outputs a control signal CONT instructing “write voltage pulse application” or “write current pulse application” to the bit line / plate line driver 207 in accordance with the input data Din received from the external circuit. To do.

In the read mode, the control unit 203 outputs a control signal CONT instructing “read voltage pulse application” or “read current pulse application” to the bit line / plate line driver 207. In this read mode, the control unit 203 further receives a read signal I _READ (when a read voltage pulse is applied) or a read signal V _READ (when a read current pulse is applied) output from a sense amplifier (not shown). Output data Dout indicating a bit value corresponding to the write voltage pulse V _REC (m) or the write current pulse I _REC (m) specified based on the signal I _READ or V _READ is output to an external circuit. The read signal I _READ or V _READ is a signal indicating the current value of the current flowing through the plate lines P1 and P2 or the voltage generated at both ends of the memory cell in the read mode.

  The row decoder 204 receives the row address signal ROW output from the address buffer 202, and selects one of the two word lines W1 and W2 according to the row address signal ROW. The word line driver 205 applies an activation voltage to the word line selected by the row decoder 204 based on the output signal of the row decoder 204.

  The column decoder 206 receives the column address signal COLUMN output from the address buffer 202, selects one of the two bit lines B1 and B2 according to the column address signal COLUMN, and One of the plate lines P1, P2 is selected.

When the bit line / plate line driver 207 receives the control signal CONT instructing “write voltage pulse application” or “read current pulse application” from the control unit 203, the bit line / plate line driver 207 causes the column decoder 206 to execute the control based on the output signal of the column decoder 206. A write voltage pulse V _REC (m) or a write current pulse I _REC (m) is applied to the selected bit line, and the selected plate line is also grounded.

When the bit line / plate line driver 207 receives a control signal CONT instructing “read voltage pulse application” or “read current pulse application” from the control unit 203, the bit line / plate line driver 207, based on the output signal of the column decoder 206, A read voltage pulse V _READ (n), a read current pulse I _READ (n), or a confirmation voltage pulse V _CHECK is applied to the bit line selected by 206, and the selected plate line is also grounded. . Thereafter, the sense amplifier outputs the signal I _READ indicating the current value of the current flowing through the plate line or the voltage V _READ generated at both ends of the memory cell to the control unit 203.

The power supply unit of the bit line / plate line driver 207 includes, for example, a ladder resistor circuit when it is desired to generate a plurality of different voltage pulses. By using this ladder resistor circuit, write voltages having m different voltage values are provided. The pulse V _REC (m) and the read voltage pulse V _READ (n) having n different voltage values can be output.

  In addition, when it is desired to generate a plurality of different current pulses, for example, a plurality of driver circuits of different sizes are provided, and a plurality of different current pulses are generated by appropriately combining them, or the gate voltage of the transistors constituting the driver circuit This can be realized by providing a circuit for controlling the above.

  The address buffer 202, the row decoder 204, the word line driver 205, the column decoder 206, and the bit line / plate line driver 207 are examples of a selection circuit that selects at least one memory cell from the memory cell array 201. Operates under the control of

[Operation of non-volatile storage device]
The storage device 200 configured as described above applies the write voltage pulse V _REC (m), the read voltage pulse V _READ (n), or the confirmation voltage pulse V _CHECK to each memory cell according to the procedure described with reference to FIG. By applying to, the writing process, the reading process, and the rewriting process described in Embodiment 1 are executed. Hereinafter, a case where writing / reading is performed on the resistance change element MC211 will be described as an example with reference to the flowchart of FIG. 6 as appropriate.

[Write mode]
The control unit 203 receives input data Din from an external circuit. Here, the control unit 203 outputs a control signal CONT indicating “write voltage pulse application” to the bit line / plate line driver 207 in accordance with the value of the input data Din. Here, m types of control signals CONT indicating “write voltage pulse application” are prepared, and one of the control signals CONT is output to the bit line / plate line driver 207 in accordance with the value of the input data Din. Become.

When the bit line / plate line driver 207 receives the control signal CONT indicating “write voltage pulse application” from the control unit 203, the bit line / plate line driver 207 applies the write voltage pulse V _REC (m) to the bit line B 1 selected by the column decoder 206. (S102). The bit line / plate line driver 207 brings the plate line P1 selected by the column decoder 206 to the ground state.

  At this time, an activation voltage is applied to the word line W1 selected by the row decoder 204 by the word line driver 205. For this reason, the drain and the source of the transistor T211 are in a conductive state.

As a result, the write voltage pulse V _REC (m) is applied to the resistance change element MC211. Thereby, the resistance value of the resistance change element MC211 changes from the high resistance state to the low resistance state. On the other hand, no write voltage pulse is applied to resistance change elements MC221 and MC222, and no activation voltage is applied to the gate of transistor T212 connected in series with resistance change element MC212. Therefore, resistance change elements MC212, MC221 and MC222 are not applied. The resistance state does not change.

When data representing “1” is written to the resistance change element MC 211, the write voltage pulse V _REC (1) is applied to the resistance change element MC 211 by the bit line / plate line driver 207. Here, the voltage value of the write voltage pulse V _REC (1) is set to −1.0 V, for example, and the pulse width is set to 100 ns. By such an operation, the write voltage pulse V _REC (1) is applied to the resistance change element MC211. Therefore, the resistance change element of the resistance change element MC211 enters a low resistance state corresponding to the data “1”.

Further, when data representing data “2” is written to the resistance change element MC 211, the write voltage pulse V _REC (2) is applied to the resistance change element MC 211 by the bit line / plate line driver 207 in the same manner. Here, the voltage value of the write voltage pulse V _REC (2) is set to −1.25 V, for example, and the pulse width is set to 100 ns. By such an operation, the write voltage pulse V _REC (2) is applied to the resistance change element MC211. Therefore, the resistance change element of the resistance change element MC211 enters a low resistance state corresponding to the data “2”.

Further, when data representing data “3” is written to the resistance change element MC211, for example, a write voltage pulse V _REC (3) of −1.5 V is written, and data representing data “4” is written to the resistance change element MC211. In this case, for example, a write voltage pulse V _REC (4) of −1.75 V is applied to each resistance change element MC211. Thereby, the resistance change element MC211 enters a low resistance state corresponding to the data “3” and the data “4”, respectively.

  Here, the resistance change element MC211 is expressed for convenience when it is in a low resistance state corresponding to data “1” to data “4”, but the resistance value of the resistance change element in the low resistance state is almost the same in any case. It is.

  When writing to the resistance change element MC211 is completed, a new address signal ADDRESS is input to the address buffer 202, and the operation in the storage mode of the storage device 200 is repeated for memory cells other than the resistance change element MC211.

As described above, multi-bit data can be written in one memory cell by applying the write voltage pulse V _REC (m) to the variable resistance element.

[Read mode]
The control unit 203 outputs a control signal CONT instructing “application of read voltage pulse” to the bit line / plate line driver 207. Here, n types of control signals CONT indicating “read voltage pulse application” are prepared, and these control signals CONT are sequentially output to the bit line / plate line driver 207.

When the bit line / plate line driver 207 receives the control signal CONT instructing “application of read voltage pulse” from the control unit 203, the bit line / plate line driver 207 applies a read voltage pulse corresponding to the control signal CONT to the bit line B1 selected by the column decoder 206. V _READ (n) is applied (S205). The bit line / plate line driver 207 brings the plate line P1 selected by the column decoder 206 to the ground state. Here, the voltage value of the read voltage pulse V _READ (n) is set to satisfy V ′ _REC (m) <V _READ (n) ≦ V ′ _REC (m + 1).

At this time, an activation voltage is applied to the word line W1 selected by the row decoder 204 by the word line driver 205. For this reason, the drain and the source of the transistor T211 are in a conductive state. Thereby, the read voltage pulse V _READ (n) is applied to the resistance change element MC211.

Note that the read voltage pulse V _READ (n) is not applied to the resistance change elements MC221 and MC222, and the activation voltage is not applied to the gate of the transistor T212 connected in series with the resistance change element MC212. The resistance states of MC212, MC221, and MC222 do not change.

Next, the bit line / plate line driver 207 measures the current value of the current flowing through the plate line P1 after applying the confirmation voltage pulse V _CHECK (S206), and controls the signal I _READ indicating the measured value. The data is output to the unit 203. Then, based on the comparison result between the current value indicated by the signal I _READ and a predetermined specified value, control unit 203 has the resistance change element of resistance change element MC211 in a high resistance state or a low resistance state. Is determined (S208). If it is determined that the variable resistance element is in a high resistance state, it is determined that n = m, and m of the write voltage pulse V _REC (m) is specified (S210). In the case of this example, if the specified m is 1, it can be seen that the data written in the resistance change element MC211 is “1”. Further, if the specified m is 2 to 4, it can be seen that the data written in the resistance change element MC211 is “2” to “4”, respectively. The control unit 203 outputs output data Dout corresponding to the value of m to the outside.

  When reading from the resistance change element MC211 is completed, a new address signal ADDRESS is input to the address buffer 202, and the operation in the read mode of the storage device 200 is repeated for resistance change elements other than the resistance change element MC211. .

  As described above, in the memory device 100 according to the present embodiment, in the writing process, one resistance voltage change is applied to the resistance change element by applying one of the writing voltage pulses of a plurality of different voltages having the first polarity to the resistance change element. The element is changed from the first resistance state to the second resistance state. On the other hand, in the reading process, read voltage pulses of a plurality of different voltages having a second polarity different from the first polarity are sequentially applied from the smaller voltage. Depending on whether the magnitude of the read voltage pulse that first changed the resistance change element in the direction from the second resistance state to the first resistance state was a plurality of different magnitudes, It is determined which of the write voltage pulses of different magnitudes has been used for the write process.

  By operating as described above, the storage device 200 can realize a stable multi-value storage operation.

(Other embodiments)
In each of the above embodiments, the variable resistance layer has a laminated structure of tantalum oxide, but the present invention is not limited to this. For example, a stacked structure of hafnium (Hf) oxide or a stacked structure of zircon (Zr) oxide may be used.

In the case of adopting a hafnium oxide laminated structure, when the composition of the first hafnium oxide is HfO _x and the composition of the second hafnium oxide is HfO _y , x is about 0.9 or more and 1.6 or less. Thus, y is preferably about 1.89 or more and 1.97 or less.

Further, when a zircon oxide laminated structure is employed, if the composition of the first zircon oxide is ZrO _x and the composition of the second zircon oxide is ZrO _y , x is about 0.9 or more and 1.4 or less. In addition, it is preferable that y is about 1.8 or more and 2 or less.

  Further, the resistance change layer may not be formed of a laminated structure of oxygen-deficient transition metal oxides, and may be formed of a single-layer oxygen-deficient transition metal oxide. Here, a resistance-voltage characteristic and a current-voltage characteristic when the variable resistance layer is formed of a single-layer oxygen-deficient tantalum oxide will be described.

15A to 15F show resistance change elements according to other embodiments of the present invention (oxygen-deficient tantalum oxide having a single resistance change layer (when the composition is TaO _x , x = 1. 57) is a diagram showing resistance-voltage characteristics of the variable resistance element configured as shown in FIG. 57, and FIGS. 15A to 15F show the write voltage pulse V _REC (m, m = 1, 2,..., Respectively. 6) show the resistance-voltage characteristics in the case of -1.00V, -1.25V, -1.50V, -1.75V, -2.00V and -2.25V, respectively. FIGS. 16A to 16F are diagrams showing current-voltage characteristics of the variable resistance element, and FIGS. 16A to 16F show the write voltage pulse V _REC (m, m = m = m). 1, 2,..., 6) are current-voltage characteristics at −1.00 V, −1.25 V, −1.50 V, −1.75 V, −2.00 V, and −2.25 V, respectively. Each is shown. 15A to 15F and FIGS. 16A to 16F are compared with FIGS. 2A to 2F and FIGS. 3A to 3F. Even when the change layer is formed of a single layer of oxygen-deficient tantalum oxide, the write voltage pulse V _REC (m, m = 1, 2, ..., 6) has a characteristic of changing from a low resistance state to a high resistance state when a voltage pulse having a larger voltage value and a reverse polarity is applied between the lower electrode and the upper electrode. Yes. Therefore, even if the variable resistance layer in each of the above embodiments is formed of a single-layer oxygen-deficient transition metal oxide, stable multilevel storage can be realized in the same manner.

  As described above, the variable resistance element driving method and the nonvolatile memory device according to the present invention have been described based on the first to sixth embodiments and other embodiments, but the present invention is limited to these embodiments. It is not something. Forms obtained by subjecting each embodiment to various modifications conceived by those skilled in the art without departing from the gist of the present invention, and forms obtained by arbitrarily combining components of each embodiment are also included in the present invention. included. In other words, a new embodiment can be realized by appropriately combining the above-described embodiments.

  The variable resistance element driving method and the nonvolatile memory device of the present invention are useful as a variable resistance element driving method and a storage device used in various electronic devices such as a personal computer or a portable phone, respectively.

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Lower electrode 3 Resistance change layer 3a 1st tantalum oxide layer 3b 2nd tantalum oxide layer 4 Upper electrode 5 Power supply 10 Resistance change element 100 Memory | storage device 101 Memory cell array 102 Address buffer 103 Control part 104 Row decoder 105 Word line Driver 106 Column decoder 107 Bit line driver 200 Non-volatile memory device 201 Memory cell array 202 Address buffer 203 Control unit 204 Row decoder 205 Word line driver 206 Column decoder 207 Bit line / plate line driver W1, W2, W3 Word lines B1, B2, B3 bit line D11, D12, D13, D21, D22, D23, D31, D32, D33 Bidirectional diode MC11, MC12, MC13, MC21, MC22, MC23, MC31, MC3 , MC33 memory cells MC211, MC212, MC221, MC222 variable resistance element T211, T212, T221, T222 select transistor

Claims (16)

A resistance change element driving method for driving a resistance change element whose resistance value reversibly changes according to electric pulses of different polarities as a multi-value storage element,
The resistance change element is changed from the first resistance state to the second resistance state by applying to the resistance change element one write electrical pulse of a plurality of different magnitudes of the write electrical pulses having the first polarity. Writing process
A read step of sequentially applying a plurality of read electrical pulses having different second polarities different from the first polarity to the variable resistance element in order from a smaller magnitude,
In the reading step, when the read electrical pulse is sequentially applied, the magnitude of the read electrical pulse that first changed the resistance change element from the second resistance state to the first resistance state is as follows. A resistance change element driving method for determining which one of the plurality of different write electric pulses is used for the writing step depending on which of the plurality of different magnitudes is provided. . In the writing step, by applying one write electric pulse of the plurality of different voltage write electric pulses having the first polarity to the resistance change element, the resistance change element is changed from the first resistance state to the second resistance state. Transition to the resistance state of
In the reading step, when the plurality of different voltage reading electrical pulses having the second polarity are sequentially applied to the resistance change element from the one having the smallest absolute value of the voltage, the resistance change element is set to the second resistance state. Depending on which of the plurality of different voltages is the voltage of the read electric pulse first changed in the direction of the first resistance state from which of the plurality of write electric pulses of the plurality of different voltages The method of driving a resistance change element according to claim 1, wherein it is determined whether the writing process has been performed by a pulse. In the writing step, the resistance change element is moved from the first resistance state by applying a write electric pulse of one current among a plurality of different write electric pulses of the first polarity to the resistance change element. Transition to the second resistance state,
In the reading step, when the plurality of different electrical current reading pulses having the second polarity are sequentially applied to the resistance change element from the smaller current magnitude, the resistance change element is set to the second resistance state. Depending on which of the plurality of different currents the current of the read electrical pulse first changed in the direction of the first resistance state from which of the plurality of write electrical pulses of the plurality of different currents The method of driving a resistance change element according to claim 1, wherein it is determined whether the writing process has been performed by a pulse. In the writing step, the variable resistance element is changed from a high resistance state to a low resistance state,
In the readout step, when the readout electrical pulse is sequentially applied, the magnitude of the readout electrical pulse that first changed the resistance change element from the low resistance state to the high resistance state is the plurality of different magnitudes. 4. The method according to claim 1, wherein a write electrical pulse among the plurality of different write electrical pulses is used to determine whether the write process has been performed according to which one of the plurality of write electrical pulses is different. Driving method of the variable resistance element. 5. The method according to claim 1, further comprising a rewriting step of applying, to the resistance change element, a write electric pulse having the same magnitude as the write electric pulse applied to the resistance change element in the writing step after the reading step. The resistance change element driving method according to Item. In the reading step, a resistance state as a prescribed value of the resistance change element is detected by giving a confirmation electric pulse to the resistance change element, and the resistance state and the prescribed value after the reading electric pulse is given. The resistance state of the first change state is detected by comparing the resistance change element with the first resistance state in the direction from the second resistance state to the first resistance state. A driving method of the resistance change element described. In the reading step, when the read electrical pulse is sequentially applied, the resistance value of the variable resistance element has changed from a resistance value obtained immediately before the read electrical pulse is applied by a larger amount than a predetermined change amount. The variable resistance element according to any one of claims 1 to 5, wherein the variable resistance element detects that the variable resistance element has first changed from the second resistance state to the first resistance state. Driving method. A resistance that intervenes between the first electrode, the second electrode, and the first electrode and the second electrode, and whose resistance value reversibly changes according to electric pulses of different polarities applied between the two electrodes. A memory cell array including a plurality of memory cells each including a variable resistance element having a change layer;
A selection circuit for selecting at least one memory cell from the memory cell array;
A control unit that controls the selection circuit to select at least one memory cell from the memory cells, and executes a writing process or a reading process for the selected memory cell;
The controller is
In the write step, by applying one write electric pulse of a plurality of different write electric pulses having a first polarity between both electrodes of the resistance change element included in the selected memory cell, Changing the resistance state of the variable resistance layer from the first resistance state to the second resistance state;
In the readout step, a plurality of readout electrical pulses having different second polarities different from the first polarity are sequentially applied between the two electrodes from the smallest size, and the readout electrical pulses are sequentially applied between the two electrodes. The magnitude of the read electrical pulse that first changed the resistance change layer from the second resistance state to the first resistance state was one of the plurality of different magnitudes. In accordance with the non-volatile memory device, it is determined which of the plurality of write electric pulses having different magnitudes the write electric pulse has performed the write process. The controller is
In the writing step, the resistance change layer is changed from a high resistance state to a low resistance state,
In the readout step, when the readout electrical pulse is sequentially applied between both electrodes, the magnitude of the readout electrical pulse that first changed the resistance change layer from the low resistance state to the high resistance state is the plurality of The non-volatile device according to claim 8, wherein a write electric pulse of the plurality of different write electric pulses is used to determine whether the write process is performed according to which of the different electric sizes is different. Storage device. The control unit, after the reading step, gives a writing electric pulse between the electrodes having the same magnitude as the writing electric pulse given between the electrodes in the writing step, thereby changing the resistance state of the resistance change layer. The non-volatile memory device according to claim 8, further executing a rewriting process to be changed. The nonvolatile memory device according to claim 8, wherein the variable resistance layer includes an oxygen-deficient transition metal oxide. The transition metal oxide includes a first region containing a first oxygen-deficient transition metal oxide having a composition represented by MO _x , and a composition represented by MO _y (where x <y). The nonvolatile memory device according to claim 11, further comprising: a second region containing a second oxygen-deficient transition metal oxide. The first region includes a tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9),
The nonvolatile memory device according to claim 12, wherein the second region includes a tantalum oxide having a composition represented by TaO _y (where 2.1 ≦ y ≦ 2.5). 14. The nonvolatile memory device according to claim 9, wherein each of the plurality of memory cells further includes a load element electrically connected to the resistance change layer. The nonvolatile memory device according to claim 14, wherein the load element is a diode. The nonvolatile memory device according to claim 14, wherein the load element is a transistor.

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