JP2012169000A - Driving method of resistance change element, nonvolatile storage device, resistance change element and multiple value storage method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving method of a resistance change element capable of stably reading and writing storage states of multiple values.SOLUTION: A driving method of a resistance change element 10 reversibly changes an interelectrode resistance value that is a resistance value between a first electrode 2 and a second electrode 4 by applying an interelectrode voltage that is a potential of the second electrode 4 based on the first electrode 2 to the resistance change element 10. With reference to Vα, Vβ, Vγ, RL, RM and RH that satisfy the following expressions: Vα<Vβ<0; Vγ>0; and RL<RM<RH, the driving method thereof comprises: a writing process for causing the interelectrode resistance value to be RL by means of an application of an interelectrode voltage Vα thereto; a first erasing process for causing the interelectrode resistance value to be RM by means of an application of an interelectrode voltage Vγ thereto after the writing process is performed; and a second erasing process for causing the interelectrode resistance value to be RH by means of an application of an interelectrode voltage Vβ thereto after the first erasing process is performed.

Description

  The present invention relates to a resistance change element driving method in which a resistance value changes in accordance with an applied electric pulse, a nonvolatile memory device that implements the method, and the like.

  In recent years, with the advancement of digital technology in electronic devices, in order to store data such as images, the capacity of nonvolatile resistance change elements (hereinafter simply referred to as “resistance change elements”) is increased, the writing power is reduced, It is said that there is a limit to the miniaturization of the flash memory using the existing floating gate in response to such demands for increasing the writing / reading time and extending the lifetime.

As a first prior art that can possibly meet the above requirements, perovskite materials (for example, Pr _(1-x) Ca _x MnO ₃ [PCMO], LaSrMnO ₃ [LSMO], GdBaCo _x O _y [GBCO] Etc.) have been proposed (see Patent Document 1). This technique is designed to store data by applying a voltage pulse (wave voltage with short duration) of different polarity to a perovskite material to increase or decrease its resistance value, and to correspond the data to a changing resistance value. Is. Furthermore, Patent Documents 2 and 3 describe a technique that uses not only an element capable of storing binary values (two states of low resistance and high resistance) but also an element capable of storing multiple values of three or more values. ing.

In addition, as a second conventional technique that makes it possible to switch the resistance value using voltage pulses of the same polarity, transition metal oxides (NiO, V ₂ O, ZnO, Nb ₂ O 5, TiO ₂ , WO ₃ , or There is also a resistance change element that utilizes a change in resistance value of the transition metal oxide film by applying a voltage pulse having a different pulse width to the CoO film (see Patent Document 4). In the variable resistance element using the transition metal oxide film, a configuration in which cross-point type memory cell arrays using diodes are stacked is also realized.

US Pat. No. 6,204,139 US Pat. No. 6,473,332 JP 2004-185756 A JP 2004-363604 A

  A problem in the element capable of storing the multi-value of the first prior art will be described.

  FIG. 11 is a diagram illustrating an example of a resistance change caused by an electrical pulse of an element using PCMO disclosed in Patent Document 2. In FIG. From the figure, it is possible to increase or decrease the resistance value by applying a predetermined number of electrical pulses having a predetermined polarity, voltage, and pulse width to an element with an initial resistance value of about 500Ω. It turns out that it is. The resistance value can take a substantially continuous value. Therefore, it is said that a multi-value storage element can be realized by selectively using three or more states having different resistance values and corresponding three or more different values to the respective resistance values. .

  FIG. 10 is a diagram illustrating a relationship between a voltage to be applied and a resistance value of a resistance change element using PCMO or the like disclosed in Patent Document 3. In FIG. 10, the applied electrical pulse is once. Also in this figure, it can be seen that the resistance value of the element changes almost continuously according to the voltage value of the applied electric pulse. In this case as well, as in the case of Patent Document 2, a multi-value storage element can be realized.

  In a multi-value storage element using three or more resistance states, the resistance state of the element is determined by reading the resistance value of the element. Therefore, in order to prevent malfunction, it is necessary that the resistance values in the respective resistance states have a certain difference from each other. However, in the elements disclosed in Patent Documents 2 and 3, the resistance value continuously changes depending on the voltage, pulse width, and number of applied electrical pulses. For this reason, even if the same electric pulse is applied, the resistance value to be realized varies due to the non-uniformity of the element itself, the voltage, the pulse width, the number of times of the electric pulse, etc., and is not stable. In addition, the resistance value of the memory element is not necessarily sufficiently stable. For this reason, when the difference between the resistance values in the respective resistance states is small, the set resistance value may change to such an extent that it is regarded as another state due to a change in the temperature of the state. As described above, the conventional memory element has a problem that it is difficult to stably operate as a variable resistance element that stores multi-value information.

Furthermore, since an oxide crystal having a perovskite structure such as Pr _0.7 Ca _0.3 MnO ₃ usually requires a high temperature of 650 ° C. to 850 ° C. for its crystallization, when introduced into a semiconductor manufacturing process, There is also a problem that other materials deteriorate.

Also, a transition having a relatively simple structure, which is made of a transition metal such as NiO, V ₂ O, ZnO, Nb ₂ O ₅ , TiO ₂ , WO ₃ , or CoO and oxygen, disclosed in the second prior art. In a resistance variable element using a metal oxide film, no mention is made of a multi-value memory element.

  The present invention has been made in view of such circumstances, and its main object is to provide a resistance change element driving method capable of stably reading and writing a multi-value storage state, and a nonvolatile storage device for implementing the method. It is to provide.

  Furthermore, another object of the present invention is to provide a method of driving a resistance change element that can be manufactured at a low temperature and that can stably read and write a multi-value storage state, and a nonvolatile storage device that implements the method. To do.

  In order to solve the above-described problem, a resistance change element driving method according to an aspect of the present invention is provided between a first electrode, a second electrode, and the first electrode and the second electrode. By applying an interelectrode voltage that is a potential of the second electrode with respect to the first electrode to a resistance change element including a resistance change layer made of an oxygen-deficient transition metal oxide A resistance change element driving method for reversibly changing an interelectrode resistance value which is a resistance value between the first electrode and the second electrode, the interelectrode voltages Vα and Vβ having a first polarity. And, for the RL, RM, and RH that satisfy the inter-electrode voltage Vγ having a second polarity different from the first polarity and RL <RM <RH, the inter-electrode voltages Vα and Vβ are | Vα |> | Vβ | is satisfied, and the interelectrode voltage Vα is applied to the variable resistance element. The writing process of setting the interelectrode resistance value to the RL, and applying the interelectrode voltage Vγ to the variable resistance element having the interelectrode resistance value of the RL, whereby the interelectrode resistance of the resistance change element A first erasing process for setting the value to the RM; and a second erasing process for setting the inter-electrode resistance value to the RH by applying the inter-electrode voltage Vβ to the resistance change element having the inter-electrode resistance value of the RM. Erasing process.

  As a result, the interelectrode resistance value takes at least three values of RL, RM, and RH according to the applied interelectrode voltage, and the interelectrode resistance value changes almost even when the applied pulse voltage value changes. Resistance value that can be read and written stably in multiple values because the resistance value in the stable region that does not work or the resistance state that makes it easy to determine the resistance state even if the resistance value changes can be used as the memory state An element driving method is realized.

  Here, after the second erasing process is performed, the first erasing process and the second erasing process are further performed one or more times, so that the interelectrode resistance value is set to the RH. A third erasing process may be included. At this time, in the third erasing process, it is determined whether the interelectrode resistance value after the second erasing process is larger than a predetermined threshold value, and the interelectrode resistance value is larger than the threshold value. If not, it is preferable that the first erasing process and the second erasing process are executed at least once.

  As a result, the resistance change element in the low resistance state or the medium resistance state is more reliably changed to the high resistance state, so that the resistance change element driving method capable of performing multi-valued reading and writing more stably is realized. The

In addition, the variable resistance layer includes a first variable resistance layer made of a first oxygen-deficient transition metal oxide connected to the first electrode, and an oxygen concentration higher than that of the first transition metal oxide. Preferably, the degree of deficiency is small, and a second variable resistance layer composed of a second transition metal oxide connected to the second electrode is laminated. At this time, the second resistance change layer has a resistance value higher than that of the first resistance change layer, or the standard electrode potential of the second transition metal constituting the second transition metal oxide is It is preferable that the potential is lower than the standard electrode potential of the first transition metal constituting the first transition metal oxide. For example, the first transition metal oxide is composed of tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9), and the second transition metal oxide is , TaO _y (where 2.1 ≦ y), and may be composed of a tantalum oxide having a composition.

  Thus, a resistance change element driving method that can be manufactured at a low temperature and that can stably read and write multiple values is realized.

  In addition, the nonvolatile memory device according to one embodiment of the present invention includes a first electrode, a second electrode, and an oxygen-deficient transition disposed between the first electrode and the second electrode. A memory cell including a resistance change element including a resistance change layer made of a metal oxide; and a pulse voltage application unit that applies a pulse voltage to the memory cell, wherein the pulse voltage application unit includes the first electrode. The interelectrode resistance value, which is the resistance value between the first electrode and the second electrode, is reversibly changed by applying to the memory cell an interelectrode voltage that is the potential of the second electrode with reference to The first polarity interelectrode voltages Vα and Vβ, the second polarity interelectrode voltage Vγ different from the first polarity, and RL, RM, RH satisfying RL <RM <RH. Voltage Vα and Vβ satisfy | Vα |> | Vβ | By applying the interelectrode voltage Vα to the memory cell, the writing process of setting the interelectrode resistance value to the RL, and applying the interelectrode voltage Vγ to the resistance change element having the interelectrode resistance value of the RL A first erasing process in which the interelectrode resistance value is set to the RM, and applying the interelectrode voltage Vβ to the memory cell with the resistance change element having the interelectrode resistance value of the RM, A second erasing process is performed to set the inter-electrode resistance value to the RH.

  Accordingly, the interelectrode resistance value takes at least three values of RL, RM, and RH according to the value of the pulse voltage applied by the pulse voltage application unit, and the electrode even if the voltage value of the applied pulse voltage changes. It is possible to use the resistance value in a stable region where the resistance value hardly changes, or the resistance state that makes it easy to determine the resistance state even if the resistance value changes as the memory state, so stable reading and writing of multiple values A nonvolatile memory device that implements a variable resistance element driving method that can be performed is realized.

  Here, the pulse voltage application unit further performs the first erasing process and the second erasing process at least once after performing the second erasing process, whereby the interelectrode resistance value is obtained. A third erasing process may be performed to set RH to RH. At this time, in the third erasing process, the pulse voltage application unit determines whether the interelectrode resistance value after the second erasing process is larger than a predetermined threshold value, When the resistance value is not larger than the threshold value, it is preferable to execute the first erasing process and the second erasing process at least once.

  As a result, the resistance change element in the low resistance state or the intermediate resistance state is more reliably changed to the high resistance state by the pulse voltage application unit, so that the resistance change element that can perform multi-level reading and writing more stably. A nonvolatile memory device that implements the driving method is realized.

In addition, the variable resistance layer includes a first variable resistance layer made of a first oxygen-deficient transition metal oxide connected to the first electrode, and an oxygen concentration higher than that of the first transition metal oxide. Preferably, the degree of deficiency is small, and a second variable resistance layer composed of a second transition metal oxide connected to the second electrode is laminated. At this time, the second resistance change layer has a resistance value higher than that of the first resistance change layer, or the standard electrode potential of the second transition metal constituting the second transition metal oxide is It is preferable that the potential is lower than the standard electrode potential of the first transition metal constituting the first transition metal oxide. For example, the first transition metal oxide is composed of tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9), and the second transition metal oxide is , TaO _y (where 2.1 ≦ y), and may be composed of a tantalum oxide having a composition.

  This realizes a nonvolatile memory device that implements a variable resistance element driving method that can be manufactured at a low temperature and that can stably read and write multiple values.

  The memory cell may further include a current control element connected to the first electrode or the second electrode. At this time, the current control element may be a selection transistor, and the current control element may be a diode.

  The present invention includes a first electrode, a second electrode, and a resistance change layer made of an oxygen-deficient transition metal oxide disposed between the first electrode and the second electrode. And an interelectrode resistance value that is a resistance value between the first electrode and the second electrode is reversible by applying an interelectrode voltage that is a potential of the second electrode with respect to the first electrode. RL, RM, RH satisfying RL <RM <RH, and the interelectrode voltages Vα and Vβ having the first polarity, the interelectrode voltage Vγ having the second polarity different from the first polarity, and RL <RM <RH. The inter-electrode voltages Vα and Vβ satisfy | Vα |> | Vβ |, the inter-electrode resistance value changes to RL when the inter-electrode voltage Vα is applied, and the inter-electrode resistance value is When RL, the interelectrode resistance value is reduced by applying the interelectrode voltage Vγ. When the resistance value between the electrodes changes to RM and the resistance value between the electrodes is RM, the resistance value between the electrodes changes to the RH when the interelectrode voltage Vβ is applied. May be.

  The present invention also includes a first electrode, a second electrode, and a resistance change layer made of an oxygen-deficient transition metal oxide disposed between the first electrode and the second electrode. A resistance value between the first electrode and the second electrode by applying an interelectrode voltage that is a potential of the second electrode with respect to the first electrode to the variable resistance element provided A multi-value storage method for a resistance change element that reversibly changes an inter-electrode resistance value between multi-values, wherein inter-electrode voltages Vα, Vβ1, and Vβ2 having a first polarity are different from the first polarity. For the RL, RM, RH1, and RH2 satisfying the second polarity interelectrode voltage Vγ and RL <RM <RH1 <RH2, the interelectrode voltages Vα, Vβ1, and Vβ2 are | Vα |> | Vβ2 |> | Vβ1. |, And the interelectrode voltage Vα is applied to the variable resistance element. The writing process for setting the inter-electrode resistance value to the RL, and applying the inter-electrode voltage Vγ to the variable resistance element having the inter-electrode resistance value of the RL. A first erasing process of setting the resistance value to the RM, and applying the interelectrode voltage Vβ1 to the resistance change element having the interelectrode resistance value of the RM, thereby setting the interelectrode resistance value to the RH1. 2 in 1 erasing process, and applying the inter-electrode voltage Vβ2 to the resistance change element having the inter-electrode resistance value of the RM or the RH1, the second inter-electrode resistance value is set to the RH2. It may be realized as a multi-value storage method having an erasing process.

  At this time, after the second 1 erasing process or the second 2 erasing process is further performed, the first erasing process, the second 1 erasing process, or the second 2 erasing process is performed. A third erasing process for setting the inter-electrode resistance value to RH1 or RH2 by further performing the erasing process at least once may be included. Specifically, in the third erasing process, whether the inter-electrode resistance value after the second erasing process is greater than or equal to a predetermined first threshold and less than or equal to a second threshold. If the inter-electrode resistance value is smaller than the first threshold value or larger than the second threshold value, at least the first erase process and the second first erase process are performed. Or in the third erasing process, it is determined whether or not the inter-electrode resistance value after the second erasing process is greater than or equal to a predetermined third threshold value. It is preferable that the first erasing process and the second two erasing processes are executed at least once when the inter-resistance value is smaller than the third threshold value.

  According to the driving method of the resistance change element according to the present invention and the nonvolatile memory device or the like of the present invention that implements the driving method, multilevel reading and writing can be performed stably. Therefore, the demand for increasing the capacity of the resistance change element, reducing the write power, speeding up the writing / reading time, and extending the life is increasing. The practical value of the invention is extremely high.

The schematic diagram which showed an example of the structure of the variable resistance element which concerns on Embodiment 1 of this invention. The schematic diagram which shows an example of the resistance-voltage characteristic of the resistance change element which concerns on Embodiment 1 of this invention. In Embodiment 1 of this invention, the graph which shows the experimental data regarding the 2nd erasure | elimination process A flowchart showing a specific example of the third erasing process in the first embodiment of the present invention. The schematic diagram which shows the operation | movement of the resistance change between three resistance states in the resistance change element which concerns on Embodiment 1 of this invention. In the resistance change element of Example 1 of this invention, the graph which shows an example of a change of a resistance state when a pulse voltage is repeatedly applied Schematic diagram for qualitatively explaining the mechanism of resistance change in the variable resistance element of the present invention. The block diagram which shows an example of a structure of the non-volatile memory device which concerns on Embodiment 2 of this invention. The block diagram which shows an example of a structure of the non-volatile memory device which concerns on Embodiment 3 of this invention. The figure which shows the relationship between the voltage applied and the resistance value of the non-volatile memory element currently disclosed by patent document 3 using PCMO etc. The figure which shows an example of the resistance change by the electric pulse of the element currently disclosed by patent document 2 using the PCMO

  Hereinafter, preferred embodiments of a resistance change element, a driving method thereof, a nonvolatile memory device, and a multi-value memory method of the present invention will be described with reference to the drawings.

(Embodiment 1)
[Configuration of variable resistance element]
First, the configuration of the variable resistance element according to Embodiment 1 of the present invention will be described.

  FIG. 1 is a schematic diagram showing an example of the configuration of the variable resistance element 10 according to Embodiment 1 of the present invention. As shown in FIG. 1, the resistance change element 10 of the present embodiment includes a substrate 1, a first electrode 2 formed on the substrate 1, and a transition metal oxide formed on the first electrode 2. A layer 3 and a second electrode 4 formed on the transition metal oxide layer 3 are provided. The first electrode 2 and the second electrode 4 are electrically connected to the transition metal oxide layer 3.

  The substrate 1 is composed of, for example, a silicon substrate. Furthermore, the substrate 1 may be configured by a semiconductor circuit including transistors, wirings, and the like. The second electrode 4 includes, for example, one of Au (gold), Pt (platinum), Ir (iridium), Pd (palladium), Cu (copper), and Ag (silver) or a material thereof. You may comprise using an alloy. The first electrode 2 may be made of tantalum nitride (TaN) or the like.

The transition metal oxide layer 3 is interposed between the first electrode 2 and the second electrode 4, and its resistance value increases or decreases according to an electric pulse applied between both electrodes (that is, reversibly has a resistance value) The first transition metal oxide layer 3a connected to the first electrode 2 has a higher oxygen content than the first transition metal oxide layer 3a, and the second electrode 4 And a second transition metal oxide layer 3b connected to each other. The transition metal oxide layer 3 is an example of an oxygen-deficient first tantalum oxide layer 3a that is an example of the first transition metal oxide layer 3a and an example of the second transition metal oxide layer 3b. The second tantalum oxide layer 3b may be stacked. Here, the oxygen content is a ratio of the number of oxygen atoms contained to the total number of atoms constituting the transition metal oxide. For example, as for the oxygen content of Ta ₂ O ₅ , the ratio of the number of oxygen atoms to the total number of atoms (O / (Ta + O)) is 71.4 atm%. Therefore, the oxygen content of the oxygen-deficient tantalum oxide is larger than 0 and smaller than 71.4 atm%. Further, the oxygen-deficient tantalum oxide layer has a lower oxygen content than the stoichiometric composition (in this case, Ta ₂ O ₅ ) (that is, the oxygen content rate compared to the stoichiometric composition). Is a small tantalum oxide layer. The oxygen content of the second transition metal oxide layer is higher than the oxygen content of the first transition metal oxide layer, and the resistance value of the second transition metal oxide layer is the first transition metal oxide layer. Higher than the resistance value. If the oxygen deficiency is described instead of the oxygen content, the oxygen deficiency of the second transition metal oxide layer is smaller than the oxygen deficiency of the first transition metal oxide layer. Here, the oxygen deficiency refers to the proportion of oxygen that is deficient with respect to the amount of oxygen constituting the oxide of the stoichiometric composition in the transition metal. For example, when the transition metal is tantalum (Ta), the stoichiometric oxide composition is Ta ₂ O ₅ , and thus can be expressed as TaO _2.5 . The degree of oxygen deficiency of TaO _2.5 is 0%. For example, the oxygen deficiency of a tantalum oxide having a composition expressed by TaO _1.5 is oxygen deficiency = (2.5−1.5) /2.5=40%.

When the composition of the first transition metal oxide layer 3a is TaO _x (first tantalum oxide layer), x is 0.8 or more and 1.9 or less, and the second transition metal oxide layer When the composition of 3b is TaO _y (second tantalum oxide layer) and y is 2.1 or more, the resistance value of the transition metal oxide layer 3 can be stably changed at high speed. It was. Therefore, x and y are preferably within the above range.

  If the thickness of the transition metal oxide layer 3 is 1 μm or less, a change in the resistance value is recognized. However, when a large-scale memory device is configured, it is preferably 200 nm or less. This is because when the photolithography process and the etching process are used in the patterning process, it is easy to process, and the voltage value of the voltage pulse necessary for changing the resistance value of the transition metal oxide layer 3 can be lowered. is there. On the other hand, the thickness of the transition metal oxide layer 3 is preferably at least 5 nm or more from the viewpoint of more reliably avoiding breakdown (dielectric breakdown) during voltage pulse application.

  In addition, the thickness of the second transition metal oxide layer 3b is disadvantageous in that the initial resistance value becomes too high if it is too large, and if it is too small, there is a disadvantage that a stable resistance change cannot be obtained. 1 nm or more and about 8 nm or less are preferable.

  When operating the variable resistance element 10 configured as described above, the first electrode 2 and the second electrode 4 are electrically connected to different terminals of the power supply 5. The power source 5 functions as an electric pulse applying device for driving the variable resistance element 10, and an electric pulse (voltage) having a predetermined polarity, voltage, and time width between the first electrode 2 and the second electrode 4. Pulse) can be applied between the first electrode 2 and the second electrode 4.

  In the following, the polarity of the voltage of the voltage pulse applied between the electrodes is specified by the potential of the second electrode 4 with respect to the first electrode 2 (this potential is referred to as “interelectrode voltage”). And

  The second electrode 4 disposed so as to be in contact with the second transition metal oxide layer 3b is, for example, Au (gold), Pt (platinum), Ir (iridium), Pd (palladium), Cu (copper). And one or more of materials having a standard electrode potential higher than the standard electrode potential of the transition metal M constituting the first transition metal oxide layer and the second transition metal oxide layer, such as Ag (silver) Constructed using materials. The first electrode 2 is preferably made of a material having a standard electrode potential smaller than the standard electrode potential of the material constituting the second electrode 4 (for example, W, Ni, or TaN).

That is, when a tantalum oxide to the transition metal oxide, the standard electrode potential V ₁ of the first electrode _2, the standard electrode potential V ₂ of the second electrode _4, and a standard electrode potential V _Ta of tantalum, V _Ta <it is preferable to satisfy _{V 2} and _V 1 _{<V 2} the relationship.

Moreover, it is more preferable to satisfy the relationship of V ₁ ≦ V _Ta <V ₂ .

  With such a configuration, it is possible to stably cause a resistance change phenomenon in the second transition metal oxide layer 3b in contact with the second electrode 4.

  The variable resistance element 10 may have a structure whose top and bottom are opposite to the structure shown in FIG.

[Method of manufacturing variable resistance element]
Next, a method for manufacturing the variable resistance element 10 will be described.

First, the first electrode 2 having a thickness of 0.2 μm is formed on the substrate 1 by sputtering. Thereafter, a tantalum oxide is formed as a transition metal oxide layer 3 on the first electrode 2 by a so-called reactive sputtering method in which a Ta target is sputtered in argon (Ar) gas and oxygen (O ₂ ) gas. A (TaO _x ) layer is formed. Here, the oxygen content in the tantalum oxide layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas. The substrate temperature can be set to room temperature without any particular heating.

Next, the surface of the tantalum oxide layer formed as described above is modified by oxidizing it. Thereby, a region (second region: TaO _y , y> x) having a higher oxygen content than a region (first region: TaO _x ) of the tantalum oxide layer that is not oxidized on the surface of the tantalum oxide layer. Is formed. These first region (TaO _x ) and second region (TaO _y ) correspond to the first transition metal oxide layer 3a and the second transition metal oxide layer 3b, respectively. The transition metal oxide layer 3 is constituted by the first transition metal oxide layer 3a and the second transition metal oxide layer 3b thus formed. The second transition metal oxide layer 3b may be formed by sputtering in an argon (Ar) gas and an oxygen (O ₂ ) gas using a TaO _y target.

  Next, the variable resistance element 10 is obtained by forming the second electrode 4 having a thickness of 0.2 μm by sputtering on the transition metal oxide layer 3 formed as described above.

  As described above, the variable resistance element 10 in the present embodiment is manufactured by a sputtering method or the like, and can be manufactured at a low temperature.

In addition, the magnitude | size and shape of the 1st electrode 2, the 2nd electrode 4, and the transition metal oxide layer 3 can be adjusted with a mask and lithography. In the present embodiment, the size of the second electrode 4 and the transition metal oxide layer 3 is 0.5 μm × 0.5 μm (area 0.25 μm ² ), and the first electrode 2 and the transition metal oxide layer 3 are The size of the contacting portion is also 0.5 μm × 0.5 μm (area 0.25 μm ² ).

In the present embodiment, the composition of the first transition metal oxide layer 3a is the first tantalum oxide layer (TaO _x (x = 1.54)), and the second transition metal oxide layer 3b The composition is the second tantalum oxide layer (TaO _y (y = 2.47)). Furthermore, the thickness of the transition metal oxide layer 3 is 50 nm, the thickness of the first transition metal oxide layer 3a is 45 nm, and the thickness of the second transition metal oxide layer 3b is 5 nm.

  Note that in this embodiment, the oxygen content of the first tantalum oxide layer and the second tantalum oxide layer is described as x = 1.54 and y = 2.47. However, the variable resistance element according to the present invention is not limited to this, and the range of x is 0.8 ≦ x ≦ 1.9, and the range of y is 2.1 ≦ y. As with the resistance change characteristics, stable resistance change can be realized.

[Operation of variable resistance element]
Next, the operation of the variable resistance element 10 obtained by the manufacturing method described above will be described.

  FIG. 2 is a schematic diagram showing an example of the resistance-voltage characteristic of the resistance change element 10 according to the first embodiment of the present invention. The power supply 5 is used as a reference with respect to the first electrode 2 of the resistance change element 10. The resistance value between the electrodes, which is the resistance value between the first electrode 2 and the second electrode 4 when the voltage of the electric pulse applied to the two electrodes 4 (that is, the voltage between the electrodes) is continuously changed. It is a figure which shows a change. Hereinafter, the case where the inter-electrode resistance value is at a predetermined high value (for example, about 10 MΩ) is referred to as a high resistance state (resistance value: RH), and is also a predetermined medium value (for example, about 100 kΩ). Is referred to as a medium resistance state (resistance value: RM), and a case where the resistance value is a predetermined low value (for example, about 10 kΩ) is referred to as a low resistance state (resistance value: RL). That is, the relationship of RL <RM <RH is satisfied for the three resistance values RL, RM, and RH. As for the voltage, as shown in FIG. 2, the relationship of Vα <V1 <Vβ <0 (that is, | Vα |> | Vβ |) and 0 <V2 <Vγ is satisfied.

  In addition, when the element structure of FIG. 1 is turned upside down, the characteristics of FIG. 2 are the characteristics that are opposite to those of FIG.

  When the resistance change element 10 is in a high resistance state and the resistance value between the electrodes is RH, or when the resistance change element 10 is in the middle resistance state and the resistance value between the electrodes is RM, Further, by applying a write voltage pulse (voltage value: Vα), which is a voltage pulse lower than a predetermined first threshold voltage V1 (large absolute value), between the first electrode 2 and the second electrode 4, the resistance change element 10 changes to the low resistance state, and the resistance value between the electrodes decreases to RL. Hereinafter, this is referred to as a writing process.

  When the resistance change element 10 is in the low resistance state and the interelectrode resistance value is RL, the first erase voltage pulse that is positive and has a voltage pulse higher than the predetermined second threshold voltage V2 is used by using the power source 5. By applying (voltage value: Vγ) between the first electrode 2 and the second electrode 4, the resistance change element 10 changes to an intermediate resistance state, and the interelectrode resistance value increases to RM. Hereinafter, this is referred to as a first erasing process.

  When the resistance change element 10 is in an intermediate resistance state and the interelectrode resistance value is RM, the power supply 5 is used to generate a voltage pulse (having a small absolute value) that is negative and higher than a predetermined first threshold voltage V1. By applying a second erase voltage pulse (voltage value: Vβ) between the first electrode 2 and the second electrode 4, the resistance change element 10 changes to a high resistance state, and the interelectrode resistance value increases to RH. . Hereinafter, this is referred to as a second erasing process. In the second erasing process, the voltage value Vβ of the second erasing voltage pulse is changed in a range that is higher than the first threshold voltage V1 (small in absolute value) and lower than 0 V. The interelectrode resistance value can be set to any value between the resistance value RM and the maximum resistance value Rmax. When the variable resistance element 10 is used as an element indicating a ternary resistance state, the voltage value Vβ of the second erase voltage pulse is higher than the first threshold voltage V1 in the second erase process (the absolute value is By making the absolute value as large as possible (closer to the absolute value of the threshold voltage V1 as much as possible), the inter-electrode resistance value RH in the high resistance state of the resistance change element 10 becomes large, and the medium resistance The difference from the state can be ensured.

  The first threshold voltage V1 is a threshold value of an applied voltage that causes a writing process, and the second threshold voltage V2 is a lowest applied voltage that causes a first erasing process. The third threshold voltage V3 is the highest (absolute value is the lowest) applied voltage that causes the second erase process.

  FIG. 3 is a graph showing experimental data regarding the second erasing process. Here, the voltage value of the second erase voltage pulse applied to the resistance change element 10 ("inversion voltage (V)" on the horizontal axis) and the resistance change element 10 after the application of the second erase voltage pulse are applied. The relationship with the resistance value (“resistance (Ω)” on the vertical axis) is plotted. In FIG. 3, the black circle mark, x mark, and black triangle mark plots are data when a second erase voltage pulse having a pulse width of 50 ns, 100 ns, and 300 ns is applied, respectively.

As can be seen from FIG. 3, in the second erase process, the voltage value Vβ of the second erase voltage pulse is higher than the first threshold voltage V1 (−1.4 to −1.3) (the absolute value is small). ), By changing in a range lower than 0 V, the resistance value between the electrodes of the resistance change element 10 is an arbitrary value between the resistance value RM (about 10 ⁵ Ω) and the maximum resistance value Rmax (about 10 ⁷ Ω). Can be set to a value. Therefore, it is also possible to store binary or higher data between the first threshold voltage V1 and the third threshold voltage V3. For example, when Vβ1 and Vβ2 are set such that | V1 |> | Vβ2 |> | Vβ1 |> | V3 |, the resistance value corresponding to Vβ1 is RH1, and the resistance value corresponding to Vβ2 is RH2. > RH1, and four values (2 bits) can be stored together with RL and RM.

  In the second erasing process, the magnitude of the interelectrode resistance value RH in the high resistance state may vary. In order to improve this, when the resistance change element 10 is in the middle resistance state and the inter-electrode resistance value is RM, the resistance change is performed by repeatedly performing the first erase process and the second erase process. The element 10 can be more stably in a high resistance state. Hereinafter, this (that is, repeating the first erasing process and the second erasing process) is referred to as a third erasing process.

  Further, even when the resistance change element 10 is in the low resistance state and the inter-electrode resistance value is RL, the high resistance state can be more stably achieved by performing the third erasing process.

  FIG. 4 is a flowchart showing a specific example of the third erasing process. Here, a flowchart in the case where the third erasing process is performed after the above writing process is performed is shown.

  First, by executing the first erasing process (S1) for the variable resistance element 10 in the low resistance state RL, the variable resistance element 10 is transitioned to the medium resistance state RM, After changing the resistance change element 10 to the high resistance state RH by performing the erasing process (S2), the resistance value of the resistance change element 10 is read (S3). A resistance value of the variable resistance element 10 is set to a predetermined threshold value (a resistance value (threshold value) that is larger than the resistance value RM and smaller than the maximum resistance value Rmax, for example, the resistance value RM and the resistance value Rmax. It is determined whether or not the intermediate value is greater than the intermediate value (S4).

  As a result, when the resistance value of the resistance change element 10 is not larger than the threshold value (No in S4), the first erasing process (S1), the second erasing process (S2), and reading of the resistance value (S3). On the other hand, if the resistance value of the resistance change element 10 is larger than the threshold value (Yes in S4), the process ends. Note that the repetition process of the first erasing process (S1) to determination (S4) corresponds to the third erasing process.

  As described above, the variable resistance element 10 in the low resistance state is more reliably subjected to the third erasing process in which the first erasing process and the second erasing process are repeatedly performed. 10 can be transitioned to a high resistance state.

  In the flowchart, the resistance value is determined (S3, S4) after the first erasing process (S1) and the second erasing process (S2) are performed, but the third erasing process according to the present invention is as follows. However, the determination of the resistance value (S3, S4) is not necessarily required. Even if the first erasing process and the second erasing process are repeated a predetermined number of times without determining the resistance value, the transition to the high resistance state is more sure.

  In the above flowchart, the third erase process is performed on the variable resistance element 10 in the low resistance state RL. However, the third erase process is performed on the variable resistance element 10 in the medium resistance state RM. May be. The third erasing process is because the resistance change element 10 can be more reliably changed to the high resistance state RH with respect to the resistance change element 10 in either the low resistance state RL or the middle resistance state RM. is there. That is, after the first erasing process, a third erasing process for setting the interelectrode resistance value to RH by repeatedly performing the first erasing process and the second erasing process may be performed.

  Further, when setting a plurality of resistance values between the third threshold voltage V3 and the first threshold voltage V1, the second erasing process has a plurality of inter-electrode voltages respectively corresponding to the plurality of resistance values. For each resistance value, a threshold value that defines a lower limit and a threshold value that defines an upper limit (not necessarily required for the state with the highest resistance) are defined, and in the determination step S4 of FIG. The third erasing process may be repeated until the threshold value is between the defining threshold value and the defining threshold value.

  Next, in the resistance change element 10 according to the first embodiment of the present invention, the resistance state (low resistance state, medium resistance state, high resistance state) used as a multi-value memory is a conventional resistance change for a multi-value memory. It will be described that the device is more stable than the resistance state of the device.

  When the resistance change element 10 is in a low resistance state, even if a negative voltage pulse having the same polarity as the write voltage pulse is applied between the first electrode 2 and the second electrode 4, the resistance change element 10 is low. Almost no change in the resistance state. Similarly, when the variable resistance element 10 is in the middle resistance state, even if a positive voltage pulse having the same polarity as the first erase voltage pulse is applied between the first electrode 2 and the second electrode 4, The resistance change element 10 remains in a medium resistance state and hardly changes. Further, when the resistance change element 10 is in a high resistance state, a voltage pulse having the same polarity as that of the second erase voltage pulse and having a negative polarity and higher than the voltage value of the second erase voltage pulse (small absolute value) When applied between the first electrode 2 and the second electrode 4, the transition metal oxide layer 3 remains almost unchanged in a high resistance state. However, when the variable resistance element 10 is in a high resistance state, the negative polarity having the same polarity as the second erase voltage pulse and higher than the first threshold voltage V1 (smaller absolute value) than the second erase voltage. When a voltage pulse having a lower value (a larger absolute value) is applied between the first electrode 2 and the second electrode 4, the resistance change element 10 enters a second high resistance state in which the resistance value is higher than that in the high resistance state. Change. Also in this case, since the high resistance state of the resistance change element 10 changes to a higher second high resistance state, the difference from the middle resistance state becomes larger, and the determination of the resistance state becomes easier.

  As described above, the resistance change element for a multi-value memory using the conventional resistance change phenomenon changes the resistance value by raising and lowering the voltage applied to the element in a region where the resistance value continuously changes. . In this case, since a transient resistance change region is used, the reproducibility of the resistance value is poor, and it is difficult to stably operate as a memory. The resistance change element 10 proposed in the first embodiment has a resistance value in a stable region in which the resistance value hardly changes even when the voltage value of the applied pulse voltage changes, or a resistance state even if the resistance value changes. Since the resistance state that facilitates determination is used as the memory state, it can be applied as a resistance change element for a multi-level memory that operates stably.

  FIG. 5 is a schematic diagram (state transition diagram) illustrating the resistance change operation between the three resistance states of the resistance change element 10 according to the first embodiment of the present invention.

  First, an operation in which the variable resistance element 10 changes between a high resistance state (resistance value RH) and a low resistance state (resistance value RL) will be described. When the resistance change element 10 is in the high resistance state, the write voltage pulse Vα is applied to change to the low resistance state (S101A). Conversely, when the variable resistance element 10 is in the low resistance state, no single voltage pulse can be applied to directly change from the low resistance state to the high resistance state. When changing from the low resistance state to the high resistance state, the first erase voltage pulse Vγ is once applied from the low resistance state to change to the middle resistance state (S102A), and then the second erase voltage pulse Vβ is changed. Application is made to change to a high resistance state (S103A). In order to obtain a more stable high resistance state, the second erasing voltage pulse is repeatedly applied after applying the first erasing voltage pulse Vγ from the low resistance state (S102A) (that is, the first erasing voltage pulse is applied). By repeating the application of the first erase voltage pulse Vγ and the application of the second erase voltage pulse), the state is changed to the high resistance state (S103B).

  Next, an operation in which the resistance change element 10 changes between the low resistance state (resistance value RL) and the middle resistance state (resistance value RM) will be described. When the resistance change element 10 is in the low resistance state, the first erase voltage pulse Vγ is applied to change to the middle resistance state (S102A). Conversely, when the resistance change element 10 is in the middle resistance state, the write voltage pulse Vα is applied to change to the low resistance state (S102B).

  Next, an operation in which the resistance change element 10 changes between the middle resistance state (resistance value RM) and the high resistance state (resistance value RH) will be described. When the resistance change element 10 is in the middle resistance state, the second erase voltage pulse Vβ is applied to change to the high resistance state (S103A). In order to obtain a more stable high resistance state, the second erase voltage pulse is repeatedly applied after the application of the first erase voltage pulse Vγ from the intermediate resistance state (that is, the first erase voltage). By repeating the application of the pulse Vγ and the application of the second erase voltage pulse), the state is changed to the high resistance state (S103B). Conversely, when the variable resistance element 10 is in the high resistance state (resistance value RH), the first erase voltage pulse Vγ cannot be applied and stably changed to the middle resistance state (resistance value RM).

  As can be seen from the above, the variable resistance element 10 according to the present embodiment is deficient in oxygen disposed between the first electrode 2, the second electrode 4, and the first electrode 2 and the second electrode 4. A transition metal oxide layer 3, which is a resistance change layer composed of a transition metal oxide of a type, and is applied with an interelectrode voltage that is a potential of a second electrode 4 with respect to the first electrode 2 The interelectrode resistance value, which is the resistance value between the first electrode 2 and the second electrode 4, reversibly changes, and Vα, Vβ, Vγ satisfying Vα <Vβ <0 and Vγ> 0 and RL <RM <RH. , RL, RM, and RH, the interelectrode resistance value is changed to RL when the interelectrode voltage Vα is applied, and the interelectrode resistance is changed to RL when the interelectrode resistance value is RL. When the value changes to RM and the interelectrode resistance value is RM, the interelectrode voltage Vβ is The inter-electrode resistance value by being compressed has a characteristic that varies in RH.

  And the following multi-value memory | storage is implement | achieved by using the resistance change element 10 which has such a characteristic. That is, the multi-value storage method includes a first electrode, a second electrode, and a resistance change layer formed of an oxygen-deficient transition metal oxide disposed between the first electrode and the second electrode. An interelectrode resistance that is a resistance value between the first electrode and the second electrode by applying an interelectrode voltage that is a potential of the second electrode with respect to the first electrode to a resistance change element that includes the first electrode A multi-value storage method of a resistance change element that reversibly changes a value between multi-values, wherein interelectrode voltages Vα, Vβ1, and Vβ2 having a first polarity and a second polarity different from the first polarity Electrode voltage Vγ and RL, RM, RH1, and RH2 satisfying RL <RM <RH1 <RH2, the interelectrode voltages Vα, Vβ1, and Vβ2 satisfy | Vα |> | Vβ2 |> | Vβ1 | Under conditions, it has the following process.

(1) Writing process in which the interelectrode resistance value is set to RL by applying the interelectrode voltage Vα to the resistance change element.

(2) A first erasing process in which the resistance value between electrodes of the resistance change element is set to RM by applying an interelectrode voltage Vγ to the resistance change element having the resistance value between electrodes RL.

(3) A second first erasing process for setting the interelectrode resistance value to RH1 by applying the interelectrode voltage Vβ1 to the resistance change element having the interelectrode resistance value RM.

(4) A second second erasing process for setting the interelectrode resistance value to RH2 by applying the interelectrode voltage Vβ2 to the resistance change element having the interelectrode resistance value of RM or RH1.

  Here, the multi-value storage method preferably further includes the following steps.

(5) After performing the second 1 erasing process or the second 2 erasing process, the first erasing process and the second 1 erasing process or the second 2 erasing process are performed once more. By performing the above, the third erasing process for setting the interelectrode resistance value to RH1 or RH2

  More specifically, in the step (5), when the second first erasing process is repeated, in the third erasing process, the interelectrode resistance value after the second first erasing process is predetermined. It is determined whether or not the threshold value is equal to or greater than the first threshold value and equal to or smaller than the second threshold value, and the first erase process is performed when the interelectrode resistance value is smaller than the first threshold value or larger than the second threshold value. And the second one erasing process are executed at least once. On the other hand, when the second 2 erasing process is repeated, in the third erasing process, whether the inter-electrode resistance value after the second 2 erasing process is greater than or equal to a predetermined third threshold value. When the inter-electrode resistance value is smaller than the third threshold value, the first erase process and the second two erase processes are executed at least once. The first threshold and the second threshold are values that specify a normal range of RH1 (first threshold ≦ RH1 ≦ second threshold), and the third threshold is a normal range of RH2 (first 3 is a value specifying threshold value ≦ RH2).

  Accordingly, the interelectrode resistance value takes at least four values of RL, RM, RH1, and RH2 according to the applied interelectrode voltage, and a stable multilevel storage method is realized.

[Example 1]
FIG. 6 is a graph showing an example of a change in resistance state when a pulse voltage is repeatedly applied in the variable resistance element 10 of Example 1 of the present invention. In the first embodiment, an electrical pulse having a predetermined voltage value (pulse voltage) and a pulse width of 100 ns is applied between the first electrode and the second electrode. The inter-electrode resistance value between the second electrode was measured. As for the interelectrode resistance value, a voltage of +0.4 V, which is a voltage whose absolute value is sufficiently smaller than the second threshold voltage V2 and does not change the interelectrode resistance value of the resistance change element 10, is set between the first electrode and the second electrode. It was calculated by applying the current between them and measuring the flowing current. In the figure, the write voltage pulse Vα (voltage -2.4 V, pulse width 100 ns) and the first erase voltage pulse Vγ (voltage +1.8 V, pulse width 100 ns) are repeated for the number of times of pulse application from 1 to 71 times. The state of resistance change when applied is shown. This is a resistance change corresponding to the transition S102A and the transition S102B shown in FIG. From the data of the number of pulse applications from 1 to 71 in FIG. 6, the resistance change element 10 may change relatively stably between the low resistance state (resistance value RL) and the middle resistance state (resistance value RM). Recognize. When the number of pulse application is from 72 to 135, the write voltage pulse Vα (voltage −2.4 V, pulse width 100 ns) is applied to the resistance change element 10 to enter the low resistance state (resistance value RL). 1 erasing voltage pulse Vγ (voltage +1.8 V, pulse width 100 ns) is applied to achieve a middle resistance state (resistance value RM), and then the first erasing voltage pulse Vγ (voltage +1.8 V, pulse width 100 ns) The second erasing voltage pulse Vβ (voltage −1.0 V, pulse width 100 ns) is repeatedly applied (9 times), and the change to the high resistance state (resistance value RH) is repeatedly performed. These resistance changes are resistance changes corresponding to the transitions S101A, S102A, and S103B shown in FIG. From the data shown in FIG. 6, it can be seen that the variable resistance element 10 changes relatively stably between the three resistance states. As described above, the variable resistance element 10 according to the first embodiment can store ternary information using these three stable states.

[Mechanism of resistance change]
Here, a mechanism of resistance value change in the writing process, the first erasing process, the second erasing process, and the third erasing process of the variable resistance element 10 will be qualitatively described with reference to FIG. At this time, there are many unclear points about the details of the mechanism of resistance change, and there are a lot of speculated parts here.

  FIG. 7 is a schematic diagram for explaining the mechanism of resistance change. In FIG. 7, only the first transition metal oxide layer 3a and the second transition metal oxide layer 3b are shown, and the first electrode 2 and the second electrode 4 are omitted.

Since the oxygen content of the second transition metal oxide layer 3b is very large (in other words, the oxygen deficiency is very small) (in this embodiment, TaO _y (2.1 ≦ y)), the resistance change element The interelectrode resistance value of 10 is very high in the initial state (the state after manufacture and before the reversible resistance change operation), and the write voltage pulse, the first erase voltage pulse, and the second erase Even if the voltage pulse is applied, the resistance changing operation is not shown (FIG. 7A). Therefore, before the resistance change operation is performed, a positive voltage or negative polarity initial break voltage pulse having a voltage value larger than the write voltage pulse, the first erase voltage pulse, and the second erase voltage pulse is applied to the second electrode 4. As a result, an initial break is performed, and a conductive path 3c is formed in the second transition metal oxide layer 3b (FIG. 7B).

  First, the mechanism of forming the conductive path 3c by this initial break voltage pulse will be qualitatively described. By applying a break voltage pulse, oxygen ions in a minute portion of the second transition metal oxide layer 3b abruptly change at the interface of the second electrode 4 (interface between the second electrode 4 and the second transition metal oxide layer 3b). ) Moves from the vicinity to the first transition metal oxide layer 3a side and has an oxygen content smaller than that of the second transition metal oxide layer 3b (in other words, the second transition metal oxide layer 3b). The degree of oxygen deficiency is larger than the degree of oxygen deficiency of 3b), so that a small-sized conductive path 3c with low resistance is formed. This state is a low resistance state of the variable resistance element 10 and is a state in which an initial break has been performed (FIG. 7B).

  Next, the mechanism of resistance change between the low resistance state and the medium resistance state of the variable resistance element 10 will be qualitatively described. By applying a positive first erase voltage pulse Vγ to the variable resistance element 10 in a low resistance state, the inside of the conductive path 3c formed in the second transition metal oxide layer 3b has a negative polarity. Oxygen ions move in the direction toward the second electrode 4, accumulate in the vicinity of the second electrode 4, and the resistance change element 10 changes to a medium resistance state (FIG. 7C). On the other hand, by applying a negative write voltage pulse Vα to the resistance change element 10 in the intermediate resistance state, oxygen ions accumulated in the vicinity of the second electrode 4 pass through the second path through the conductive path 3c. 4 moves away from the interface 4 and the resistance change element 10 changes to a low resistance state (FIG. 7B).

  Next, a mechanism of resistance change between the middle resistance state and the high resistance state of the resistance change element 10 will be qualitatively described. When the second erase voltage Vβ having a negative polarity is applied to the resistance change element 10 in the middle resistance state, the second erase voltage Vβ is smaller than the absolute value of the first threshold voltage V1 because the second erase voltage Vβ is smaller than the second threshold voltage V1. Oxygen ions accumulated in the vicinity of the electrode 4 can hardly move in the direction away from the interface of the second electrode 4 in the conductive path 3c. However, oxygen ions other than the oxygen ions accumulated in the vicinity of the second electrode 4 are present in some part of the conductive path 3c (for example, the conductive path 3c and the first transition metal oxide). In the vicinity of the boundary with the layer 3a). In this way, the resistance change element 10 is considered to change from the middle resistance state to the high resistance state (FIG. 7D). In the state of the resistance change element 10 shown in FIG. 7D, when the positive first erasing voltage Vγ and the negative second erasing voltage Vβ are repeatedly applied, the vicinity of the second electrode 4 is obtained. The oxygen ion layer accumulated in the layer and the oxygen ion layer accumulated near the boundary between the conductive path 3c and the first transition metal oxide layer 3a have insufficient voltage applied to reduce the thickness thereof. It is estimated that a more stable high-resistance state is realized because the thickness increases (below the threshold value).

(Embodiment 2)
The second embodiment is a nonvolatile memory device including the variable resistance element 10 described in the first embodiment. The configuration and operation of this nonvolatile memory device will be described below.

[Configuration of non-volatile storage device]
FIG. 8 is a block diagram showing an example of the configuration of the nonvolatile memory device 200 according to Embodiment 2 of the present invention. As illustrated in FIG. 8, the nonvolatile memory device 200 includes a memory cell array 201 including a resistance change element, an address buffer 202, a control unit 203, a row decoder 204, a word line driver 205, a column decoder 206, And a bit line / plate line driver 207. The bit line / plate line driver 207 includes a sense circuit, and can measure a current flowing in the bit line or the plate line and a generated voltage.

  As shown in FIG. 8, the memory cell array 201 includes two word lines W1 and W2 extending in the vertical direction, two bit lines B1 and B2 extending in the horizontal direction across the word lines W1 and W2, Corresponding to each intersection of two plate lines P1, P2 extending in the lateral direction provided corresponding to the bit lines B1, B2 on a one-to-one basis, and word lines W1, W2 and bit lines B1, B2 in a matrix form Are provided with four memory cells MC211, MC212, MC221, and MC222. Note that the memory cells MC211, MC212, MC221, and MC222 include a selection transistor T211 and a resistance change element R211, a selection transistor T212 and a resistance change element R212, a selection transistor T221 and a resistance change element R221, and a selection transistor T222 and a resistance change element R222, respectively. Consists of

  Note that the number or number of these components is not limited to the above. Here, the memory cell array 201 includes four memory cells as described above. However, this is an example, and a configuration including five or more memory cells may be employed.

  In the above configuration example, the plate line is arranged in parallel with the bit line, but the plate line may be arranged in parallel with the word line. The plate line is configured to apply a common potential to the connected transistors. However, the plate line includes a source line selection circuit and a driver having the same configuration as the row decoder 204 and the word line driver 205, and the selected source line and The non-selected source line may be driven with a different voltage (including polarity).

  The variable resistance elements R211, R212, R221, and R222 described above correspond to the variable resistance element 10 described in the first embodiment. The configuration of the memory cell array 201 will be further described. The memory cell MC211 (selection transistor T211 and resistance change element R211) is provided between the bit line B1 and the plate line P1, and the source of the selection transistor T211 and the resistance change element R211 are arranged in series to be connected. More specifically, the selection transistor T211 is connected to the bit line B1 and the resistance change element R211 between the bit line B1 and the resistance change element R211. The resistance change element R211 includes the selection transistor T211 and the plate line P1. Are connected to the selection transistor T211 and the plate line P1. The gate of the selection transistor T211 is connected to the word line W1.

  The connection state of the other three selection transistors T212, T221, T222 and the three resistance change elements R212, R221, R222 arranged in series with the selection transistors T212, T221, T222 is the selection transistor T211 and Since it is the same as that of the resistance change element R211, description is abbreviate | omitted.

  With the above configuration, when a predetermined voltage (activation voltage) is supplied to the gates of the selection transistors T211, T212, T221, and T222 via the word lines W1 and W2, the selection transistors T211, T212, T221, The drain and source of T222 become conductive.

  The address buffer 202 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 204 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 206. . Here, the address signal ADDRESS is a signal indicating the address of the memory cell selected from among the memory cells MC211, MC212, MC221, and MC222. The row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS, and the column address signal COLUMN is a signal similarly indicating a column address.

  The control unit 203 selects one of the write mode, the first erase mode, the second erase mode, the third erase mode, and the read mode according to the mode selection signal MODE received from the external circuit. select. Hereinafter, in the case of voltage application, each voltage is applied with reference to the plate line.

  In the write mode, the control unit 203 outputs a control signal CONT instructing “application of write voltage” to the bit line / plate line driver 207 in accordance with the input data Din received from the external circuit.

  In the read mode, the control unit 203 outputs a control signal CONT instructing “application of read voltage” to the bit line / plate line driver 207. In this read mode, the control unit 203 further receives a signal IREAD output from the bit line / plate line driver 207, and outputs output data Dout indicating a bit value corresponding to the signal IREAD to an external circuit. This signal IREAD is a signal indicating the current value of the current flowing through the plate lines P1 and P2 in the read mode.

  In the first erase mode, the control unit 203 confirms the resistance states of the resistance change elements R211, R212, R221, and R222. If the resistance state is a low resistance state, A control signal CONT for instructing “application of erase voltage” is output to the bit line / plate line driver 207 in the case of a high resistance state, and a control signal CONT for instructing “application of write voltage” and “application of first erase voltage” is output. To do.

  Further, in the second erase mode, the control unit 203 checks the resistance states of the resistance change elements R211, R212, R221, and R222, and according to the resistance state, The bit line / plate line driver receives the control signal CONT for instructing “application of erase voltage” and “application of the second erase voltage”, and the control signal CONT instructing “application of second erase voltage” in the middle resistance state. It outputs to 207.

  In the third erase mode, the control unit 203 repeats the first erase mode and the second erase mode a predetermined number of times, or while performing the read mode and the determination (S4) in FIG. The first erase mode and the second erase mode are repeated.

  The row decoder 204 receives the row address signal ROW output from the address buffer 202, and selects one of the two word lines W1 and W2 according to the row address signal ROW. The word line driver 205 applies an activation voltage to the word line selected by the row decoder 204 based on the output signal of the row decoder 204.

  The column decoder 206 receives the column address signal COLUMN output from the address buffer 202, selects one of the two bit lines B1 and B2 according to the column address signal COLUMN, and selects the selected one. One of the two plate lines P1 and P2 corresponding to the bit line is selected.

  When the bit line / plate line driver 207 receives the control signal CONT instructing “application of write voltage” from the control unit 203, the bit line / plate line driver 207 is selected as the bit line selected by the column decoder 206 based on the output signal of the column decoder 206. A write voltage VWRITE (write voltage pulse) is applied between the plate lines.

  When the bit line / plate line driver 207 receives a control signal CONT instructing “reading voltage application” from the control unit 203, the bit line / plate line driver 207 determines the bit line selected by the column decoder 206 based on the output signal of the column decoder 206. Similarly, a read voltage VREAD is applied between the selected plate lines. Thereafter, the bit line / plate line driver 207 outputs a signal IREAD indicating the current value of the current flowing through the plate line to the control unit 203.

  Further, when the bit line / plate line driver 207 receives the control signal CONT instructing “application of the first erase voltage” from the control unit 203, the bit line / plate line driver 207 is selected by the column decoder 206 based on the output signal of the column decoder 206. A first erase voltage VRESET1 (first erase voltage pulse) is applied between the selected plate lines in the same manner as the bit lines.

  Further, when the bit line / plate line driver 207 receives the control signal CONT instructing “second erase voltage application” from the control unit 203, the bit line / plate line driver 207 is selected by the column decoder 206 based on the output signal of the column decoder 206. A second erase voltage VRESET2 (second erase voltage pulse) is applied between the selected plate lines in the same manner as the bit lines.

  Here, the voltage value of the write voltage VWRITE is set to −2.4 V, for example, and the pulse width is set to 100 ns. The voltage value of the read voltage VREAD is set to + 0.4V, for example. Further, the voltage value of the first erase voltage VRESET1 is set to +1.8 V, for example, and the pulse width is set to 100 ns. Further, the voltage value of the second erase voltage VRESET2 is set to −1.0 V, for example, and the pulse width is set to 100 ns.

  Functionally, the control unit 203 and the bit line / plate line driver 207 constitute a pulse voltage application unit that applies a predetermined pulse voltage to a selected memory cell (more precisely, a resistance change element). ing. With such a pulse voltage application unit, at least (1) a write voltage pulse (interelectrode voltage Vα) having a first polarity is applied to a memory cell, thereby changing the resistance state of the resistance change element of the memory cell. (2) By applying a first erase voltage pulse (interelectrode voltage Vγ) having a second polarity different from the first polarity to the memory cell, to change from the high resistance state to the low resistance state. A first erase process for changing the resistance state of the resistance change element of the memory cell from the low resistance state to the middle resistance state; and (3) a second erase voltage pulse having the same polarity as the first polarity (between the electrodes). Applying a voltage Vβ) to the memory cell, thereby changing the resistance state of the resistance change element of the memory cell from the medium resistance state to the high resistance state; and (4) after the writing process. Alternatively, after the first erasing process, the memory cell is repeatedly subjected to the first erasing process and the second erasing process, thereby changing the resistance state of the resistance change element of the memory cell to the low resistance state or And a third erasing process for changing from the middle resistance state to the high resistance state.

[Operation of non-volatile storage device]
Hereinafter, the operation example of the nonvolatile memory device 200 configured as described above is divided into the write mode, the first erase mode, the second erase mode, the third erase mode, and the read mode. explain. Here, the writing process in the first embodiment is the writing mode, the first erasing process is the first erasing mode, the second erasing process is the second erasing mode, and the third erasing process is the third erasing mode. It corresponds to each.

  In the following, as the input data Din received by the control unit 203 from the external circuit, “2” corresponds to the case where the variable resistance element is in the low resistance state, and “1” corresponds to the case where the resistance change element is in the middle resistance state. The case of “0” is associated with “0”.

  For convenience of explanation, it is assumed that the address signal ADDRESS is a signal indicating the address of the memory cell MC211.

[Write mode]
The control unit 203 receives input data Din from an external circuit. Here, when the input data Din is “2”, the control unit 203 outputs a control signal CONT indicating “application of write voltage” to the bit line / plate line driver 207. On the other hand, the control unit 203 does not output the control signal CONT when the input data Din is “1” or “0”.

  When the bit line / plate line driver 207 receives the control signal CONT indicating “write voltage application” from the control unit 203, the bit line / plate line driver 207 writes the write voltage VWRITE () between the bit line B1 selected by the column decoder 206 and the selected plate line P1. Write voltage pulse) is applied.

  At this time, an activation voltage is applied to the word line W1 selected by the row decoder 204 by the word line driver 205. For this reason, the drain and the source of the selection transistor T211 are in a conductive state.

  As a result, a write voltage VWRITE, that is, a write voltage pulse having a voltage value of −2.4 V and a pulse width of 100 ns is applied to the memory cell MC211. Thereby, the write process in the first embodiment is executed by the pulse voltage application unit, and the resistance value of the resistance change element R211 of the memory cell MC211 changes from the high resistance state or the middle resistance state to the low resistance state. On the other hand, the write voltage pulse is not applied to the memory cells MC221 and MC222, and the activation voltage is not applied to the gate of the selection transistor T212 of the memory cell MC212. Therefore, the resistances of the resistance change elements of the memory cells MC212, MC221, and MC222. The state does not change.

  In this way, only the resistance change element R211 can be changed to the low resistance state, whereby data indicating “2” corresponding to the low resistance state is written in the memory cell MC211.

  When writing to the memory cell MC211 is completed, a new address signal ADDRESS is input to the address buffer 202, and the operation in the write mode of the nonvolatile memory device 200 is repeated for the memory cells other than the memory cell MC211. It is.

[Read mode]
The control unit 203 outputs a control signal CONT instructing “application of read voltage” to the bit line / plate line driver 207.

  When the bit line / plate line driver 207 receives the control signal CONT instructing “reading voltage application” from the control unit 203, the reading voltage VREAD between the bit line B1 selected by the column decoder 206 and the selected plate line P1. Apply.

  At this time, an activation voltage is applied to the word line W1 selected by the row decoder 204 by the word line driver 205. For this reason, the drain and the source of the selection transistor T211 are in a conductive state.

  Therefore, for example, a measurement voltage having a voltage value of +0.4 V is applied to the memory cell MC211 as the read voltage VREAD. As a result, a read current indicating a current value corresponding to the resistance value of the resistance change element R211 flows from the bit line B1 to the plate line P1 via the resistance change element R212. The read voltage VREAD is a sufficiently low voltage that does not change the resistance value of the resistance change element of the memory cell even when applied to the memory cell.

  Note that since the measurement voltage is not applied to the memory cells MC221 and MC222 and the activation voltage is not applied to the gate of the selection transistor T212 of the memory cell MC212, the current does not flow through the memory cells MC212, MC221, and MC222. .

  Next, a sense amplifier (not shown) connected to the bit line compares the current value of the read current flowing through the bit line B1 with the current value flowing through the reference resistance value, and controls the signal IREAD indicating the result. The data is output to the unit 203.

  The control unit 203 outputs output data Dout corresponding to the current value indicated by the signal IREAD to the outside. For example, when the current value indicated by the signal IREAD corresponds to the current value of the current that flows when the resistance change element R211 is in the low resistance state, the control unit 203 outputs the output data Dout indicating “2”.

  In this way, a current corresponding to the resistance value of the resistance change element R211 of the memory cell MC211 flows only in the memory cell MC211 and the current flows to the sense circuit provided in the bit line / plate line driver 207. As a result, data indicating “2” is read from the memory cell MC211.

  The resistance value of the resistance change element R211 of the memory cell MC211 is measured by measuring the voltage in the process in which the voltage precharged in the resistance change element R211 is attenuated with a time constant corresponding to the resistance value of the resistance change element R211. Also good.

  When reading from the memory cell MC211 is completed, a new address signal ADDRESS is input to the address buffer 202, and the operation in the read mode of the nonvolatile memory device 200 is repeated for memory cells other than the memory cell MC211.

[First erase mode]
In the first erase mode, first, the control unit 203 acquires the resistance value state (memory state) of the resistance change element R211 of the memory cell MC211 by executing the read mode. When it is determined that bit data indicating “2” is stored in the memory cell MC211 (when it is determined that the resistance change element R211 of the memory cell MC211 is in the low resistance state), the control unit 203 determines that the “first The control signal CONT indicating “1 erase voltage application” is output to the bit line / plate line driver 207. When it is determined that bit data indicating “0” is stored in the memory cell MC211 (when it is determined that the resistance change element R211 of the memory cell MC211 is in the high resistance state), the control unit 203 reads “Write A control signal CONT indicating “voltage application” and “first erase voltage application” is output to the bit line / plate line driver 207. On the other hand, when it is determined that bit data indicating “1” is stored in the memory cell MC211 (when it is determined that the resistance change element R211 of the memory cell MC211 is in the middle resistance state), the control unit 203 performs the above control. The signal CONT is not output.

  When it is determined that bit data indicating “2” is stored in the memory cell MC211, the bit line / plate line driver 207 receives a control signal CONT indicating “first erase voltage application” from the control unit 203. A first erase voltage VRESET1 (first erase voltage pulse) is applied between the bit line B1 selected by the column decoder 206 and the selected plate line P1.

  At this time, an activation voltage is applied to the word line W1 selected by the row decoder 204 by the word line driver 205. For this reason, the drain and the source of the selection transistor T211 are in a conductive state.

  As a result, the first erase voltage VRESET, that is, the first erase voltage pulse having a voltage value of +1.8 V and a pulse width of 100 nsec is applied to the memory cell MC211. As a result, the first erase process in the first embodiment is executed by the pulse voltage application unit, and the resistance value of the resistance change element R211 of the memory cell MC211 changes from the low resistance state to the middle resistance state. On the other hand, since the first erase voltage pulse is not applied to the memory cells MC221 and MC222, and the activation voltage is not applied to the gate of the selection transistor T212 of the memory cell MC212, the resistance change of the memory cells MC212, MC221 and MC222 The resistance state of the element does not change.

  When it is determined that bit data indicating “0” is stored in the memory cell MC211, first, the above-described write mode is executed, and the resistance state of the resistance change element R211 of the memory cell MC211 is changed from the high resistance state. After changing to the low resistance state, the first erase voltage described above is applied, and the resistance state of the resistance change element R211 of the memory cell MC211 changes from the low resistance state to the middle resistance state.

  In this way, only the resistance change element R211 of the memory cell MC211 can be changed from the low resistance state or the high resistance state to the middle resistance state. As a result, data indicating “2” corresponding to the low resistance state stored in the memory cell MC211 or “0” corresponding to the high resistance state changes to “1” corresponding to the medium resistance state.

[Second erase mode]
In the second erase mode, first, the control unit 203 acquires the resistance value state (memory state) of the resistance change element R211 of the memory cell MC211 by executing the read mode. When it is determined that bit data indicating “1” is stored in the memory cell MC211 (when it is determined that the resistance change element R211 of the memory cell MC211 is in the middle resistance state), the controller 203 2 is output to the bit line / plate line driver 207. When it is determined that bit data indicating “2” is stored in the memory cell MC211 (when it is determined that the resistance change element R211 of the memory cell MC211 is in the low resistance state), the control unit 203 determines that the “first A control signal CONT indicating “one erase voltage application” and “second erase voltage application” is output to the bit line / plate line driver 207. On the other hand, when it is determined that bit data indicating “0” is stored in the memory cell MC211 (when it is determined that the resistance change element R211 of the memory cell MC211 is in the high resistance state), the control unit 203 performs the above control. The signal CONT is not output.

  When it is determined that bit data indicating “1” is stored in the memory cell MC 211, the bit line / plate line driver 207 receives the control signal CONT indicating “second erase voltage application” from the control unit 203. A second erase voltage VRESET2 (second erase voltage pulse) is applied between the bit line B1 selected by the column decoder 206 and the selected plate line P1.

  At this time, an activation voltage is applied to the word line W1 selected by the row decoder 204 by the word line driver 205. For this reason, the drain and the source of the selection transistor T211 are in a conductive state.

  As a result, the second erase voltage VRESET, that is, the second erase voltage pulse having a voltage value of −1.0 V and a pulse width of 100 ns is applied to the memory cell MC211. Thereby, the second erase process in the first embodiment is executed by the pulse voltage application unit, and the resistance value of the resistance change element R211 of the memory cell MC211 changes from the middle resistance state to the high resistance state. On the other hand, since the second erase voltage pulse is not applied to the memory cells MC221 and MC222, and the activation voltage is not applied to the gate of the selection transistor T212 of the memory cell MC212, the resistance change of the memory cells MC212, MC221 and MC222 The resistance state of the element does not change.

  When it is determined that bit data indicating “2” is stored in the memory cell MC211, first, the first erase mode described above is executed, and the resistance state of the resistance change element R211 of the memory cell MC211 is low. The resistance state is changed to the middle resistance state, and then the second erase voltage described above is applied, and the resistance state of the resistance change element R211 of the memory cell MC211 changes from the middle resistance state to the high resistance state.

  In this way, only the resistance change element R211 of the memory cell MC211 can be changed from the middle resistance state or the low resistance state to the high resistance state. As a result, data indicating “1” corresponding to the medium resistance state stored in the memory cell MC211 or “2” corresponding to the low resistance state changes to “0” corresponding to the high resistance state.

  In the third erase mode, the control unit 203 repeats the first erase mode and the second erase mode a predetermined number of times, or while performing the read mode and the determination (S4) in FIG. The first erase mode and the second erase mode are repeated.

  When the second erasing of the memory cell MC211 is completed, a new address signal ADDRESS is input to the address buffer 202, and the operation in the second erasing mode of the nonvolatile memory device 200 described above is performed in a memory other than the memory cell MC211. Repeated for the cell.

  By operating as described above, the nonvolatile memory device 200 can realize a stable ternary memory operation.

(Embodiment 3)
The third embodiment is a cross-point type nonvolatile memory device including the variable resistance element 10 described in the first embodiment. Here, the cross-point type nonvolatile storage device is a storage device in a mode in which an active layer is interposed at an intersection (a three-dimensional intersection) between a word line and a bit line.

  Hereinafter, the configuration and operation of the nonvolatile memory device according to Embodiment 3 will be described.

[Configuration of non-volatile storage device]
FIG. 9 is a block diagram showing an example of the configuration of the nonvolatile memory device 100 according to Embodiment 3 of the present invention. As shown in FIG. 9, the cross-point nonvolatile memory device 100 includes a memory cell array 101 including a resistance change element, an address buffer 102, a control unit 103, a row decoder 104, a word line driver 105, A column decoder 106 and a bit line driver 107 are provided. The bit line driver 107 includes a sense circuit, and can measure a current flowing through the bit line and a generated voltage.

  As shown in FIG. 9, the memory cell array 101 includes a plurality of word lines W1, W2, W3,... Formed in parallel to each other and extending in the lateral direction, and these word lines W1, W2, W3,. A plurality of bit lines B1, B2, B3,... Are formed so as to intersect and extend in parallel with each other in the vertical direction. Here, the word lines W1, W2, W3,... Are formed in a first plane parallel to the main surface of the substrate (not shown), and the bit lines B1, B2, B3,. It is formed in a second plane located above or below one plane and substantially parallel to the first plane. Therefore, the word lines W1, W2, W3,... And the bit lines B1, B2, B3,... Have a three-dimensional intersection. , MC23, MC31, MC32, MC33,... (Hereinafter referred to as “memory cells MC11, MC12,...”) Are provided.

  Each memory cell MC includes a resistance change element R11, R12, R13, R21, R22, R23, R31, R32, R33,..., And a current control element composed of, for example, a bidirectional diode connected to each of these in series. D11, D12, D13, D21, D22, D23, D31, D32, D33,. The resistance change element is connected to the bit lines B1, B2, B3,..., And the current control element is connected to the resistance change element and the word lines W1, W2, W3,. As the resistance change element, the resistance change element 10 according to the first embodiment can be used. As the current control element, an MIM (Metal Insulator Metal) diode, an MSM (Metal Semiconductor Metal) diode, a varistor, or the like can be used.

  The address buffer 102 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 104 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 106. . Here, the address signal ADDRESS is a signal indicating the address of the selected memory cell among the memory cells MC12, MC21,. The row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS, and the column address signal COLUMN is a signal similarly indicating a column address.

  Hereinafter, in the case of voltage application, each voltage is applied with reference to the bit line.

  The control unit 103 selects any one of the write mode, the first erase mode, the second erase mode, the third erase mode, and the read mode according to the mode selection signal MODE received from the external circuit. select.

  In the writing mode, the first erasing mode, the second erasing mode, and the third erasing mode, the control unit 103 determines the writing voltage pulse, the first erasing voltage pulse, and the like in accordance with the input data Din received from the external circuit. The second erase voltage pulse or a plurality of sets of the first erase voltage pulse and the second erase voltage pulse are output to the word line driver 105.

  Further, in the read mode, the control unit 103 outputs a read voltage to the word line driver 105. In this read mode, the control unit 103 further receives the signal IREAD output from the bit line driver 107 and outputs output data Dout indicating a bit value corresponding to the signal IREAD to an external circuit. This signal IREAD is a signal indicating the current value of the current flowing through the word lines W1, W2, W3,... In the read mode.

  The row decoder 104 receives the row address signal ROW output from the address buffer 102, and selects any one of the word lines W1, W2, W3,... According to the row address signal ROW. The word line driver 105 applies an activation voltage to the word line selected by the row decoder 104 based on the output signal of the row decoder 104.

  The column decoder 106 receives the column address signal COLUMN output from the address buffer 102, and selects any one of the bit lines B1, B2, B3,... According to the column address signal COLUMN.

  The bit line driver 107 sets the bit line selected by the column decoder 106 to the ground state based on the output signal of the column decoder 106.

  Note that this embodiment is a single-layer cross-point nonvolatile memory device, but a multi-layer cross-point nonvolatile memory device may be formed by stacking memory cell arrays.

  Further, the positional relationship between the resistance change element and the current control element may be interchanged. That is, the bit line may be connected to the resistance change element, and the word line may be connected to the current control element.

  Further, the bit line and / or the word line may also serve as an electrode in the resistance change element.

  In the present embodiment, similarly to the second embodiment, functionally, a predetermined pulse voltage is applied to the selected memory cell (resistance change element) by the control unit 103 and the word line driver 105. A pulse voltage application unit is configured. With such a pulse voltage application unit, at least (1) a write voltage pulse (interelectrode voltage Vα) having a first polarity is applied to a memory cell, thereby changing the resistance state of the resistance change element of the memory cell. (2) a first erasing voltage pulse (interelectrode voltage Vγ) having a second polarity different from the first polarity in the memory cell; A first erasing process for changing the resistance state of the resistance change element of the memory cell from a low resistance state to a medium resistance state by applying, and (3) a second erasing voltage pulse (electrode) having a first polarity. A second erasing process for changing the resistance state of the resistance change element of the memory cell from the middle resistance state to the high resistance state by applying a voltage Vβ) to the memory cell; and (4) writing After or after the first erasing process, the first erasing process and the second erasing process are repeatedly performed on the memory cell, thereby changing the resistance state of the resistance change element of the memory cell to a low resistance. And a third erasing process for changing the state or the intermediate resistance state to the high resistance state.

[Operation of non-volatile storage device]
Hereinafter, the operation example of the nonvolatile memory device 100 configured as described above is divided into the above-described write mode, first erase mode, second erase mode, third erase mode, and read mode. I will explain. Note that a known method can be used as a method for selecting a bit line and a word line, a method for applying a voltage pulse, and the like, and thus detailed description thereof is omitted.

  Hereinafter, a case where writing / reading is performed on the memory cell MC22 will be described as an example.

[Write mode]
When data representing “2” is written (stored) in the memory cell MC22, the bit line driver 107 grounds the bit line B2, and the word line driver 105 electrically connects the word line W2 and the control unit 103. . Then, the control unit 103 applies a write voltage pulse to the word line W2. Here, the voltage value of the write voltage pulse is set to -2.4 V, and the pulse width is set to 100 ns.

  By the operation as described above, the write process in the first embodiment is executed by the pulse voltage application unit, and the write voltage pulse is applied to the resistance change element R22 of the memory cell MC22. Therefore, the resistance change element R22 of the memory cell MC22. Becomes a low resistance state corresponding to “2”.

[First erase mode]
When data representing “1” is written (stored) in the memory cell MC22, the bit line driver 107 grounds the bit line B2, and the word line driver 105 electrically connects the word line W2 and the control unit 103. Is done. Then, the control unit 103 applies a first erase voltage pulse to the word line W2. Here, the voltage value of the erase voltage pulse is set to +1.8 V, and the pulse width is set to 100 ns.

  By the operation as described above, the first erase process in the first embodiment is performed by the pulse voltage application unit, and the first erase voltage pulse is applied to the resistance change element R22 of the memory cell MC22. The resistance change element R22 of the MC 22 is in a medium resistance state corresponding to “1”.

[Second erase mode]
When data representing “0” is written (stored) in the memory cell MC22, the bit line driver 107 grounds the bit line B2, and the word line driver 105 electrically connects the word line W2 and the control unit 103. Is done. Then, the control unit 103 applies a first erase voltage pulse to the word line W2. Here, the voltage value of the erase voltage pulse is set to -1.0 V, and the pulse width is set to 100 ns.

  With the operation as described above, the second erase process in the first embodiment is executed by the pulse voltage application unit, and the second erase voltage pulse is applied to the resistance change element R22 of the memory cell MC22. The resistance change element R22 of MC22 is in a high resistance state corresponding to “0”.

  In the third erase mode, the first erase mode and the second erase mode are repeated a certain number of times, or the first read mode and the determination (S4) shown in FIG. The erase mode and the second erase mode are repeated.

[Read mode]
When reading data written in the memory cell MC22, the bit line B2 is grounded by the bit line driver 107, and the word line W2 and the control unit 103 are electrically connected by the word line driver 105. Then, the control unit 103 applies a read voltage to the word line W2. Here, the voltage value of the read voltage is set to + 0.4V.

  When a read voltage is applied to memory cell MC22, a current having a current value corresponding to the resistance value of resistance change element R22 of memory cell MC22 flows between bit line B2 and word line W2. Control unit 103 detects the current value of this current, and detects the resistance state of memory cell MC22 based on the current value and the read voltage.

  If the resistance change element R22 of the memory cell MC22 is in the low resistance state, it can be seen that the data written in the memory cell MC22 is “2”. In addition, it can be seen that the data written in the memory cell MC22 is “1” in the middle resistance state. Further, it can be seen that the data written in the memory cell MC22 is “0” in the high resistance state.

  By operating as described above, the nonvolatile memory device 100 can realize a ternary memory operation.

  In the above description, the bit line is grounded and a predetermined voltage pulse is applied to the word line. However, different voltage pulses are applied to the bit line and the word line, respectively, and the potential difference is a predetermined voltage. You may comprise so that it may become.

(Other embodiments)
In each of the above embodiments, the transition metal oxide layer 3 has a laminated structure of tantalum oxide, but the present invention is not limited to this. For example, a stacked structure of hafnium (Hf) oxide or a stacked structure of zirconium (Zr) oxide may be used.

In the case of adopting a hafnium oxide laminated structure as the transition metal oxide layer 3, the composition of the first hafnium oxide to be the first transition metal oxide layer 3a is HfO _x and the second transition metal oxide When the composition of the second hafnium oxide to be the layer 3b is HfO _y , x is about 0.9 to 1.6 and y is about 1.8 to 2.0. The film thickness of the object is preferably 3 nm or more and 4 nm or less.

In addition, when a laminated structure of zirconium oxide is adopted as the transition metal oxide layer 3, the composition of the first zirconium oxide to be the first transition metal oxide layer 3a is ZrO _x, and the second transition metal When the composition of the second zirconium oxide to be the oxide layer 3b is ZrO _y , x is about 0.9 to 1.4, y is about 1.9 to 2.0, The film thickness of the zirconium oxide is preferably 1 nm or more and 5 nm or less.

  When the transition metal oxide layer 3 is a hafnium oxide, the first hafnium oxide is formed on the first electrode 2 by a so-called reactive sputtering method using an Hf target and sputtering in argon gas and oxygen gas. A physical layer is formed. The second hafnium oxide layer can be formed by exposing the surface of the first hafnium oxide layer to a plasma of argon gas and oxygen gas after forming the first hafnium oxide layer. The oxygen content of the first hafnium oxide layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering. The substrate temperature can be set to room temperature without any particular heating.

The thickness of the second hafnium oxide layer can be easily adjusted by the exposure time of the argon gas and oxygen gas to the plasma. When the composition of the first hafnium oxide layer is represented as HfO _x and the composition of the second hafnium oxide layer is represented as HfO _y , 0.9 ≦ x ≦ 1.6, 1.8 <y, and the second hafnium Stable resistance change characteristics can be realized when the thickness of the oxide layer is in the range of 3 nm to 4 nm.

When the transition metal oxide layer 3 is a zirconium oxide, the first zirconium oxide layer is formed on the first electrode 2 by a so-called reactive sputtering method using a Zr target and sputtering in argon gas and oxygen gas. Form. The second zirconium oxide layer can be formed by exposing the surface of the first zirconium oxide layer to plasma of Ar gas and O ₂ gas after forming the first zirconium oxide layer. The oxygen content of the first zirconium oxide layer can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering. The substrate temperature can be set to room temperature without any particular heating.

The film thickness of the second zirconium oxide layer can be easily adjusted by the exposure time of the argon gas and oxygen gas to the plasma. When the composition of the first zirconium oxide layer is expressed as ZrO _x and the composition of the second zirconium oxide layer is expressed as ZrO _y , 0.9 ≦ x ≦ 1.4, 1.9 <y, Stable resistance change characteristics can be realized when the thickness of the oxide layer is in the range of 1 nm to 5 nm.

  Furthermore, different materials may be used for the first transition metal constituting the first transition metal oxide layer 3a and the second transition metal constituting the second transition metal oxide layer 3b. In this case, it is preferable that the second transition metal oxide layer 3b has a lower degree of oxygen deficiency than the first transition metal oxide layer 113a, that is, has a higher resistance value. Here, as described above, the oxygen deficiency refers to the ratio of oxygen deficiency with respect to the amount of oxygen constituting the oxide of the stoichiometric composition in each transition metal. By adopting such a configuration, a voltage (interelectrode voltage) applied between the first electrode 2 and the second electrode 4 at the time of resistance change is more increased in the second transition metal oxide layer 3b. The redox reaction that is distributed and occurs in the second transition metal oxide layer 3b can be more easily caused.

In the case where a material in which the first transition metal and the second transition metal are different from each other is used, the standard electrode potential of the second transition metal is preferably lower than the standard electrode potential of the first transition metal. This is because it is considered that a resistance change phenomenon occurs when an oxidation-reduction reaction occurs in a minute conductive path formed in the second transition metal oxide layer 3b having a high resistance value and the resistance value changes. . For example, a stable resistance changing operation can be obtained by using oxygen-deficient tantalum oxide for the first transition metal oxide layer 3a and TiO ₂ for the second transition metal oxide layer 3b. Titanium (standard electrode potential = −1.63 eV) is a material having a lower standard electrode potential than tantalum (standard electrode potential = −0.6 eV). The standard electrode potential represents a characteristic that the higher the value, the less likely it is to be oxidized. By disposing a metal oxide having a lower standard electrode potential than that of the first transition metal oxide layer 3a in the second transition metal oxide layer 3b, more redox is achieved in the second transition metal oxide layer 3b. Reaction is likely to occur.

  Further, the second transition metal oxide layer 3b is formed to have a film thickness smaller than a predetermined film thickness (formed at least thinner than the film thickness of the first transition metal oxide layer 3a). The initial break voltage for forming the conductive path in the oxide layer 3b can be reduced.

  In the above-described embodiment, the transition metal oxide as the resistance change layer has been described with respect to tantalum oxide, hafnium oxide, zirconium oxide, etc., but the transition metal oxide sandwiched between the upper and lower electrodes has been described. The physical layer only needs to contain an oxide layer such as tantalum, hafnium, zirconium, etc. as the main variable resistance layer that exhibits resistance change, and may contain, for example, a trace amount of other elements. . It is also possible to intentionally include a small amount of other elements by fine adjustment of the resistance value, and such a case is also included in the scope of the present invention. For example, if nitrogen is added to the resistance change layer, the resistance value of the resistance change layer increases and the reactivity of resistance change can be improved.

Therefore, in the resistance change element using the oxygen-deficient transition metal oxide M for the resistance change layer, the resistance change layer is set to MO _x (where the configuration of the transition metal oxide in the stoichiometric configuration is MO _s . Oxygen-deficient first transition metal oxide layer having a composition represented by 0 <x <s) and NO _y (where NO _{y is} a resistance value> MO _{x is} a resistance value) When the second transition metal oxide layer having the composition is used, the first oxygen-deficient transition metal oxide layer and the second transition metal oxide layer have the transition metal oxidation of the corresponding composition. In addition to substances, it does not prevent the inclusion of predetermined impurities (for example, additives for adjusting the resistance value).

  In addition, when a resistance film is formed by sputtering, an unintended trace amount of elements may be mixed into the resistance film (resistance change layer) due to residual gas or outgassing from the vacuum vessel wall. Naturally, a trace amount of elements mixed in the resistance film is also included in the scope of the present invention.

  As described above, the variable resistance element, the driving method thereof, the nonvolatile memory device, and the multi-value memory method according to the present invention have been described using the first to third embodiments and the modifications thereof. The present invention is not limited to the embodiment and the modification. Without departing from the spirit of the present invention, embodiments obtained by subjecting each embodiment and modifications thereof to various modifications conceived by those skilled in the art, and arbitrary combinations of components in each embodiment and modifications thereof The form obtained by this is also included in the present invention.

  The present invention relates to a nonvolatile resistance change element, a driving method thereof, a multi-value storage method, and a nonvolatile storage device, in particular, a nonvolatile storage element used in various electronic devices such as a personal computer or a portable telephone, and the driving thereof. It is useful as a method and a nonvolatile memory device.

DESCRIPTION OF SYMBOLS 1 Substrate 2 1st electrode 3 Transition metal oxide layer 3a 1st transition metal oxide layer 3b 2nd transition metal oxide layer 3c Conductive path 4 2nd electrode 5 Power supply 10 Resistance change element 100 Nonvolatile memory device 101 Memory Cell array 102 Address buffer 103 Control unit 104 Row decoder 105 Word line driver 106 Column decoder 107 Bit line driver W1, W2, W3 Word lines B1, B2, B3 Bit lines MC11, MC12, MC13, MC21, MC22, MC23, MC31, MC32 MC33 Memory cells D11, D12, D13, D21, D22, D23, D31, D32, D33 Current control element (bidirectional diode)
R11, R12, R13, R21, R22, R23, R31, R32, R33 Resistance change element 200 Non-volatile memory device 201 Memory cell array 202 Address buffer 203 Control unit 204 Row decoder 205 Word line driver 206 Column decoder 207 Bit line / plate line Driver W1, W2 Word line B1, B2 Bit line MC211, MC212, MC221, MC222 Memory cell T211, T212, T221, T222 Select transistor R211, R212, R221, R222 Resistance change element

Claims (22)

For a resistance change element comprising a first electrode, a second electrode, and a resistance change layer made of an oxygen-deficient transition metal oxide disposed between the first electrode and the second electrode By applying an interelectrode voltage that is the potential of the second electrode with respect to the first electrode, the interelectrode resistance value that is the resistance value between the first electrode and the second electrode is reversible. A variable resistance element driving method for changing
For the RL, RM, and RH that satisfy the interelectrode voltages Vα and Vβ of the first polarity, the interelectrode voltage Vγ of the second polarity different from the first polarity, and RL <RM <RH.
The interelectrode voltages Vα and Vβ satisfy | Vα |> | Vβ |
A writing process for setting the interelectrode resistance value to the RL by applying the interelectrode voltage Vα to the variable resistance element;
Applying a voltage Vγ between the electrodes to the variable resistance element having the interelectrode resistance value RL, thereby setting the interelectrode resistance value of the variable resistance element to the RM;
A resistance change element driving method comprising: a second erasing process of setting the interelectrode resistance value to the RH by applying the interelectrode voltage Vβ to the resistance change element having the interelectrode resistance value of the RM. .   Further, after the second erasing process is performed, the first erasing process and the second erasing process are further performed one or more times to set the inter-electrode resistance value to the RH. The method of driving a resistance change element according to claim 1, further comprising an erasing process.   In the third erasing process, it is determined whether or not the inter-electrode resistance value after the second erasing process is larger than a predetermined threshold value, and the inter-electrode resistance value is not larger than the threshold value. 3. The resistance change element driving method according to claim 2, wherein the first erasing process and the second erasing process are executed at least once.   The variable resistance layer includes a first variable resistance layer composed of a first oxygen-deficient transition metal oxide connected to the first electrode, and a degree of oxygen deficiency higher than that of the first transition metal oxide. And the second resistance change layer made of the second transition metal oxide connected to the second electrode is stacked and configured. A method of driving the resistance change element.   The resistance change element driving method according to claim 4, wherein the second resistance change layer has a resistance value higher than that of the first resistance change layer.   6. The standard electrode potential of the second transition metal constituting the second transition metal oxide is lower than the standard electrode potential of the first transition metal constituting the first transition metal oxide. 6. The driving method of the resistance change element according to the above. The first transition metal oxide is composed of a tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9),
The driving method of a resistance change element according to claim 4, wherein the second transition metal oxide is composed of a tantalum oxide having a composition represented by TaO _y (where 2.1 ≦ y). . A resistance change element comprising: a first electrode; a second electrode; and a resistance change layer made of an oxygen-deficient transition metal oxide disposed between the first electrode and the second electrode. A memory cell;
A pulse voltage application unit for applying a pulse voltage to the memory cell,
The pulse voltage application unit is
By applying an interelectrode voltage, which is the potential of the second electrode with respect to the first electrode, to the memory cell, an interelectrode resistance value, which is a resistance value between the first electrode and the second electrode, is obtained. Reversibly change,
RL, RM, and RH satisfying the interelectrode voltages Vα and Vβ having the first polarity, the interelectrode voltage Vγ having the second polarity different from the first polarity, and RL <RM <RH.
The interelectrode voltages Vα and Vβ satisfy | Vα |> | Vβ |
A writing process of setting the inter-electrode resistance value to the RL by applying the inter-electrode voltage Vα to the memory cell;
Applying a voltage Vγ between the electrodes to the variable resistance element having an interelectrode resistance value of RL, thereby setting the interelectrode resistance value to the RM;
Performing a second erasing process of setting the interelectrode resistance value to the RH by applying the interelectrode voltage Vβ to the memory cell in the resistance change element having the interelectrode resistance value of the RM. Sex memory device.   The pulse voltage applying unit further performs the first erasing process and the second erasing process at least once after performing the second erasing process, thereby setting the inter-electrode resistance value to the RH. The non-volatile memory device according to claim 8, wherein a third erasing process is performed.   In the third erasing process, the pulse voltage application unit determines whether the interelectrode resistance value after the second erasing process is larger than a predetermined threshold, and the interelectrode resistance value is 10. The nonvolatile memory device according to claim 9, wherein the first erasing process and the second erasing process are executed at least once when not larger than the threshold value. 11.   The variable resistance layer includes a first variable resistance layer composed of a first oxygen-deficient transition metal oxide connected to the first electrode, and a degree of oxygen deficiency higher than that of the first transition metal oxide. And the second resistance change layer made of the second transition metal oxide connected to the second electrode is stacked and formed. Non-volatile storage device.   The nonvolatile memory device according to claim 11, wherein the second resistance change layer has a resistance value higher than that of the first resistance change layer.   The standard electrode potential of the second transition metal constituting the second transition metal oxide is lower than the standard electrode potential of the first transition metal constituting the first transition metal oxide. The non-volatile memory device described in 1. The first transition metal oxide is composed of a tantalum oxide having a composition represented by TaO _x (where 0.8 ≦ x ≦ 1.9),
13. The nonvolatile memory device according to claim 11, wherein the second transition metal oxide is composed of a tantalum oxide having a composition represented by TaO _y (where 2.1 ≦ y).   The nonvolatile memory device according to claim 8, wherein the memory cell further includes a current control element connected to the first electrode or the second electrode.   The nonvolatile memory device according to claim 15, wherein the current control element is a selection transistor.   The nonvolatile memory device according to claim 15, wherein the current control element is a diode. A first electrode;
A second electrode;
A resistance change layer composed of an oxygen-deficient transition metal oxide disposed between the first electrode and the second electrode;
By applying an inter-electrode voltage that is a potential of the second electrode with respect to the first electrode, an inter-electrode resistance value that is a resistance value between the first electrode and the second electrode is reversible. Change,
RL, RM, and RH satisfying the interelectrode voltages Vα and Vβ having the first polarity, the interelectrode voltage Vγ having the second polarity different from the first polarity, and RL <RM <RH.
The interelectrode voltages Vα and Vβ satisfy | Vα |> | Vβ |
When the interelectrode voltage Vα is applied, the interelectrode resistance value changes to RL,
When the interelectrode resistance value is RL, the interelectrode resistance value is changed to the RM by applying the interelectrode voltage Vγ.
A resistance change element in which the interelectrode resistance value changes to the RH when the interelectrode voltage Vβ is applied when the interelectrode resistance value is the RM. For a resistance change element comprising a first electrode, a second electrode, and a resistance change layer made of an oxygen-deficient transition metal oxide disposed between the first electrode and the second electrode By applying an inter-electrode voltage that is the potential of the second electrode with respect to the first electrode, an inter-electrode resistance value that is a resistance value between the first electrode and the second electrode is increased. A multi-value storage method of a resistance change element that reversibly changes between values,
RL, RM, RH1, RH2 satisfying the interelectrode voltages Vα, Vβ1, and Vβ2 of the first polarity, the interelectrode voltage Vγ of the second polarity different from the first polarity, and RL <RM <RH1 <RH2. about,
The interelectrode voltages Vα, Vβ1 and Vβ2 satisfy | Vα |> | Vβ2 |> | Vβ1 |
A writing process of setting the inter-electrode resistance value to the RL by applying the inter-electrode voltage Vα to the variable resistance element;
Applying a voltage Vγ between the electrodes to the variable resistance element having the interelectrode resistance value RL, thereby setting the interelectrode resistance value of the variable resistance element to the RM;
Applying a voltage Vβ1 between the electrodes to the resistance change element having an interelectrode resistance value of the RM, thereby setting the interelectrode resistance value to the RH1;
Applying a voltage Vβ2 between the electrodes to the variable resistance element having an interelectrode resistance value of RM or RH1, thereby setting the interelectrode resistance value to RH2;
A multi-value storage method for a resistance change element, comprising:   Further, after performing the second first erase process or the second second erase process, the first erase process, the second first erase process, or the second second erase process, The multi-value storage method for a resistance change element according to claim 19, further comprising performing a third erasing process to set the inter-electrode resistance value to the RH1 or the RH2 by further performing at least once.   In the third erasing process, it is determined whether or not the interelectrode resistance value after the second erasing process is equal to or higher than a predetermined first threshold value and lower than or equal to a second threshold value. When the interelectrode resistance value is smaller than the first threshold value or larger than the second threshold value, the first erase process and the second first erase process are executed at least once. The multi-value storage method for a variable resistance element according to claim 20.   In the third erasing process, it is determined whether the interelectrode resistance value after the second erasing process is equal to or greater than a predetermined third threshold value, and the interelectrode resistance value is 21. The multi-value storage method for a resistance change element according to claim 20, wherein when the threshold value is smaller than 3, the first erase process and the second 2 erase process are executed at least once.

Images