JP2005332361A - プログラム命令圧縮装置および方法 - Google Patents

プログラム命令圧縮装置および方法 Download PDF

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Publication number
JP2005332361A
JP2005332361A JP2004343921A JP2004343921A JP2005332361A JP 2005332361 A JP2005332361 A JP 2005332361A JP 2004343921 A JP2004343921 A JP 2004343921A JP 2004343921 A JP2004343921 A JP 2004343921A JP 2005332361 A JP2005332361 A JP 2005332361A
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Japan
Prior art keywords
instruction
program
data path
program instructions
data processing
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Japanese (ja)
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JP2005332361A5 (enExample
Inventor
Jan Guffens
グーフェンス ヤン
Ludwig Callewaert
カレワート ルートヴィヒ
Nieuwenhove Koenraad Van
ファン ニーウヴェンホーフェ コーエンラート
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ARM Ltd
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ARM Ltd
Advanced Risc Machines Ltd
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Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Publication of JP2005332361A publication Critical patent/JP2005332361A/ja
Publication of JP2005332361A5 publication Critical patent/JP2005332361A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
JP2004343921A 2004-05-17 2004-11-29 プログラム命令圧縮装置および方法 Pending JP2005332361A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0410986A GB2414308B (en) 2004-05-17 2004-05-17 Program instruction compression

Publications (2)

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JP2005332361A true JP2005332361A (ja) 2005-12-02
JP2005332361A5 JP2005332361A5 (enExample) 2007-02-22

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JP2004343921A Pending JP2005332361A (ja) 2004-05-17 2004-11-29 プログラム命令圧縮装置および方法

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Country Link
US (1) US7302552B2 (enExample)
JP (1) JP2005332361A (enExample)
GB (1) GB2414308B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015143991A (ja) * 2006-09-22 2015-08-06 インテル コーポレイション 文字列を処理するための命令及び論理回路
US10416888B2 (en) 2016-09-09 2019-09-17 Fujitsu Limited Parallel processing device, method for controlling parallel processing device, and controller used in parallel processing device

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GB2370380B (en) 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
GB2420884B (en) * 2004-12-03 2009-04-15 Picochip Designs Ltd Processor architecture
US7581082B2 (en) * 2005-05-13 2009-08-25 Texas Instruments Incorporated Software source transfer selects instruction word sizes
GB2430773A (en) * 2005-10-03 2007-04-04 Advanced Risc Mach Ltd Alignment of variable length program instructions
US20080077772A1 (en) * 2006-09-22 2008-03-27 Ronen Zohar Method and apparatus for performing select operations
US7624251B2 (en) * 2006-11-01 2009-11-24 Apple Inc. Instructions for efficiently accessing unaligned partial vectors
US7620797B2 (en) * 2006-11-01 2009-11-17 Apple Inc. Instructions for efficiently accessing unaligned vectors
CN101398752B (zh) * 2007-09-29 2011-08-31 国际商业机器公司 重叠指令存取单元和重叠指令存取方法
GB2454865B (en) 2007-11-05 2012-06-13 Picochip Designs Ltd Power control
US20090282220A1 (en) * 2008-05-08 2009-11-12 Mips Technologies, Inc. Microprocessor with Compact Instruction Set Architecture
US20100312991A1 (en) * 2008-05-08 2010-12-09 Mips Technologies, Inc. Microprocessor with Compact Instruction Set Architecture
GB2470037B (en) 2009-05-07 2013-07-10 Picochip Designs Ltd Methods and devices for reducing interference in an uplink
GB2470891B (en) 2009-06-05 2013-11-27 Picochip Designs Ltd A method and device in a communication network
GB2470771B (en) 2009-06-05 2012-07-18 Picochip Designs Ltd A method and device in a communication network
GB2474071B (en) 2009-10-05 2013-08-07 Picochip Designs Ltd Femtocell base station
GB2482869B (en) 2010-08-16 2013-11-06 Picochip Designs Ltd Femtocell access control
GB2484489A (en) * 2010-10-12 2012-04-18 Advanced Risc Mach Ltd Instruction decoder using an instruction set identifier to determine the decode rules to use.
GB2489716B (en) 2011-04-05 2015-06-24 Intel Corp Multimode base system
GB2489919B (en) 2011-04-05 2018-02-14 Intel Corp Filter
GB2491098B (en) 2011-05-16 2015-05-20 Intel Corp Accessing a base station
US20160179542A1 (en) * 2014-12-23 2016-06-23 Patrick P. Lai Instruction and logic to perform a fused single cycle increment-compare-jump
KR102688577B1 (ko) 2016-09-19 2024-07-26 삼성전자주식회사 전자 장치, vliw 프로세서 및 그 제어 방법들

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09512651A (ja) * 1994-05-03 1997-12-16 アドバンスド リスク マシーンズ リミテッド 複数命令セットのマッピング
JPH11194939A (ja) * 1995-07-12 1999-07-21 Mitsubishi Electric Corp データ処理装置
JP2002533815A (ja) * 1998-12-18 2002-10-08 ボプス インコーポレイテッド 動的コンパクト命令を有するスケーラブル命令セットアーキテクチャのための方法及び装置

Family Cites Families (6)

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US5057837A (en) * 1987-04-20 1991-10-15 Digital Equipment Corporation Instruction storage method with a compressed format using a mask word
US5826054A (en) * 1996-05-15 1998-10-20 Philips Electronics North America Corporation Compressed Instruction format for use in a VLIW processor
US5922065A (en) * 1997-10-13 1999-07-13 Institute For The Development Of Emerging Architectures, L.L.C. Processor utilizing a template field for encoding instruction sequences in a wide-word format
JP4502532B2 (ja) * 2001-02-23 2010-07-14 株式会社ルネサステクノロジ データ処理装置
WO2004017197A2 (en) * 2002-08-16 2004-02-26 Koninklijke Philips Electronics N.V. Apparatus, method, and compiler enabling processing of variable length instructions in a very long instruction word processor
EP1546869B1 (en) * 2002-09-24 2013-04-03 Silicon Hive B.V. Apparatus, method, and compiler enabling processing of load immediate isntructions in a very long instruction word processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09512651A (ja) * 1994-05-03 1997-12-16 アドバンスド リスク マシーンズ リミテッド 複数命令セットのマッピング
JPH11194939A (ja) * 1995-07-12 1999-07-21 Mitsubishi Electric Corp データ処理装置
JP2002533815A (ja) * 1998-12-18 2002-10-08 ボプス インコーポレイテッド 動的コンパクト命令を有するスケーラブル命令セットアーキテクチャのための方法及び装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015143991A (ja) * 2006-09-22 2015-08-06 インテル コーポレイション 文字列を処理するための命令及び論理回路
US10416888B2 (en) 2016-09-09 2019-09-17 Fujitsu Limited Parallel processing device, method for controlling parallel processing device, and controller used in parallel processing device

Also Published As

Publication number Publication date
US20050257028A1 (en) 2005-11-17
GB2414308B (en) 2007-08-15
GB2414308A (en) 2005-11-23
GB0410986D0 (en) 2004-06-16
US7302552B2 (en) 2007-11-27

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