JP2005317768A - Solid-state image pickup element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup element in a structure capable of suppressing the decline of sensitivity due to the reduction of a pixel cell size, and being easily and stably manufactured. <P>SOLUTION: For the solid-state image pickup element, a light receiving sensor 1 is formed inside a semiconductor base body 11, first conducting type impurity regions 21, 22 and 23 are formed under the first conducting type charge storage region 14 of the light receiving sensor 1, and at least a deepest part 23 is formed over the entire image pickup region including the light receiving sensor 1 for the first conducting type impurity regions 21, 22 and 23. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device.

In a solid-state image pickup device such as a CCD solid-state image pickup device, an overflow barrier (hereinafter referred to as OFB) is formed under the light receiving sensor portion so that charges can be accumulated in the light receiving sensor portion.
For example, the P-type semiconductor well region under the N-type charge accumulation region of the light receiving sensor portion becomes the OFB.

By the way, when the size of the pixel cell is reduced, the area of the light receiving sensor portion is reduced, so that the amount of accumulated charge in the light receiving sensor portion is reduced and the sensitivity is lowered.
Therefore, for the purpose of deepening the OFB and increasing the amount of charge accumulated in the light receiving sensor unit, for example, it is considered to form a P-type impurity region that becomes the OFB at a relatively deep position in the semiconductor substrate.

However, even if the P-type impurity region to be the OFB is formed deep in the substrate, as the size of the pixel cell is reduced, modulation is applied from the surroundings, and the OFB is placed at a position shallower than the P-type impurity region. Will be formed. Therefore, there is a problem that the amount of accumulated charge in the light receiving sensor unit cannot be increased, and the sensitivity is lowered due to the decrease in the area of the light receiving sensor unit.
This is considered to be an influence of P-type impurities in the vicinity of the surface of the semiconductor substrate in the pixel cell.

  In order to solve this problem, a technique for forming an N-type impurity region in a relatively deep position of the light receiving sensor portion has been proposed (see, for example, Patent Document 1 or Patent Document 2).

That is, for example, as shown in FIG. 6, a schematic cross-sectional view of the imaging region of the CCD solid-state imaging device is located below the N-type charge accumulation region 54 of the light receiving sensor unit 60 and at the position of the N-type charge accumulation region 54. Correspondingly, N-type impurity regions 71, 72, 73 are formed for each pixel.
As described above, the N-type impurity regions 71, 72, and 73 are formed under the N-type charge accumulation region 54 of the light-receiving sensor unit 60, thereby increasing the charge accumulation amount of the light-receiving sensor unit 60 and increasing the sensitivity. It becomes possible to improve.
JP 2002-164529 A JP 2003-86783 A

  As described above, in order to form an N-type impurity region at a deep position in the light receiving sensor portion, ion implantation with a large energy is required. Therefore, a resist mask serving as a mask for ion implantation is formed as thick as several μm. There is a need.

However, as the size of the pixel cell is further reduced, it becomes difficult to form a thick resist mask pattern with high accuracy, so that the pattern line width of the resist mask varies. As a result, the position where the N-type impurity region is formed varies, which affects the characteristics of each pixel of the solid-state image sensor. For example, the read voltage, the anti-blooming characteristics, and the like are different for each pixel.
This is one of the factors that hinder the stable production of the solid-state imaging device.

  In addition, in order to further improve the sensitivity, if an N-type impurity region is formed deeper in the substrate, the resist mask becomes insufficient in film thickness, so that the impurity region is formed at a desired location. become unable.

  In order to solve the above-described problems, in the present invention, a solid-state imaging device having a structure that can suppress a decrease in sensitivity due to a reduction in pixel cell size and can be manufactured easily and stably. It is to provide.

  In the solid-state imaging device of the present invention, a light receiving sensor portion is formed in a semiconductor substrate, and a first conductivity type impurity region is formed below the first conductivity type charge storage region of the light receiving sensor portion. At least the deepest portion of the conductive impurity region is formed over the entire imaging region including the light receiving sensor portion.

According to the above-described configuration of the solid-state imaging device of the present invention, the potential of the light receiving sensor unit is increased by the first conductive type impurity region formed below the first conductive type charge storage region of the light receiving sensor unit. Therefore, the amount of charge accumulated in the light receiving sensor unit can be increased. As a result, even if the area of the light receiving sensor unit is reduced by reducing the pixel size of the solid-state imaging device, a sufficient amount of storage can be secured by compensating for the decrease in the amount of accumulated charge due to the reduction in the area of the light receiving sensor unit. Is possible.
Further, at least the deepest portion of the first conductivity type impurity region is formed over the entire imaging region including the light receiving sensor unit, thereby forming the first conductivity type impurity region formed over the entire imaging region. In this case, it is not necessary to form a mask pattern with a fine line width, and variations in resist line width and position can be eliminated.
Therefore, for example, even when a thick resist mask is used to perform deep ion implantation, the first conductivity type impurity region can be easily formed with high positional accuracy, which is caused by variations in resist line width and position. Variations in characteristics from pixel to pixel can be reduced.

In the above-described solid-state imaging device of the present invention, the first conductivity type impurity region may be formed over the entire imaging region.
In such a configuration, it is not necessary to form a mask pattern having a fine line width in order to form the first conductivity type impurity region, so that variations in resist line width and position can be completely eliminated. It becomes possible.

According to the above-described present invention, even if the area of the light receiving sensor portion is reduced by reducing the pixel size of the solid-state image sensor, the reduction in the amount of accumulated charges is compensated for by the reduction in the area of the light receiving sensor portion. It becomes possible to secure the amount. As a result, it is possible to suppress a decrease in sensitivity due to the reduction in the pixel cell size and ensure sufficient sensitivity.
Further, since the impurity region of the first conductivity type can be formed at a deeper position, it is possible to increase the charge accumulation amount of the light receiving sensor unit and further improve the sensitivity.

  Furthermore, since it is possible to reduce variations in characteristics of each pixel, it is possible to easily and stably manufacture a solid-state imaging device, and to improve manufacturing yield.

  Therefore, according to the present invention, it is possible to easily reduce the pixel size, and thereby to increase the number of pixels and the size of the solid-state imaging device.

1 and 2 are schematic configuration diagrams of a solid-state imaging device according to an embodiment of the present invention. FIG. 1 is a plan view of the solid-state imaging device, and FIG. 2 is a cross-sectional view taken along line AA of FIG.
In the present embodiment, the present invention is applied to a CCD solid-state imaging device.

  The solid-state imaging device includes a plurality of light receiving sensor units (photosensors) 1 that perform photoelectric conversion arranged in a matrix, and a plurality of vertical transfer registers 2 having a CCD structure corresponding to each column of the light receiving sensor units (photosensors) 1. And an imaging region 4 comprising a channel stop region 3 arranged along a vertical transfer register for separating each pixel, and a signal charge from the imaging region 4 arranged on one end side of the imaging region 4 as an output unit A horizontal transfer register 5 having a CCD structure to be transferred to the output, an output unit 6 connected to the final stage of the horizontal transfer register 5, and a peripheral region 7 having a bus line and the like.

In the imaging region 4, as shown in the cross-sectional view of FIG. 2, an N-type charge accumulation region 14 and a P-type (P ⁺ ) positive charge accumulation region 15 on the surface thereof are formed on a semiconductor substrate 11 made of, for example, a silicon substrate. A light receiving sensor unit (photosensor) 1, a vertical transfer register (transfer channel region) 2, and a channel stop region 3 are formed. A read gate portion 9 is provided between the transfer channel region 2 and the light receiving sensor portion (photosensor) 1.
On the semiconductor substrate 11, a transfer electrode (gate electrode) 17 made of, for example, polycrystalline silicon is formed across the readout gate portion 9 and the channel stop region 3 via a gate insulating film 16. The transfer channel region 2, the gate insulating film 16, and the transfer electrode 17 constitute a vertical transfer portion.
A P-type impurity region 12 serving as an OFB (overflow barrier) is formed at a deep position of the semiconductor substrate 11.
If necessary, a solid-state imaging device is configured by providing components such as a color filter and an on-chip lens on the upper layer.
In the figure, reference numeral 13 denotes a semiconductor region above the P-type impurity region 12 in the semiconductor substrate 11, and the configuration of the semiconductor region 13 is not particularly limited and is the same as a conventionally known configuration. Can be.

Further, three layers of N-type impurity regions 21, 22, and 23 are formed below the N-type charge accumulation region 14 of the light receiving sensor unit (photosensor) 1.
Hereinafter, the N-type impurity regions 21, 22, and 23 are referred to as DSR (Deep SensoR) regions.
By forming these N-type DSR regions 21, 22, and 23, the potential of the light receiving sensor unit (photosensor) 1 is deepened and the charge accumulation amount of the light receiving sensor unit (photosensor) 1 is increased. Can do.

In the present embodiment, among the three layers of DSR regions 21, 22, and 23, the lowermost layer DSR region 21 is formed across adjacent pixels.
On the other hand, the other two layers of the DSR regions 22 and 23 are separated for each pixel as in the conventional configuration shown in FIG. 6, and the N-type charge accumulation of the light receiving sensor unit (photosensor) 1 of each pixel. It is formed at a position corresponding to the region 14.

The lowermost DSR region 21 is formed over at least the entire imaging region 4 in plan view across adjacent pixels.
The DSR region 21 is preferably not formed in the output unit 6 of FIG.
As described above, since the DSR region 21 is formed at least over the entire imaging region 4, a resist mask having a fine line width is not required when the DSR region 21 is formed by ion implantation.

  The solid-state imaging device of the present embodiment can be manufactured as follows, for example.

First, a P-type impurity region 12, a channel stop region 3, and a vertical transfer register region 2 to be OFB are formed on a semiconductor substrate 11 such as a silicon substrate by a conventionally known method.
Next, an N-type impurity is ion-implanted at least over the entire imaging region 4 with a desired energy (relatively high energy) and a dose, thereby forming the lowermost DSR region 21 (see FIG. 3A above).

Next, as shown in FIG. 3B, a resist 31 having a pattern serving as a mask for forming a DSR region for each pixel is formed by photolithography.
Here, since ion implantation of high energy has already been completed in the previous process, the film thickness of the resist 31 can be reduced compared to the case of manufacturing the configuration shown in FIG. Thus, the controllability with respect to the line width and positional deviation of the resist 31 can be sufficiently provided.

  Next, as shown in FIG. 4C, by using the resist 31 as a mask, ion implantation 32 of N-type impurities is performed with a desired energy and dose amount, whereby two layers of DSR regions 22 and 23 for each pixel are formed. Are sequentially formed.

Subsequently, as shown in FIG. 4D, the transfer electrode (gate electrode) 17 on the gate insulating film 16, the N-type charge storage region 14 of the light-receiving sensor unit (photosensor) 1, and the P-type are processed by a method similar to the conventional method. Positive charge storage region 15, interlayer insulating film 18 and light shielding film 19 thereon are formed.
Thereafter, an insulating layer, a planarizing layer, a color filter, and an on-chip lens are formed as necessary.
In this way, the solid-state imaging device of the present embodiment shown in FIGS. 1 and 2 can be manufactured.

  The order of the steps is not limited to the order shown in FIGS. 3A to 4D, but the transfer electrode (gate electrode) 17 is formed in the ion implantation step for the entire imaging region 4 that forms the lowermost DSR region 21. This is done before the process.

According to the above-described embodiment, since the lowermost layer DSR region 21 is formed over at least the entire imaging region 4 across adjacent pixels, the lowermost layer DSR region 21 is formed. It is not necessary to use a resist mask with a fine line width.
For this reason, the resist 31 serving as a mask for forming the two layers of the DSR regions 22 and 23 thereon is not required to withstand high-energy ion implantation. Therefore, in the case of manufacturing the configuration shown in FIG. It becomes possible to make it thinner.
As a result, even if the pattern of the resist 31 becomes finer, variations in the pattern line width can be suppressed and the alignment accuracy can be ensured, and the positional accuracy of the two-layer DSR regions 22 and 23 can be improved as compared with the conventional case. Therefore, variation in characteristics of each pixel can be reduced.

Further, since the DSR regions 21, 22, and 23 are formed under the charge accumulation region 14 of the light receiving sensor unit (photosensor) 1, the charge accumulation amount of the light receiving sensor unit 1 can be increased, thereby improving the sensitivity. Can be improved.
Further, when forming the lowermost layer DSR region 21, it is not necessary to use a resist mask having a fine line width, so that the DSR region 21 can be formed deeper in the semiconductor substrate 11. Thereby, further improvement in sensitivity is expected.

That is, according to the present embodiment, even if the area of the light receiving sensor unit (photosensor) 1 is reduced by reducing the pixel size of the solid-state imaging device, good characteristics can be obtained and the light receiving sensor unit ( It is possible to secure a sufficient accumulation amount by compensating for the decrease in the accumulation amount of charges due to the reduction in the area of the photosensor 1.
Accordingly, it is possible to easily reduce the pixel size, and thereby it is possible to increase the number of pixels and the size of the solid-state imaging device.

  Even if the pattern of the resist 31 becomes fine, variations in the pattern line width can be suppressed, alignment accuracy can be ensured, and variations in characteristics from pixel to pixel can be reduced. Thus, it is possible to manufacture a solid-state imaging device, and the manufacturing yield can be improved.

  Since only the formation process of the lowermost layer DSR region 21 is changed, the manufacturing conditions can be manufactured with almost no change.

  Furthermore, according to the configuration of the present embodiment, it is considered that the lowermost DSR region 21 is formed at least in the entire imaging region 4, so that the shutter voltage can be reduced.

In the above-described embodiment, the DSR region 21 formed in the entire imaging region is one layer, and the DSR regions 22 and 23 formed for each pixel are two layers. However, the number of layers in the DSR region is as follows. It is not limited.
The present invention includes a configuration in which a plurality of DSR regions are formed, and at least the lowest DSR region among these layers is formed over at least the entire imaging region.
The present invention also includes a configuration in which one layer of the DSR region is formed at least over the entire imaging region.

  Next, as another embodiment of the present invention, FIG. 5 shows a schematic configuration diagram (cross-sectional view of an imaging region) of a solid-state imaging device.

In the present embodiment, in particular, the three layers of N-type impurity regions (DSR regions) 21, 22, and 23 under the charge accumulation region 14 of the light receiving sensor unit (photosensor) 1 are all (related to the depth. Rather) over at least the entire imaging region across adjacent pixels.
Other configurations are the same as those of the solid-state imaging device of the previous embodiment shown in FIG. 1 and FIG.

  In this case, the ion implantation process for the entire imaging region for forming the three layers of the DSR regions 21, 22, and 23 is performed before the process for forming the transfer electrode (gate electrode) 17.

  In the present embodiment, the uppermost DSR region 23 is too shallow near the vertical transfer register (transfer channel region) 2 so that the influence on the potential of the vertical transfer register 2 and the like does not increase. Desirably not.

According to the above-described embodiment, the DSR regions 21, 22, and 23 are formed under the charge accumulation region 14 of the light receiving sensor unit (photosensor) 1 as in the previous embodiment, so that the light receiving sensor. Sensitivity can be improved by increasing the amount of charge accumulated in the portion 1.
Thereby, even if the area of the light receiving sensor unit (photosensor) 1 is reduced by reducing the pixel size of the solid-state imaging device, a sufficient accumulation amount can be secured.

Furthermore, according to the present embodiment, all three layers of DSR regions 21, 22, and 23 are formed in the entire imaging region, and there is no DSR region formed for each pixel. This has the advantage that the influence of line width and misalignment can be completely eliminated.
Thereby, it becomes possible to form the DSR regions 21, 22, and 23 deeper in the semiconductor substrate 11, and further improvement in sensitivity is expected.
In addition, the influence of the resist mask line width and misalignment at the time of manufacturing can be completely eliminated, and the variation in characteristics of each pixel can be greatly reduced, so that a solid-state imaging device can be manufactured easily and stably. This can improve the manufacturing yield.

  Therefore, according to the present embodiment, it is possible to easily reduce the pixel size, thereby increasing the number of pixels and the size of the solid-state imaging device.

  Furthermore, according to the configuration of the present embodiment, it is considered that the shutter voltage can be reduced because the DSR areas 21, 22, and 23 are formed at least in the entire imaging area 4.

In each of the above-described embodiments, the DSR regions 21, 22, and 23, and the uppermost DSR region 23 and the charge storage region 14 are both spaced apart vertically. In the invention, like FIG. 1 of Patent Document 1, a part or all of these may be connected in the vertical direction.
Even in that case, the deepest part of the DSR region may be formed at least over the entire imaging region.

In each of the above-described embodiments, the present invention is applied to the CCD solid-state imaging device, but the present invention can also be applied to other configurations.
For example, the present invention can also be applied to a CMOS solid-state imaging device.

In addition, when the present invention is applied to a solid-state imaging device in which the charge accumulation region of the light receiving sensor unit is a P-type, a P-type impurity region is formed as an impurity region formed at least over the entire imaging region.
That is, an impurity region having the same conductivity type as that of the charge accumulation region of the light receiving sensor portion may be formed.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (plan view) of a solid-state imaging device according to an embodiment of the present invention. It is sectional drawing in AA of FIG. FIGS. 3A and 3B are process diagrams showing a manufacturing process of the solid-state imaging device of FIGS. 1 and 2; FIGS. C and D are process diagrams showing manufacturing processes of the solid-state imaging device of FIGS. 1 and 2. It is a schematic block diagram (sectional drawing of an imaging region) of the solid-state image sensor of other embodiment of this invention. FIG. 2 is a schematic cross-sectional view of a CCD solid-state imaging device in which an N-type impurity region is formed under a charge storage region.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Photosensitive sensor part (photo sensor), 2 Vertical transfer register (transfer channel area), 3 Channel stop area, 4 Imaging area, 5 Horizontal transfer register, 6 Output part, 9 Reading gate part, 11 Semiconductor substrate, 12 P type Impurity region (OFB), 14 charge storage region, 15 positive charge storage region, 16 gate insulating film, 17 transfer electrode (gate electrode), 19 light shielding film, 21, 22, 23 N-type impurity region (DSR region), 31 Resist

Claims (4)

A light receiving sensor part is formed in the semiconductor substrate,
A first conductivity type impurity region is formed under the first conductivity type charge storage region of the light receiving sensor unit,
At least the deepest portion of the first conductivity type impurity region is formed over the entire imaging region including the light receiving sensor unit.   2. The solid-state imaging device according to claim 1, wherein all of the first conductivity type impurity regions are formed over the entire imaging region.   2. The solid-state imaging device according to claim 1, wherein a plurality of impurity regions of the first conductivity type are formed, and at least a lowermost layer of the plurality of layers is formed over the entire imaging region.   The layer of the plurality of layers other than the layer formed over the entire imaging region is formed separately for each pixel under the light receiving sensor unit. Solid-state image sensor.

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