JP2005317150A - Optical disk playback device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical recording medium playback device capable of executing rotary phase control having excellent time response characteristics regarding the rotary phase control of an optical recording medium. <P>SOLUTION: This optical disk playback device is provided with a memory for operating a first-in first-out operation, and controls the rotation of an optical disk medium so as to reduce a phase difference between a writing timing signal and a reading timing signal. In the memory, data is written based on the writing timing signal, and data is read based on the reading timing signal. The writing timing signal is generated from a signal taken out of the optical recording medium. The reading timing signal is generated from a stable oscillation source such as a crystal oscillator. The optical disk playback device is provided with a phase difference count/phase difference information calculation part for calculating a phase difference based on a bank information signal indicating a deviation amount from a center value in the first-in first-out operation of the memory, the writing timing signal, and the reading timing signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an optical disc reproducing apparatus, and more particularly to rotational phase control of an optical recording medium.

  Optical disc playback apparatuses have become widespread since the introduction of CD (Compact Disc) systems. Initially, digital audio discs (DADs) that play extremely high-quality sound over an hour or more were mainstream, but CD-ROMs that utilize the features of large-capacity and high-speed access as computer peripherals, It has been developed as a CD family, such as CD-I that can interactively use data, video CD with pictures, and CD-R that can record data. Further, in recent years, a DVD (Digital Versatile Disc / Digital Video Disc) family having a larger capacity has been spreading.

  In such an optical disc reproducing apparatus, the rotation control of the optical recording medium is performed by a spindle servo. The spindle servo of the optical recording medium includes a constant linear velocity (CLV) system in which the rotation speed of the optical recording medium changes depending on the position of the optical pickup, and a constant angular velocity (CAV: Constant Angular Velocity) system in which the rotation speed is constant. There is.

  The pit density of the optical recording medium recorded by the CLV method is constant on the inner peripheral side and the outer peripheral side. Although the linear velocity is constant, the angular velocity varies depending on the reading position of the data to be reproduced in the radial direction of the optical recording medium. That is, the rotation speed of the optical recording medium is not constant. Therefore, when reproducing data recorded on the optical recording medium by the CLV method, it is necessary to stabilize the rotation by performing rotation phase control after drawing the rotation of the optical recording medium near the target rotation number.

  The data read from the optical recording medium is determined from 1/0 by the bit clock reproduced by the PLL circuit from the data and is taken in. That is, the data capture is affected by the rotation of the optical recording medium. Control is performed so that the linear velocity of rotation and readout of the optical recording medium is constant, but the linear velocity is disturbed due to the eccentricity or uneven rotation of the optical recording medium, and the digital data data that is taken in as judged by the bit clock The rate is disturbed.

  On the other hand, the system clock is generated based on a clock generated by a crystal oscillator. Data is output from the optical disk reproducing apparatus based on the system clock. If the final data output is not performed at a constant rate of the crystal system clock, distortion occurs in the case of audio data. Therefore, the input data is extracted at a constant rate and subjected to processing such as decoding. .

  In other words, the data capture (input) from the optical recording medium is performed in a situation where there is a possibility that the data rate may fluctuate. Performed at a constant rate. Therefore, a processing system that performs decoding must absorb a difference in data rate (jitter / rotation unevenness) between data acquisition and final data extraction.

  In general, a RAM (Random Access Memory) for storing data is used to secure an area for jitter absorption, and a FIFO (First-In First-Out) operation is performed. Absorbs. A FIFO circuit composed of registers may be placed in the previous stage for storing data, but by using a RAM of an appropriate scale for data storage, a ring buffer area for performing FIFO operation can be secured, and jitter absorption is achieved. FIFO operation can be performed by RAM addressing.

  The FIFO operation is to store (write) the fetched data at successive addresses and start using the data from the “old” address that is different from the previous write address when reading the data for processing. is there.

  For example, when the address is fixed, it is assumed that old data is arranged on the left side and new data is arranged on the right side. For new data, the data write “W” position is sequentially shifted to the right and stored. On the other hand, the data read “R” for processing is located away from “W”, and this also gradually moves to the right. When the data rates of data acquisition and data processing are equal, the phase relationship between “W” and “R” remains the same and both move to the right.

  Also, considering the address as a phase relationship rather than a fixed one, if the data rate of data capture (write) and data processing (read) is the same, the relationship between “W” and “R” remains unchanged and a new frame is created. Each time, each address is incremented by one. When the data rate for data capture changes, for example, when the data rate is slow, the movement of the “W” position is slow and the processing (reading) speed does not change, so “W” and “R” The distance on the address “is closer”. Conversely, when the data rate for data capture increases, the movement of “W” becomes faster, and the distance between “W” and “R” increases.

  Therefore, the phase relationship between data write “W” and data processing “R” varies according to the data rate of capture. Even if the address between “W” and “R” increases or decreases according to the change in the data rate, by performing the FIFO operation, normal processing can be performed even in the case of the data rate change. However, if the capture data rate remains low, the address between “W” and “R” is used up, and “W” and “R” interfere with each other, so that normal processing cannot be performed.

  Thus, it is necessary to perform rotational phase control so as not to cause abnormal processing so that the data rate of data writing “W” follows the data rate of data processing (reading) “R”.

  As shown in FIG. 1, the configuration of the rotation control system of the optical disk reproducing apparatus includes an optical recording medium 2, an optical pickup 3, an RF amplifier 4, a digital decoding processing unit 5, a servo signal processing unit 7, and a spindle motor 8. To do.

  Information is recorded on the optical recording medium 2 by minute holes called pits. The optical pickup 3 reads data from the optical recording medium 2 using laser light. The optical pickup 3 is well known to those skilled in the art. The RF amplifier 4 is also called a head amplifier, and is in principle a transimpedance amplifier. The RF amplifier 4 is often composed of an OP amplifier having good DC characteristics. The digital decoding processing unit 5 performs CIRC decoding, EFM frame synchronization, EFM demodulation, decoding, and the like, and outputs phase difference information that is rotation information of the optical recording medium 2. The servo signal processing unit 7 controls the rotation of the spindle motor 8 based on the phase difference information. The spindle motor 8 is driven to rotate the optical recording medium 2 in response to an input command when the optical recording medium 2 is set.

  A signal read from the optical recording medium 2 by the optical pickup 3 is input to the RF amplifier 4. The signal amplified, impedance-converted, and waveform-shaped by the RF amplifier 4 is input to the digital decoding processing unit 5. The digital decoding processing unit 5 outputs the decoded data and also outputs the rotation information of the optical recording medium 2 to the servo signal processing unit 7. The servo signal processing unit 7 controls the rotation of the spindle motor 8 in response to the input rotation information. Here, the rotation control system of the optical disc playback apparatus has been described. However, the optical disc playback apparatus further includes a CPU that controls the entire optical disc playback apparatus, a playback system, an interface with a host device, and the like.

  Conventionally, as shown in FIG. 2, the digital decoding processing unit 5 includes a PLL circuit 11, an EFM frame synchronization / EFM demodulating unit 12, a CIRC decode controller 14, an interleave RAM 15, a flag RAM 16, frequency dividers 17 and 18, and a phase comparison. And a phase difference counting unit 22.

  A signal read from the optical recording medium 2 is input to the PLL circuit 11 and the EFM frame synchronization / EFM demodulation unit 12. The bit clock output from the PLL circuit 11 is supplied to the EFM frame synchronization / EFM demodulation unit 12. The 8-bit main data decoded from the 16-bit data at the time of modulation and the frame synchronization timing signal WFCK are output from the EFM frame synchronization / EFM demodulation unit 12 to the CIRC decode controller 14. The frame synchronization timing signal WFCK is input to the frequency divider circuit 17.

  The CIRC decode controller 14 uses the interleave RAM 15 and the flag RAM 16 to CIRC decode the input main data and outputs a decode signal S. Between the CIRC decode controller 14 and the interleave RAM 15, and between the CIRC decode controller 14 and the flag RAM 16, data to be written to and read from each RAM is input / output, and a control signal therefor exists. The CIRC decode controller 14 outputs to the frequency divider 18 a timing signal RFCK that indicates the timing for extracting data from the FIFO area of the interleave RAM 15. The signal RFCK_N frequency-divided by N by the frequency divider 18 is supplied to the phase comparator 21 and the phase difference count unit 22, respectively. The CIRC decode controller 14 also outputs a FIFO flow signal FLW indicating the overflow / underflow state of the FIFO area to the phase comparator 21 and the phase difference count unit 22. The phase difference signal X and the phase difference polarity signal D output from the phase comparator 21 are input to the phase difference count unit 22. The phase difference information Y is output from the phase difference count unit 22 and input to the servo signal processing unit 7.

  The function of each component in the above-described configuration will be described. A PLL (Phase Locked Loop) circuit 11 generates a bit clock from a signal read from the optical recording medium 2.

  The EFM frame synchronization / EFM demodulation unit 12 demodulates and outputs synchronization information detection and EFM (Eight to Four Modulation) data. That is, the 24-bit EFM SYNC pattern is detected to determine the head of the 588-bit EFM frame, and one subcode symbol and 32 main data symbols are separated by using 14 bits as one symbol. Since the signal input to the EFM frame synchronization / EFM demodulator 12 is EFM-modulated data, it converts (demodulates) 1-symbol 14-bit data into 8-bit data. When the EFM frame synchronization is established, a signal WFCK indicating the timing of the EFM frame is output. The signal WFCK indicates the timing at which main data is stored in the interleave RAM 15 in synchronization with the bit clock.

  A CIRC (Cross Interleaved Reed-Solomon Code) decode controller 14 inputs a symbol and main data including a subcode synchronization signal SC that has been subjected to synchronization protection, and performs CIRC error correction (C1) on the main data. In addition, the data input / output area of the interleave RAM 15 is address-managed so as to perform a FIFO operation. The CIRC decode controller 14 outputs a signal RFCK indicating the timing for reading data from the FIFO area. The FIFO flow signal FLW is a signal indicating that the FIFO area of the interleave RAM 15 has overflowed or underflowed. In case of overflow or underflow, the FIFO area is forcibly centered in order to re-store data in the interleave RAM 15, and at the same time, the initialization of the phase comparator is instructed.

  The interleave RAM 15 is a work memory used when decoding the CIRC. The interleave RAM 15 is used to solve the CIRC interrib and is also used as a TBC (time axis correction) memory. When storing the input data, the CIRC decode controller 14 manages the memory address of the FIFO operation. The FIFO operation is written based on the timing signal WFCK supplied from the EFM frame synchronization / EFM demodulator 12, and the reading is performed based on the timing signal RFCK generated by the CIRC decode controller 14.

  The flag RAM 16 stores the CIRC error correction result.

  The frequency divider 17 divides the timing signal WFCK by N. The frequency divider 18 divides the timing signal RFCK by N. The frequency division ratio N is determined in advance in consideration of the phase difference detection range, the phase difference information update cycle, and the like.

  The phase comparator 21 compares the phase of the divided timing signal WFCK and the divided timing signal RFCK and outputs a phase difference signal.

  The phase difference count unit 22 outputs phase difference information as the count number of the system clock CLK based on the phase difference signal output from the phase comparator 21.

  Conventional generation of phase difference information will be described. FIG. 3 shows configurations of the phase comparator 21 and the phase difference count unit 22. FIG. 4 is a timing chart showing the operation. As shown in FIG. 3, the phase comparator 21 includes a flip-flop and a logic gate circuit, and a rising edge or a falling edge of an N-divided signal WFCK_N of the timing signal WFCK and an N-divided signal RFCK_N of the timing signal RFCK. Is detected and the phase difference is measured. Here, description will be made assuming that the phase difference of the rising edge is measured.

  The N-divided signal RFCK_N of the timing signal RFCK is sampled by the system clock CLK and becomes the phase comparison input signal A. The N-divided signal WFCK_N of the timing signal WFCK is sampled by the system clock CLK and becomes the phase comparison input signal B. A phase comparison output signal U indicating a phase difference from the rising edge of the phase comparison input signal A to the rising edge of the phase comparison input signal B, and a level from the rising edge of the phase comparison input signal B to the rising edge of the phase comparison input signal A. A phase comparison output signal D indicating the phase difference is generated. Based on the phase comparison output signal U and the phase comparison output signal D, the phase difference signal X and the phase difference polarity signal D are generated, the phase difference is counted by the phase difference counting unit 22, and output as the phase difference information signal Y. The

  FIG. 4A shows an operation example when N = 1 (no frequency division). From the top, phase comparison input signal A, phase comparison input signal B, phase comparison output signal U, phase comparison output signal (phase difference polarity signal) D, phase difference signal X, and phase difference information signal Y are shown. A period in which the phase difference signal X is active (H level) indicates a phase shift. The phase difference polarity signal D indicates the polarity of the phase, that is, which of the signals A and B is advanced.

  Accordingly, the phase difference counting unit 22 measures the period by counting up or counting down depending on the polarity. In FIG. 4, the phase difference information signal Y represents the count number as ± in the vertical axis direction. The positive count indicates that the phase of the phase comparison input signal A is ahead of the phase comparison input signal B, and the negative count indicates that the phase of the phase comparison input signal A is greater than the phase comparison input signal B. Indicates.

  The phase difference information is updated at the time of the rising edge of the phase comparison input signal A. That is, the period of the phase comparison input signal A becomes the update period of the phase difference information. The information sent to the servo processing unit 7 as phase difference information is a numerical value at the time of rising of the phase comparison input signal A, which is the final value of the count value.

  In the period T11, two periods of the phase comparison input signal B are included in one period of the phase comparison input signal A. At this time, the phase difference counting unit 22 only counts from the rising position of the first pulse of the phase comparison input signal B, and the presence of the second pulse does not affect the count. That is, the phase cannot be fully corrected.

  In order to prevent such a situation, it is preferable to divide the input signal and perform phase correction in a long period. FIG. 4B shows an operation example when N = 2 (frequency division by 2). This is a case where the same timing signals RFCK and WFCK are input after being divided by two. The phase comparison input signal A and the phase comparison input signal B are frequency-divided signals by 2 in the case of FIG. 4A and have a longer period. The period T21 in FIG. 4B corresponds to the periods T11 and T12 in FIG. The rising edge of the second pulse in period 11 in FIG. 4 (a) is reflected in the rising edge in period T21 in FIG. 4 (b).

  That is, when using a phase comparator, when trying to obtain a signal having a sufficient length for the phase difference signal that is the output of the phase comparator, a frequency division obtained by dividing the frame period signal with one frame as one period by n. The signal is input to the phase comparator, and the length of the phase difference signal obtained from the phase comparator is counted to obtain phase difference information. In this case, the phase difference information is updated in the period of the n-divided signal that is the input signal of the phase comparator. Therefore, the phase difference information is updated only once every n frame period signals.

  As described above, the generation of the phase difference information by the phase comparator 21 needs to divide the input signal in order to obtain the dynamic range of the phase difference. However, dividing the input signal means that the period for updating the phase difference information becomes longer, and the time response is deteriorated.

  The following techniques are known as techniques relating to the control method and control circuit of the rotational speed.

  According to Japanese Patent Laid-Open No. Hei 4-21968, the disc reproducing apparatus comprises a reading means, a motor, an address detecting means, an access means, a storage means, a data output means, and a motor control means. It is. The reading means reads information from a disk on which information consisting of addresses indicating the positions of data on the disk is recorded at a constant recording speed. The motor rotates the disk. The address detecting means detects an address from the information read by the reading means and outputs it as the current address. When the target address, which is the start address of the data to be reproduced, is specified, the access means starts an access operation for moving the reading position of the reading means so that the current address and the target address coincide with each other. The access operation ends when the address matches. The storage means temporarily stores data to be reproduced output from the reading means. The data output means reads and outputs the data to be reproduced at the same speed as the recording speed immediately after the data to be reproduced is written in the storage means. The motor control means keeps the rotation speed of the motor faster than the rotation speed for realizing the recording speed while the access means is performing the access operation, and the reading means reads the data at the same speed as the recording speed after the access operation is completed. In this way, the rotational speed of the motor is gradually reduced.

  In this disk reproducing apparatus, the motor control means maintains the rotational speed of the motor during the access operation of the access means at a rotational speed faster than the rotational speed for realizing the recording speed, and is stored in the storage means after the access operation is completed. The motor is accelerated or decelerated so that the amount of data is kept within a specified range.

  In the disk reproducing apparatus, after the access operation of the access means is completed, the motor control means decelerates the motor when the amount of data in the storage means exceeds the upper limit of the specified range, and the lower limit of the specified range. The motor is accelerated when the value is lower than, and the drive current is not supplied to the motor when acceleration or deceleration is not performed.

  Further, in this disk reproducing apparatus, before the access means starts the access operation, the rotational speed of the motor is increased to a rotational speed faster than the rotational speed for realizing the recording speed.

  According to Japanese Patent Laid-Open No. 6-208756, a technique relating to a spindle motor control circuit of an optical disk system is known. The spindle motor control circuit of the optical disk system is characterized by comprising spindle motor rotation sensing means, speed error signal generating means, and speed drive voltage generating means. The spindle motor rotation sensing means generates a motor phase frequency corresponding to the rotation of the spindle motor. The speed error signal generating means compares the phase of the phase frequency with preset target speed data, and generates speed error data for the difference. The speed drive voltage generating means generates a speed drive voltage corresponding to the speed error data to drive the spindle motor.

  In this spindle motor control circuit, the speed error signal generating means includes a rising edge detection circuit, a delay unit, a speed error counter, and a speed error signal output unit. The rising edge detection circuit detects the rising edge of the phase frequency and outputs a rising edge detection signal. The delay device delays the detected rising edge detection signal and outputs an error data generation signal. The speed error counter counts the phase frequency input period to a predetermined clock in response to the error data generation signal output from the delay device, and the phase frequency data to be counted is set as the reference target speed data set in advance. Speed error data corresponding to the difference is generated. The speed error signal output unit outputs the speed error data output from the speed error counter to the speed voltage generating means in synchronization with the rising edge detection signal.

  According to Japanese Patent Laid-Open No. 9-115238, a technique relating to a spindle servo circuit of a multi-speed optical disk reproducing apparatus is known. The spindle servo circuit of the multi-speed optical disk reproducing apparatus includes a first phase comparator, a first low-pass filter, a motor driving unit, a high-frequency amplifier, a phase-locked loop circuit unit, and a first frequency divider. It was characterized by comprising. The first phase comparator compares the phases of the reference clock signal and the reproduction frame clock signal and outputs a phase difference signal. The first low-pass filter generates a control signal for the rotation speed of the spindle motor by low-pass filtering the phase difference signal. The motor drive unit drives the rotation of the spindle motor in response to the rotation speed control signal. The high frequency amplifier amplifies a high frequency signal reproduced from an optical disk rotated by a spindle motor, shapes the waveform, and outputs a reproduced data signal. The phase-locked loop circuit unit generates the reproduced bit clock signal from the reproduced data signal, but maintains the generation of the reproduced bit clock signal in the previous state when the speed is higher than a predetermined double speed in response to the rotation speed control signal. The first frequency divider divides the reproduced bit clock signal to generate a reproduced frame clock signal.

  In the spindle servo circuit of the multi-speed optical disk reproducing apparatus, the phase-locked loop circuit unit includes a second phase comparator, a second low-pass filter, a voltage controlled oscillator, and a second frequency divider. It is characterized by comprising. The second phase comparator outputs a phase difference signal by comparing the phases of the reproduced data signal and the reproduced bit clock signal, but the output is in a disabled state when it exceeds a predetermined double speed in response to the rotational speed control signal. Maintained. The second low-pass filter low-pass filters the phase difference signal to generate a control voltage signal. The voltage controlled oscillator generates a predetermined frequency signal in response to the control voltage signal. The second frequency divider divides a predetermined frequency signal to generate a reproduced bit clock signal.

JP-A-4-21968 JP-A-6-208756 JP-A-9-115238

  An object of the present invention is to provide an optical recording medium reproducing device that stably rotates an optical recording medium.

  Another object of the present invention is to provide an optical recording medium reproducing apparatus that performs rotational phase control with excellent temporal response characteristics.

  Another object of the present invention is to provide an optical recording medium reproducing apparatus that performs rotational phase control with excellent frequency response characteristics.

  Another object of the present invention is to provide a FIFO (First-In First-Out) control circuit having a short response time and a wide dynamic range.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in [Best Mode for Carrying Out the Invention]. These numbers and symbols are added to clarify the correspondence between the description of [Claims] and [Best Mode for Carrying Out the Invention]. However, these numbers and symbols should not be used for the interpretation of the technical scope of the invention described in [Claims].

  In an aspect of the present invention, the optical disc reproducing apparatus includes a memory (15) that performs a first-in first-out operation, and the optical recording is performed so that a phase difference between the write timing signal (WFCK) and the read timing signal (RFCK) is reduced. Control the rotation of the medium (2). In the memory (15), data is written based on the write timing signal (WFCK), and data is read based on the read timing signal (RFCK). The write timing signal (WFCK) is generated from a signal extracted from the optical recording medium (2). The read timing signal (RFCK) is generated from a stable oscillation source such as a crystal oscillator. The optical disc reproducing apparatus includes a bank information signal (BI) indicating a deviation amount from a center value of a margin address range up to an address where overflow or underflow occurs in the first-in first-out operation of the memory (15), and the write timing. A phase difference count / phase difference information calculation unit (25) for calculating the phase difference based on the signal and the read timing signal;

  The bank information signal (BI) of the present invention is generated based on a falling edge or a rising edge of the write timing signal (WFCK) and a falling edge or a rising edge of the read timing signal (RFCK).

  The bank information signal (BI) of the present invention is generated by an up / down counter that counts up or down in response to the write timing signal (WFCK) and counts down or up in response to the read timing signal (RFCK). Is done.

  The phase difference count / phase difference information calculation unit (25) of the present invention includes a bank information calculation unit (31) and a phase difference information count unit (32). The bank information calculation unit (31) calculates a first phase difference based on the bank information signal (BI). The phase difference information counting unit (32) calculates a second phase difference from a time difference between falling or rising edges of the read timing signal (RFCK) and the write timing signal (WFCK). The phase difference is calculated by adding the first phase difference and the second phase difference.

  In the present invention, the first phase difference is obtained by multiplying the shift amount and the period of the read timing signal.

  In the present invention, the second phase difference counts a system clock from a falling edge or a rising edge of the read timing signal to a falling edge or a rising edge of the write timing signal immediately before the falling edge or the rising edge. Is required.

  The phase difference count / phase difference information calculation unit (25) of the present invention includes a multiplier, a counter, and an adder. The multiplier calculates the first phase difference. The counter obtains the second phase difference. The adder adds the first phase difference and the second phase difference.

  In another aspect of the present invention, optical recording of an optical disc reproducing apparatus that controls rotation of the optical recording medium (2) so that a phase difference between the write timing signal (WFCK) and the read timing signal (RFCK) is reduced. A medium rotation control method comprising a bank information calculation step and a phase difference information count step. The optical disk reproducing device includes a memory (15) in which data is written based on a write timing signal (WFCK), data is read based on a read timing signal (RFCK), and a first-in first-out operation is performed. The write timing signal (WFCK) is generated from a signal extracted from the optical recording medium (2). The read timing signal (RFCK) is generated from a stable oscillation source such as a crystal oscillator. The bank information calculation step calculates a first phase difference based on a bank information signal (BI) indicating a deviation amount from a center value in the first-in first-out operation of the memory (15). In the phase difference information counting step, a time difference between the rising edge and the falling edge of the signal is calculated based on the write timing signal (WFCK) and the read timing signal (RFCK).

  In another aspect of the present invention, the phase control device includes a FIFO memory (15) and a phase difference calculation unit (25). In the FIFO memory (15), data is written based on the write signal (WFCK), data is read based on the read signal (RFCK), and a first-in first-out operation is performed. The phase difference calculator (25) calculates the phase difference between the read signal (RFCK) and the write signal (WFCK). The phase difference is determined by the amount of deviation from the center value of the FIFO memory (15) in the first-in first-out operation and the writing immediately before the falling edge or rising edge from the falling edge or rising edge of the read signal (RFCK). Based on the falling edge of the signal (WFCK) or the time difference until the rising edge. The phase control device controls the delay amount of the write signal (WFCK) so that the phase difference is reduced.

  ADVANTAGE OF THE INVENTION According to this invention, the optical recording medium reproducing | regenerating apparatus which rotates an optical recording medium stably can be provided.

  In addition, according to the present invention, it is possible to provide an optical recording medium reproducing device that can update phase difference information in a shorter time than the conventional method and performs rotational phase control with excellent temporal response characteristics.

  Furthermore, according to the present invention, it is possible to provide an optical recording medium reproducing device that can respond to a large fluctuation in frequency and performs rotational phase control with excellent frequency response characteristics.

  Another object of the present invention is to provide a first-in first-out (FIFO) control circuit having a short response time and a wide dynamic range.

  The best mode for carrying out the present invention will be described below with reference to the accompanying drawings.

  In reproduction of an optical recording medium, for example, a compact disc (CD), a signal taken out of the optical recording medium also varies in time axis due to influences such as motor rotation jitter and optical recording medium eccentricity. Therefore, the clock reproduced from the signal taken out from the optical recording medium and the binary data are also affected by this. In the case of a music CD, wow and flutter appear if it is played as it is. For this reason, a method is used in which data with time axis fluctuation taken out from the optical recording medium is temporarily stored in the buffer memory, and is taken out from the buffer memory and reproduced at regular time intervals. By reading data from the buffer memory with the clock of the crystal oscillator, it is possible to obtain uniform data at stable time intervals. However, since the time interval stored in the buffer memory varies, the amount of data stored in the buffer memory also varies. Therefore, it is necessary to control the rotation of the motor so that the buffer memory does not become empty (underflow) or overflow (overflow).

  The buffer memory is used as a memory when decoding CIRC. This buffer memory is used to solve the CIRC interrib and is also used as a TBC (time axis correction) memory. The buffer memory also stores a frame synchronization signal of the signal on the optical recording medium and a signal for error correction. Except for these signals, it is also the role of the memory to make connected audio signals of equal intervals, but since this memory is not directly related to the present invention, the details are omitted.

  In the reproduction / CIRC decoding of a compact disc (CD), the data read from the optical recording medium is written to the interleave RAM in synchronization with the bit clock reproduced by the PLL circuit from the EFM signal read from the disc. On the other hand, error correction in CIRC decoding and extraction of decoded data are also performed on the interleave RAM, which is performed in synchronization with a clock obtained by dividing the crystal clock.

  The interleave RAM has a FIFO area for absorbing a difference in data rate between a writing process for reading data from an optical recording medium and storing the data in the interleave RAM, and a reading process by a decoding process. The timing signal indicating the timing when the frame data read from the optical recording medium is written to the interleave RAM is WFCK, and the timing signal indicating the timing for taking out the CIRC decoding process and the decoded data frame is RFCK. In order to prevent the FIFO area from overflowing or underflowing, the phase of the timing signal WFCK and the timing signal RFCK are matched, and the rotation control of the optical recording medium, that is, the rotation phase control is performed so as to center the number of FIFO stages.

  A configuration of the optical disc reproducing apparatus according to the embodiment will be described. Although there is an overlapping part with the description of the above-described conventional technology, it will be described again.

  As shown in FIG. 1, the configuration of the rotation control system of the optical disk reproducing apparatus of the present invention includes an optical recording medium 2, an optical pickup 3, an RF amplifier 4, a digital decoding processing unit 5, a servo signal processing unit 7, and a spindle motor 8. It comprises.

  Information is recorded on the optical recording medium 2 by minute holes called pits. The optical pickup 3 reads data from the optical recording medium 2 using laser light. The optical pickup 3 is well known to those skilled in the art. The RF amplifier 4 is also called a head amplifier, and is in principle a transimpedance amplifier. The RF amplifier 4 is often composed of an OP amplifier having good DC characteristics. The digital decoding processing unit 5 performs CIRC decoding, EFM frame synchronization, EFM demodulation, decoding, and the like, and outputs phase difference information that is rotation information of the optical recording medium 2. The servo signal processing unit 7 controls the rotation of the spindle motor 8 based on the phase difference information. The spindle motor 8 is driven to rotate the optical recording medium 2 in response to an input command when the optical recording medium 2 is set.

  A signal read from the optical recording medium 2 by the optical pickup 3 is input to the RF amplifier 4. The signal amplified, impedance-converted, and waveform-shaped by the RF amplifier 4 is input to the digital decoding processing unit 5. The digital decoding processing unit 5 outputs the decoded data and also outputs the rotation information of the optical recording medium 2 to the servo signal processing unit 7. The servo signal processing unit 7 controls the rotation of the spindle motor 8 in response to the input rotation information. Here, the rotation control system of the optical disc playback apparatus has been described. However, the optical disc playback apparatus further includes a CPU that controls the entire optical disc playback apparatus, a playback system, an interface with a host device, and the like.

  As shown in FIG. 5, the digital decoding processing unit 5 of the present invention includes a PLL circuit 11, an EFM frame synchronization / EFM demodulation unit 12, a CIRC decode controller 14, an interleave RAM 15, a flag RAM 16, a phase difference count / phase difference information calculation. The unit 25 is provided.

  A signal read from the optical recording medium 2 is input to the PLL circuit 11 and the EFM frame synchronization / EFM demodulation unit 12. The bit clock output from the PLL circuit 11 is supplied to the EFM frame synchronization / EFM demodulation unit 12. The 8-bit main data decoded from the 16-bit data at the time of modulation and the frame synchronization timing signal WFCK are output from the EFM frame synchronization / EFM demodulation unit 12 to the CIRC decode controller 14. The frame synchronization timing signal WFCK is input to the phase difference count / phase difference information calculation unit 25.

  The CIRC decode controller 14 uses the interleave RAM 15 and the flag RAM 16 to CIRC decode the input main data and outputs a decode signal S. Between the CIRC decode controller 14 and the interleave RAM 15, and between the CIRC decode controller 14 and the flag RAM 16, data to be written to and read from each RAM is input / output, and a control signal therefor exists. The CIRC decode controller 14 outputs, to the phase difference count / phase difference information calculation unit 25, a timing signal RFCK that indicates the timing at which data is extracted from the FIFO area of the interleave RAM 15 and a bank information signal BI that indicates bank information in the FIFO area. The bank information signal BI is a difference between a write position and a read position in the FIFO area of the interleave RAM 15, and corresponds to increase / decrease in the FIFO area. The phase difference information Y calculated by the phase difference count / phase difference information calculation unit 25 is input to the servo signal processing unit 7.

  In general, the CIRC decode controller 14 is a write frame counter that increments based on a signal WFCK that indicates the timing at which the frame data read from the optical recording medium 2 is written to the interleave RAM 15, the CIRC decoding process, and the timing to extract the decoded frame data A lead frame counter that increments based on RFCK. Access to the interleave RAM 15 is calculated from these frame counter values. The increase / decrease in the difference between the write frame counter and the read frame counter corresponds to the increase / decrease in the FIFO area in the interleave RAM 15. The bank information represents information on the FIFO area.

  The function of each component in the above-described configuration will be described. The PLL circuit 11 generates a bit clock from a signal read from the optical recording medium 2.

  The EFM frame synchronization / EFM demodulation unit 12 demodulates and outputs synchronization information detection and EFM (Eight to Four Modulation) data. That is, the 24-bit EFM SYNC pattern is detected to determine the head of the 588-bit EFM frame, and one subcode symbol and 32 main data symbols are separated by using 14 bits as one symbol. Since the signal input to the EFM frame synchronization / EFM demodulator 12 is EFM-modulated data, it converts (demodulates) 1-symbol 14-bit data into 8-bit data. When the EFM frame synchronization is established, a signal WFCK indicating the timing of the EFM frame is output. The signal WFCK indicates the timing at which main data is stored in the interleave RAM 15 in synchronization with the bit clock.

  The CIRC decode controller 14 inputs main data and performs CIRC error correction (C1) on the main data. Further, the data input / output area of the interleave RAM 15 is address-managed so as to perform a FIFO operation. The CIRC decode controller 14 outputs a signal RFCK indicating the timing for reading data from the FIFO area.

  The interleave RAM 15 is a work memory used when decoding the CIRC. The interleave RAM 15 is used to solve the CIRC interrib and is also used as a TBC (time axis correction) memory. When storing the input data, the CIRC decode controller 14 manages the memory address of the FIFO operation. The FIFO operation is written based on the timing signal WFCK supplied from the EFM frame synchronization / EFM demodulator 12, and the reading is performed based on the timing signal RFCK generated by the CIRC decode controller 14.

  The flag RAM 16 stores the CIRC error correction result.

  The phase difference count / phase difference information calculation unit 25 calculates phase difference information between the timing signal WFCK and the timing signal RFCK based on the timing signals WFCK and RFCK and the bank information signal BI. The phase difference count / phase difference information calculation unit 25 outputs the calculated phase difference information Y to the servo signal processing unit 7.

The phase difference count / phase difference information calculation circuit 25 calculates the amount of deviation from the number of FIFO center stages with reference to the bank information, and counts the edge intervals of the signals RFCK and WFCK within one cycle of the timing signal RFCK, The phase difference information is calculated from these values according to the following equation.
(Deviation amount from FIFO center) × RFCK cycle count number + edge count number (1)

  As shown in FIG. 6, the phase difference count / phase difference information calculation unit 25 includes a bank information calculation unit 31, a phase difference information count unit 32, and an adder 33. The bank information calculation unit 31 calculates the bank component of the phase difference corresponding to the multiplication part of the equation (1) based on the bank information signal BI. The phase difference information counting unit 32 calculates a phase difference that cannot be calculated with bank information based on the timing signals WFCK and RFCK and the system clock CLK. The adder 33 adds the phase differences obtained by the bank information calculation unit 31 and the phase difference information count unit 32 to generate phase difference information Y.

  The concept of the phase difference calculated by the bank information calculation unit 31 and the phase difference information count unit 32 will be described with reference to FIG. The timing signal RFCK is a fixed clock signal generated from the system clock CLK generated by the crystal oscillator. The timing signal WFCK is a variable clock signal generated based on a signal read from the optical recording medium 2. In FIG. 7, the timing reference is the falling position of each signal. As shown in FIG. 7, when the timing signal WFCK falls twice during one cycle of the timing signal RFCK, the bank information signal BI is transferred from “n” to “n” at the first falling position of the timing signal WFCK. It is counted up to “n + 1” and counted up from “n + 1” to “n + 2” at the second falling position. That is, the write address in the FIFO area is counted up twice. The bank information calculation unit 31 calculates the portion up to “n + 1” corresponding to the count up of the FIFO area. The phase difference information counting unit 32 calculates the phase difference from the last falling position of the timing signal WFCK to the falling position of the timing signal RFCK within one cycle of the timing signal RFCK.

  Since the timing signal RFCK is generated from the system clock CLK, one period is expressed as the number of pulses of the system clock CLK. Here, since the timing signal RFCK is generated by dividing the system clock CLK by 144, the phase difference of one cycle is counted as 144. Since the period counted by the phase difference information counting unit 32 is within one cycle of the timing signal RFCK, the phase difference information counting unit 32 is a counter that counts from 0 to 143.

Therefore, the bank information calculation unit 31 is a constant multiplication circuit that receives the bank information signal BI and multiplies the constant 144 representing one cycle. The constant multiplier circuit is well known to those skilled in the art, such as a configuration using a shift circuit and an adder, and a configuration using a multiplier, and thus will not be described in detail here. In order to calculate the phase difference accurately, the bank information is handled differently depending on whether or not the timing signal WFCK falls between the falling edges of the timing signal RFCK. That is, when there is a fall of the timing signal WFCK between the fall of the timing signal RFCK, the bank information is decremented by one and the constant 144 is multiplied, and there is no fall of the timing signal WFCK between the fall of the timing signal RFCK. In this case, the bank information is multiplied by a constant 144. Therefore,
(Bank information) × 144 When there is no falling of the timing signal WFCK (2)
(Bank information-1) × 144 When the timing signal WFCK falls (3)
It becomes.

  Whether the timing signal WFCK falls during the fall of the timing signal RFCK can be determined by the count enable signal CNTE described later.

  As shown in FIG. 8, the phase difference information counting unit 32 includes a flip-flop 41, falling edge detection units 42 and 43, a count enable signal generation unit 45, a counter 47, and a latch circuit 48.

  The system clock CLK is input to the flip-flop 41, the falling edge detectors 42 and 43, the count enable signal generator 45, and the counter 47. The timing signal RFCK is input to the falling edge detection unit 43. Since the timing signal WFCK is an asynchronous signal with respect to the system clock CLK, it is input to the flip-flop 41, sampled (synchronized) with the system clock CLK, and input to the falling edge detector 42 as the signal WFCK '.

  A signal indicating the falling edge of the timing signal WFCK generated by the falling edge detector 42 is input to the set side of the count enable signal generator 45. On the other hand, a signal indicating the falling edge of the timing signal RFCK generated by the falling edge detector 43 is input to the reset side of the count enable signal generator 45. The count enable signal CNTE generated by the count enable signal generation unit 45 is supplied to the enable input of the counter 47 and also supplied to the bank information calculation unit 31.

  The count value CNT counted by the counter 47 is input to the latch circuit 48. The count value CNT is latched at the time of falling of the timing signal RFCK which is the phase difference information update timing, and is output as the phase difference count signal CNTO.

  The operation of the phase difference information counting unit 32 will be described with reference to FIG. When the timing signal RFCK falls at time t1, the falling edge detector 43 detects the fall, and makes the signal RFDP active (H level) between time t2 and time t3 in synchronization with the rise of the system clock CLK. When the signal RFDP becomes active, the latch circuit 48 latches the output CNT of the counter 47. At this time, if the timing signal WFCK does not fall during one cycle of the timing signal RFCK up to the time point t1, the count enable signal generator 45 remains reset, so the count enable signal CNTE is inactive (L level). It is. Therefore, the counter 47 does not perform a count operation, and the count value CNT is “0”. At time t3, the latch circuit 48 latches the count value “0”.

  When the timing signal WFCK falls immediately before time t5, the signal WFCK ′ sampled by the flip-flop 41 falls at time t5 in synchronization with the system clock CLK. The falling edge detector 42 detects a falling edge and activates the signal WFDP from time t6 to time t7.

  When the signal WFDP becomes active, the count enable signal generator 45 is set, and activates the count enable signal CNTE from time t7. When the count enable signal CNTE becomes active (H level), the counter 47 operates and starts counting the system clock CLK. Since the rise of the system clock CLK is earlier than the count enable signal at time t7, the count-up is started from time t8. Therefore, the period from the falling edge of the signal WFCK is measured.

  When the timing signal RFCK falls at time t10, the falling edge detector 43 detects the fall and activates the signal RFDP in synchronization with the system clock CLK from time t11 to time t12. When the signal RFDP becomes active, the count enable signal generation unit 45 and the counter 47 are reset. The reset is reflected in the signal from time t12, and the count enable signal becomes inactive. However, since the rise of the system clock CLK is fast, the counter 47 is reset after being counted up. Therefore, the count value “5” after counting up is latched in the latch circuit 48.

  In this manner, the phase difference information counting unit 32 measures the interval from the falling time t5 of the timing signal WFCK (signal WFCK ′ synchronized with the system clock) to the falling time t10 of the timing signal EFCK. That is, the phase difference information counting unit 32 can measure from the falling edge of the timing signal WFCK immediately before the falling edge of the timing signal RFCK to the falling edge of the timing signal RFCK.

  In the present embodiment, the bank information signal BI is described as being generated by the CIRC decode controller 14 and supplied to the phase difference count / phase difference information calculation unit 25, but based on the timing signals WFCK and RFCK. It is also possible to generate. For example, an up / down counter is used. A signal WFDP indicating the falling edge of the timing signal WFCK output from the falling edge detector 42 is input to the count-up input of the up / down counter, and indicates the falling edge of the timing signal RFCK output from the falling edge detector 43. The signal RFDP is input to the countdown input of the up / down counter. This up / down counter counts up in response to the signal WFDP, counts down in response to the signal RFDP, and becomes a counter indicating bank information. That is, the output of this up / down counter becomes the bank information signal BI. In this case, a FIFO flow signal FLW indicating the overflow / underflow state of the FIFO area in the conventional phase comparison method is used so as not to cause a difference from the bank information or FIFO address managed by the CIRC decode controller 14. Need to be controlled. By providing the bank information signal BI with the up / down counter, the phase difference can be processed only by the phase difference count / phase difference information calculation unit 25. Therefore, the influence of the difference in the configuration of the CIRC decode controller 14 is reduced.

  As described above, the phase difference information can be calculated by the phase difference count / phase difference information calculation unit 25. That is, the bank information calculation unit 31 corresponds to the portion indicated by the number of cycles (bank) in FIG. 7 from the amount of deviation (bank information) from the center value of the FIFO area for absorbing rotation unevenness of the optical recording medium. The phase difference corresponding to the bank is calculated. The phase difference information counting unit 32 counts the edge interval between the timing signal WFCK indicating the timing of writing a frame to the interleave RAM and the timing signal RFCK indicating the timing of reading the frame from the interleave RAM by using the system clock CLK, thereby causing an intra-frame phase difference. Is calculated. The phase difference information counting unit 32 calculates a phase difference corresponding to a count, which is a phase difference within one cycle in FIG. The phase difference information can be calculated by adding the phase difference corresponding to the bank and the in-frame phase difference. Further, the phase difference information can be updated every period of the timing signal RFCK which is also a signal indicating the frame period, for example, every time the timing signal RFCK falls.

  The phase difference information calculated in this way, that is, the optical disc rotation information, is input to the servo signal processing unit 7 and becomes a spindle control signal. The spindle control signal is input to the spindle motor, and the rotation phase of the optical recording medium is controlled.

  FIG. 10 shows a comparison of operation between the method using the conventional phase comparator and the method using the phase difference count / phase difference information calculation unit 25 according to the present invention. FIG. 10 shows the relationship between two cycles of the read timing signal RFCK generated from a stable oscillation source such as a crystal oscillator and the write timing signal WFCK generated based on the clock signal reproduced from the optical recording medium 2. The phase difference is indicated as a phase comparison value according to the conventional method and phase difference information according to the method of the present invention. In the first cycle of the timing signal RFCK, the timing signal WFCK falls twice. In the second cycle of the timing signal RFCK, the timing signal WFCK falls three times. That is, the phase difference is larger in the second period than in the first period.

  In the conventional phase comparator method, counting starts from the first falling edge in the cycle, and the phase comparison value is updated at the falling edge of the timing signal RFCK. The phase comparison value is reset because the phase comparison in the new period is performed together with the update of the phase comparison value. Therefore, the count range in the first cycle of the timing signal RFCK is count 1, the updated phase comparison value is C1, the count range in the second cycle is count 2, and the updated phase comparison value is C2. The position of the first falling edge of the timing signal WFCK is not significantly different between the first period and the second period of the timing signal RFCK. For this reason, there is no significant difference between the phase comparison values of the first period and the second period of the timing signal RFCK. That is, the phase comparison values C1 and C2 are substantially the same value.

  In the system of the present invention, bank information is reflected. In the first cycle of the timing signal RFCK, the timing signal WFCK is included in one cycle or more, and the bank information is counted up from “n” to “n + 1” and further to “n + 2”. The phase difference corresponding to the “n + 1” period is calculated by the bank information calculation unit 31, and the phase difference corresponding to the “n + 2” period is counted by the phase difference information counting unit 32. Therefore, the phase difference information updated in the first cycle of the timing signal RFCK is P1. When the timing signal RFCK falls, the bank information is counted down to “n + 1” and the second period starts. In the second period of the timing signal RFCK, the timing signal WFCK includes three periods. Therefore, the bank information is also counted up to “n + 4”. The phase difference corresponding to the period from bank information “n + 1” to “n + 3” is calculated by the bank information calculation unit 31, and the phase difference corresponding to the period “n + 4” is counted by the phase difference information counting unit 32. Therefore, the phase difference information updated in the second cycle of the timing signal RFCK is P2. Since the bank information is accumulated without being reset even if the period of the timing signal RFCK is exceeded, the phase difference information is larger in the second period than in the first period of the timing signal RFCK. Note that FIG. 10 shows an image of the calculation, and it is not necessary to perform the calculation at the time of change of each signal. The calculation is performed only when the phase difference information such as the falling edge portion of the timing signal RFCK is updated. Good.

  Thus, it can be seen that the phase difference calculation can follow even when the phase difference fluctuation occurs abruptly. Therefore, not only is the time response that the phase difference information can be updated every time the timing signal RFCK falls, but also the frequency response is excellent. That is, the dynamic range of phase difference fluctuation can be widened.

It is a figure which shows the structure of an optical disk reproducing device rotation control system. It is a figure which shows the structure of the conventional digital decoding process part. It is a figure which shows the structure of the conventional phase comparator. It is a timing chart which shows operation | movement of the conventional phase comparator. It is a figure which shows the structure of the digital decoding process part which concerns on embodiment of this invention. It is a figure which shows the structure of the phase difference count and phase difference information calculating part which concerns on embodiment of this invention. It is a timing chart which shows operation | movement of the phase information calculating part which concerns on embodiment of this invention. It is a figure which shows the structure of the phase difference information count part which concerns on embodiment of this invention. It is a timing chart which shows operation | movement of the phase difference information count part which concerns on embodiment of this invention. It is a figure which shows the comparison of the operation | movement in embodiment of this invention, and the operation | movement in a prior art.

Explanation of symbols

2 Optical recording medium 3 Optical pickup 4 RF amplifier 5 Digital decoding processing unit 7 Servo signal processing unit 8 Spindle motor 11 PLL circuit 12 EFM frame synchronization / EFM demodulating unit 14 CIRC decoding controller 15 Interleave RAM
16 Flag RAM
17, 18 Frequency divider 21 Phase comparator 22 Phase difference count unit 25 Phase difference count / phase difference information calculation unit 31 Bank information calculation unit 32 Phase difference information count unit 33 Adder 41 Flip-flops 42, 43 Falling edge detection unit 45 Count enable signal generator 47 Counter 48 Latch circuit

Claims (9)

Data is written based on a write timing signal, data is read based on a read timing signal, and a first-in first-out operation is performed.
The write timing signal is generated from a signal extracted from an optical recording medium,
The read timing signal is generated from a stable oscillation source,
An optical disk reproducing apparatus for controlling rotation of the optical recording medium so that a phase difference between the write timing signal and the read timing signal is reduced,
A bank information signal indicating an amount of deviation from a center value in a margin address range to an address where an overflow or underflow occurs in the first-in first-out operation of the memory;
The write timing signal;
An optical disc reproducing apparatus comprising a phase difference count / phase difference information calculation unit that calculates the phase difference based on the read timing signal. The optical disk reproducing apparatus according to claim 1,
The bank information signal is
A falling edge or a rising edge of the write timing signal;
An optical disk reproducing device generated based on a falling edge or a rising edge of the read timing signal. In the optical disk reproducing apparatus according to claim 1 or 2,
The bank information signal is
Count up or count down in response to the write timing signal,
An optical disk reproducing device generated by an up / down counter that counts down or counts up in response to the read timing signal. In the optical disk reproducing device according to any one of claims 1 to 3,
The phase difference count / phase difference information calculation unit is
A bank information calculation unit for calculating a first phase difference based on the bank information signal;
A phase difference information count unit that calculates a second phase difference from a time difference between a falling edge or a rising edge of the read timing signal and the write timing signal;
An optical disc reproducing apparatus that calculates the phase difference by adding the first phase difference and the second phase difference. The optical disk reproducing apparatus according to claim 4, wherein
The optical disk reproducing apparatus, wherein the first phase difference is obtained by multiplying the deviation amount and the period of the read timing signal. In the optical disk reproducing device according to claim 4 or 5,
The second phase difference counts a system clock based on an interval between a falling edge or a rising edge of the read timing signal and a falling edge or a rising edge of the write timing signal immediately before the falling edge or the rising edge. An optical disk playback device required by In the optical disk reproducing device according to any one of claims 4 to 6,
The phase difference count / phase difference information calculation unit is
A multiplier for calculating the first phase difference;
A counter for obtaining the second phase difference;
An optical disc reproducing apparatus comprising: an adder that adds the first phase difference and the second phase difference. Data is written based on a write timing signal, data is read based on a read timing signal, and a first-in first-out operation is performed.
The write timing signal is generated from a signal extracted from an optical recording medium,
The read timing signal is generated from a stable oscillation source,
An optical recording medium rotation control method of an optical disc reproducing apparatus for controlling rotation of the optical recording medium so that a phase difference between the write timing signal and the read timing signal is reduced,
A bank information calculation step of calculating a first phase difference based on a bank information signal indicating a deviation amount from a center value in the first-in first-out operation of the memory;
An optical recording medium rotation control method for an optical disc reproducing apparatus, comprising: a phase difference information counting step of calculating a time difference between rising edges or falling edges of signals based on the write timing signal and the read timing signal. FIFO memory,
A phase control device comprising: a phase difference calculation unit;
In the FIFO memory, data is written based on a write signal, data is read based on a read signal, and a first-in first-out operation is performed.
The phase difference calculator
The amount of deviation from the center value of the FIFO memory in the first-in first-out operation;
The phase difference between the read signal and the write signal based on the time difference from the falling edge or rising edge of the read signal to the falling edge or rising edge of the write signal immediately before the falling edge or rising edge And
A phase control device that controls a delay amount of the write signal so that the phase difference is reduced.

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