JP2005311335A5 - - Google Patents

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Publication number
JP2005311335A5
JP2005311335A5 JP2005083179A JP2005083179A JP2005311335A5 JP 2005311335 A5 JP2005311335 A5 JP 2005311335A5 JP 2005083179 A JP2005083179 A JP 2005083179A JP 2005083179 A JP2005083179 A JP 2005083179A JP 2005311335 A5 JP2005311335 A5 JP 2005311335A5
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JP
Japan
Prior art keywords
semiconductor layer
forming
mask
impurity
conductivity type
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Application number
JP2005083179A
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English (en)
Japanese (ja)
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JP4713192B2 (ja
JP2005311335A (ja
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Priority to JP2005083179A priority Critical patent/JP4713192B2/ja
Priority claimed from JP2005083179A external-priority patent/JP4713192B2/ja
Publication of JP2005311335A publication Critical patent/JP2005311335A/ja
Publication of JP2005311335A5 publication Critical patent/JP2005311335A5/ja
Application granted granted Critical
Publication of JP4713192B2 publication Critical patent/JP4713192B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2005083179A 2004-03-25 2005-03-23 薄膜トランジスタの作製方法 Expired - Fee Related JP4713192B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005083179A JP4713192B2 (ja) 2004-03-25 2005-03-23 薄膜トランジスタの作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004088848 2004-03-25
JP2004088848 2004-03-25
JP2005083179A JP4713192B2 (ja) 2004-03-25 2005-03-23 薄膜トランジスタの作製方法

Publications (3)

Publication Number Publication Date
JP2005311335A JP2005311335A (ja) 2005-11-04
JP2005311335A5 true JP2005311335A5 (fr) 2008-03-21
JP4713192B2 JP4713192B2 (ja) 2011-06-29

Family

ID=35439683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005083179A Expired - Fee Related JP4713192B2 (ja) 2004-03-25 2005-03-23 薄膜トランジスタの作製方法

Country Status (1)

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JP (1) JP4713192B2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8900970B2 (en) * 2006-04-28 2014-12-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device using a flexible substrate
CN100461433C (zh) 2007-01-04 2009-02-11 北京京东方光电科技有限公司 一种tft阵列结构及其制造方法
JP5429454B2 (ja) * 2009-04-17 2014-02-26 ソニー株式会社 薄膜トランジスタの製造方法および薄膜トランジスタ
KR102333270B1 (ko) 2009-12-04 2021-12-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN102629609A (zh) * 2011-07-22 2012-08-08 京东方科技集团股份有限公司 阵列基板及其制作方法、液晶面板、显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0341732A (ja) * 1989-07-07 1991-02-22 Seiko Epson Corp 半導体装置の製造方法
JP2869893B2 (ja) * 1989-11-07 1999-03-10 カシオ計算機株式会社 半導体パネル
GB9930217D0 (en) * 1999-12-21 2000-02-09 Univ Cambridge Tech Solutiion processed transistors
JP2002185005A (ja) * 2000-12-15 2002-06-28 Matsushita Electric Ind Co Ltd 混成ｔｆｔアレー基板とその製造方法
JP2003124215A (ja) * 2001-10-15 2003-04-25 Seiko Epson Corp パターン形成方法、半導体デバイス、電気回路、表示体モジュール、カラーフィルタおよび発光素子
JP3864413B2 (ja) * 2002-04-22 2006-12-27 セイコーエプソン株式会社 トランジスタの製造方法

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