JP2005311087A - Formation method of aluminum wiring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the formation method of aluminum wiring which realizes formation of aluminum wirings, by filling in opening parts of different sizes, including a fine groove and hole at a normal pressure, and enables the fine groove and hole for wiring to be charged with aluminum by plating. <P>SOLUTION: In the formation method of aluminum wiring, an insulating layer with an opening is provided to a wiring substrate surface; a seed metal layer is deposited at the bottom and a sidewall surface inside the opening and in the surface of the insulating layer; the opening is charged with aluminum or aluminum alloy through plating; and a metal layer, containing aluminum or aluminum alloy other than the inside of the opening, is removed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for forming an aluminum wiring used in a semiconductor integrated circuit device, and particularly to a technique effective for forming a low resistance aluminum wiring.

  In recent years, with the miniaturization of wiring in a semiconductor integrated circuit device, the wiring has been miniaturized to 100 nm or less. For fine wiring of 100 nm or less, it is known that wiring using aluminum is effective in order to realize low resistance.

  However, the process of etching aluminum, which has been conventionally used as a method for forming aluminum wiring, has been a practical problem because it is difficult to reduce the size. Several improvements have been proposed for this issue.

  Japanese Patent Application Laid-Open No. 10-90039 discloses a method of forming a dual damascene wiring by high-pressure reflow.

  Japanese Patent Application Laid-Open No. 11-145143 discloses a method of forming wirings by reflow using chemical vapor deposition (CVD).

  Japanese Patent Application Laid-Open No. 11-307477 discloses a method of forming a wiring by a plating method.

JP-A-10-090039 JP-A-11-145143 Japanese Patent Laid-Open No. 11-307477

  Conventionally, various methods for forming wiring using aluminum have been studied, but each has problems.

  For example, a film that is embedded by reflow requires a film thickness that is three times or more the wiring width, so that it takes a long time to form an extra aluminum film, or a film that uses a CVD method has a low film formation speed. In addition, in the case where reflow is performed at a stage where the film thickness is thin, wirings having different widths and depths cannot be embedded at a time.

In the CVD method or the sputtering method, it is necessary to move the substrate from an apparatus for forming a film under a low pressure condition of 0.1 Pa or less to an apparatus for forming a film under a high pressure condition of about 10 ⁶ Pa used for reflow. is there.

  For this reason, a method of embedding aluminum by a plating method has been studied. However, since aluminum is very easily oxidized, the surface is oxidized to form an insulating film before plating, and it is difficult to perform uniform plating. .

  The present invention lies in that it is possible to form an aluminum wiring by embedding openings of different sizes including fine grooves and holes under normal pressure, and aluminum is formed by plating the fine grooves and holes for wiring. This is a method of forming an aluminum wiring that can be filled.

  Below, the outline | summary of the typical thing of the embodiment of this invention is demonstrated.

  In the method for forming an aluminum wiring according to the present invention, an insulating layer having an opening is provided on the surface of the wiring substrate, a seed metal layer is deposited on the bottom and side wall surfaces and the surface of the insulating layer in the opening, and the inside of the opening is plated or plated by plating. Filling with an aluminum alloy and removing the metal layer containing aluminum or aluminum alloy other than in the opening.

  Further, it is preferable to include a step of depositing a seed metal layer on the surface of the adhesive layer after depositing the adhesive layer on the bottom and side wall surfaces in the opening and the surface of the insulating layer.

  Moreover, it is preferable that the thickness of a seed metal layer is 5-30 nm.

  Furthermore, in the method for forming an aluminum wiring according to the present invention, an insulating layer having an opening is provided on the surface of the wiring substrate, a seed metal layer is deposited on the bottom and sidewall surfaces in the opening and the surface of the insulating layer, and the surface of the seed layer is vacuumed. The seed layer is immersed in a plating solution while being maintained in an inert atmosphere, and the inside of the opening is filled with aluminum or an aluminum alloy by plating, and the metal layer containing aluminum or aluminum alloy other than the inside of the opening is removed. Features.

  When the seed layer is immersed in the plating solution while the surface of the seed layer is maintained in a vacuum or in an inert atmosphere, the thickness of the seed metal layer is preferably 1 to 30 nm.

  Here, the opening has a groove width of 10 to 100 nm or a hole diameter of 10 to 100 nm.

  As a method for manufacturing a semiconductor integrated circuit device, an insulating layer having an opening is provided on the main surface of a semiconductor wafer in which a plurality of circuit element regions are formed on a semiconductor substrate, and the above-described aluminum wiring formation method is provided in the opening It is also possible to manufacture a semiconductor integrated circuit device using

  The aluminum wiring includes a wiring board, an insulating layer having an opening on the surface of the wiring board, a seed metal layer deposited on the bottom and side wall surfaces in the opening, and aluminum or an aluminum alloy filled in the opening by plating. It is characterized by having.

  Furthermore, as a semiconductor integrated circuit device, a semiconductor substrate, a semiconductor wafer having a plurality of circuit element regions formed on the semiconductor substrate, an insulating layer having an opening formed on the main surface of the semiconductor wafer, and an opening It has a seed metal layer deposited on the bottom and side wall surfaces in the part, and aluminum or aluminum alloy filled in the opening by plating.

  According to the present invention, it is possible to form an aluminum wiring by embedding openings of different sizes including fine grooves and holes under normal pressure.

  A feature of the method for forming an aluminum wiring in this embodiment is that a seed layer having an appropriate thickness is formed, or oxidation of the seed layer surface is prevented, and fine grooves and holes formed on the surface of the wiring substrate are formed. The opening is filled with aluminum by a plating method.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Creation of substrate]

(Example 1)
1 and 2 show the procedure for forming the aluminum wiring.

As shown in FIG. 1A, a complementary metal oxide semiconductor is formed on a silicon substrate 1 having a diameter of 300 mm.
(Complimentary metal oxide semiconductor: CMOS) A device was formed (not shown), and an insulating layer 2 of a silicon oxide film (SiO ₂ ) was formed thereon by a plasma CVD method to a thickness of 500 nm.

  The semiconductor element formed on the silicon substrate 1 is not limited to a CMOS device, and may be a bipolar transistor, a resistor, a capacitor element, or the like.

Further, as the insulating layer 2, it can be used SiO _2, SiOF, SiOC, benzocyclobutene (BCB), a methylsiloxane (MSQ), polyarylene ether (PAE) and derivatives thereof.

As shown in FIG. 1B, a connection hole 3 to the semiconductor element was formed in the insulating layer 2 of the silicon oxide film by reactive ion etching (RIE).

  As shown in FIG. 1C, after forming the titanium nitride film 4 in the connection hole 3 by using the CVD method, the connection hole 3 is filled with tungsten 5, and the titanium nitride film and tungsten other than the connection hole 3 are subjected to chemical mechanical polishing ( It was removed by chemical mechanical polishing (CMP).

  As shown in FIG. 1D, after forming an insulating layer with a thickness of 300 nm on the entire surface of the substrate, wiring trenches 6 having a width of 50 nm to 10,000 nm were formed by RIE.

  As shown in FIG. 1 (e), titanium nitride was deposited as the adhesive layer 7 to a thickness of 2 nm and aluminum was deposited as the seed layer 8 to a thickness of 5 nm by the CVD method. Note that these thicknesses are determined based on the thickness of the film formed on the inner side surface of the wiring groove 6.

  As the adhesive layer 7, a metal such as titanium, tantalum, or tungsten or a nitride thereof can be used. Moreover, it can also be used as a multilayer film in which these materials are laminated. The adhesive layer 7 is not necessarily required, but may be deposited to such an extent that the wiring resistance does not become a problem.

In order to prevent the formation of an aluminum oxide film on the surface of the seed layer 8, the substrate was moved into the aluminum plating apparatus after the inside of the CVD chamber was evacuated. When moving from the CVD chamber to the plating apparatus, an inert atmosphere such as nitrogen (N ₂ ) or argon (Ar) may be used.

As shown in FIG. 2 (f), aluminum electroplating was performed on the seed layer 8, and the wiring trench 6 was filled with aluminum 9. The plating solution used was 2.0 mol / dm ^-3 aluminum chloride as the aluminum source, and propylene carbonate containing dichlorobenzene subjected to dehydration treatment as the electrolytic solution. Plating was performed at 500 nm in the range of 20 to 25 ° C.

  In addition, it is preferable to add a substance that reacts at the same potential or a noble potential as the aluminum salt during plating and has a slower diffusion in the plating solution than the aluminum salt. By adding such a substance, it is possible to grow aluminum from the bottom of the opening, and it is possible to realize fine wiring formation without gaps such as voids and seams.

The substrate after plating is heat-treated in a hydrogen (H ₂ ) atmosphere for a period of ₂ to 120 minutes and a substrate temperature of 100 to 500 ° C. in order to promote recrystallization of aluminum and increase the crystal grain size. went.

Instead of a reducing atmosphere of hydrogen (H ₂ ), an inert atmosphere such as nitrogen (N ₂ ) or argon (Ar) or a vacuum may be used.

  As shown in FIG. 2G, the aluminum (including the seed layer) and the adhesive layer other than the wiring trench were removed using the CMP method.

As shown in FIG. 2H, silicon nitride (SiN) 10 was deposited as an etch stop layer on the wiring trench. As the etch stop layer 10, in addition to the silicon nitride film, SiC,
SiCN or the like can be used.

As shown in FIG. 2 (i), an interlayer insulating layer 11 is deposited and a diameter of 50 nm to reach the wiring trench 6.
A 100 nm connection hole 12 (via) and a wiring groove (line) 13 were formed.

  As shown in FIG. 2 (j), these connection holes 12 and wiring grooves 13 were formed by embedding aluminum using the same method as in FIGS. 1 (e) to 2 (h).

(Example 2)
As shown in FIG. 3, a substrate was prepared in the same manner as in Example 1 except that no adhesive layer was formed and the thickness of the seed layer was 10 nm.

(Example 3)
A substrate was prepared in the same manner as in Example 1 except that the atmosphere in which the seed layer was formed and then plated was in a vacuum.

Example 4
A substrate was prepared in the same manner as in Example 1 except that the adhesive layer was not formed and that the atmosphere for transporting the seed layer from formation to plating was an argon (Ar) gas atmosphere.

(Example 5)
A substrate was prepared in the same manner as in Example 1 except that the atmosphere in which the seed layer was formed and then plated was in a vacuum, and that the film thickness of the seed layer was 1 nm.

(Comparative Example 1)
A substrate was prepared in the same manner as in Example 1 except that the seed layer had a thickness of 1 nm.

(Comparative Example 2)
A substrate was prepared in the same manner as in Example 1 except that no adhesive layer was formed and the seed layer had a thickness of 1 nm.

(Comparative Example 3)
A substrate was prepared in the same manner as in Example 1 except that the seed layer had a thickness of 40 nm.

(Comparative Example 4)
A substrate was prepared in the same manner as in Example 1 except that the atmosphere in which the seed layer was formed and then plated was in a vacuum, and the thickness of the seed layer was 40 nm.

[Evaluation of substrate]
Hereinafter, the evaluation method of the aluminum wiring concerning the Example of this form is explained.

  The evaluation items were two items regarding the ratio of voids present in the holes after the aluminum was buried and the in-plane uniformity of the aluminum plating film thickness.

  About the ratio in which a void exists, it evaluated from the result of having observed the cross section of the plating film with SEM (scanning electron microscope). The substrate after the completion of plating was processed by FIB (Focused Ion Beam), the cross section was observed for 1000 holes of Φ100 nm, the ratio of occurrence of voids was examined, and the embedding in the aluminum wiring was evaluated.

  The in-plane uniformity of the substrate was evaluated by measuring the sheet resistance of the plating film after aluminum plating by measuring the resistance of the four short needles and measuring 49 points in the plane.

  These results are summarized in Table 1.

  In Examples 1 and 2, since the atmosphere for transporting the substrate from the formation of the seed layer to the plating was in the air, the aluminum in the seed layer was oxidized to become an insulating aluminum oxide. However, since the seed film thickness was appropriately set to 5 nm, the oxide film could be reduced during plating, the void generation rate was very low, and the in-plane uniformity of the plating film thickness was good.

  On the other hand, in Comparative Examples 1 and 2, since the seed layer was as thin as 1 nm, the seed layer was entirely made of aluminum oxide. For this reason, in Comparative Example 1, since the adhesive layer having high resistance is used as the power feeding layer in order to perform plating, uniform plating cannot be performed, a large number of voids are generated, and the in-plane uniformity of the film thickness is low. In Comparative Example 2, plating could not be performed at all because no current could flow.

  In Comparative Example 3, since the seed layer was as thick as 40 nm, the holes were almost filled with the seed layer, making it difficult to fill by plating. For this reason, the generation ratio of voids was high.

  From the above, by setting the film thickness of the seed layer to 5 to 30 nm, the oxide film generated when the substrate is transported in the atmosphere can be reduced during plating, and there is no adverse effect on embedding, so there is no void. The advantage of this embodiment that plating with good in-plane uniformity of the plating film thickness can be performed has been clarified.

  In Example 4, it was possible to prevent oxidation of the aluminum surface of the seed layer by setting the atmosphere for transporting the substrate from the formation of the seed layer to plating to an inert argon gas atmosphere. For this reason, no void was observed during the plating, and the in-plane uniformity of the plating film thickness was further improved.

  In Example 5, although the thickness of the seed layer was reduced to 1 nm, the surface of the seed layer was not oxidized because the substrate transfer atmosphere from the formation of the seed layer to plating was evacuated, and good plating was possible. Met.

  In Comparative Example 4, since the seed layer was thickened to 40 nm, the holes were almost filled with the seed layer, making it difficult to fill by plating. For this reason, the generation ratio of voids was high.

  From the above, it is possible to prevent oxidation of the aluminum surface of the seed layer by setting the substrate transport atmosphere from the formation of the seed layer to plating to an inert argon gas atmosphere and the seed layer thickness of 1 to 30 nm. The advantage of this embodiment that it was possible to perform plating with no voids and good in-plane uniformity of the plating film thickness was clarified.

  Conventionally, it has been considered that copper wiring is effective because copper has a lower resistance than aluminum, and it has been difficult to reduce the size in the process of etching aluminum.

  When copper is used as the wiring material, a damascene process is used. In the damascene process, grooves and holes are formed in the insulating layer, a barrier layer for preventing copper diffusion and a copper seed layer that serves as a power feeding layer for electroplating are formed. Wiring was formed by removing excess copper by mechanical polishing.

  In this damascene process, a single damascene process in which wiring grooves and holes for interlayer connection for connecting wires and wirings are embedded in different processes, and a dual in which wiring grooves and holes for interlayer connection are simultaneously embedded There is a damascene process. By using the dual damascene process, the number of steps can be reduced. Further, a finer copper wiring can be formed by the damascene process, and the copper wiring is put into practical use.

  However, considering the current situation in which wiring is being miniaturized to 100 nm, it has become a problem that resistance cannot be lowered even when copper wiring is used. That is, when copper wiring is used, it is necessary to completely cover the periphery of copper with a barrier layer in order to prevent copper diffusion. This is because copper easily diffuses in the insulating layer and reaches the element portion to deteriorate the performance of the element.

  Materials such as Ta, Ti, W and their nitrides used as this barrier layer have a high resistance and increase the wiring resistance. In order to prevent copper diffusion, these barrier layers need to have a certain thickness. For this reason, even if copper is used as a wiring material, the resistance of the barrier layer is high, so that the resistance of the entire wiring becomes high.

  Moreover, since the proportion of the barrier layer in the entire wiring increases as the miniaturization progresses, the resistance rise becomes more problematic as the wiring becomes finer. Furthermore, a problem appears that the specific resistance of the wiring material itself increases.

  According to the embodiment of the present embodiment, it is possible to solve such technical problems in copper wiring. That is, the wiring using aluminum does not necessarily require a barrier layer, and the resistance increase due to the barrier layer is unlikely to be a problem. Moreover, the resistance of the aluminum wiring of 100 nm or less can be equivalent to copper.

  Therefore, it is necessary to form a seed layer having an appropriate thickness in the aluminum wiring, and it is necessary to prevent the oxidation of the surface of the seed layer and to perform aluminum plating. By doing so, the inside of the opening formed in the insulating layer can be completely filled with aluminum.

  In addition, since a fine wiring having no gap such as a void or a seam can be formed, the performance of a high-density semiconductor integrated circuit device and its manufacturing yield can be improved.

Explanatory drawing of the first half part which showed the formation method of aluminum wiring. Explanatory drawing of the latter half part which showed the formation method of aluminum wiring. Explanatory drawing which showed a part of formation method of the aluminum wiring which does not attach an adhesion layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Insulating layer 3, 12 ... Connection hole, 4 ... Titanium nitride film, 5 ... Tungsten, 6, 13 ... Wiring groove, 7 ... Adhesive layer, 8 ... Seed layer, 9 ... Aluminum, 10 ... Etch stop layer, 11... Interlayer insulating layer.

Claims (10)

An insulating layer having an opening is provided on the surface of the wiring board,
Depositing a seed metal layer on the bottom and sidewall surfaces in the opening and on the surface of the insulating layer;
Filling the opening with aluminum or aluminum alloy by plating,
A method for forming an aluminum wiring, comprising removing a metal layer containing aluminum or an aluminum alloy other than in the opening.   2. The aluminum wiring according to claim 1, further comprising a step of depositing the seed metal layer on the surface of the adhesive layer after depositing an adhesive layer on the bottom and sidewall surfaces in the opening and on the surface of the insulating layer. Forming method.   3. The method of forming an aluminum wiring according to claim 1, wherein the seed metal layer has a thickness of 5 to 30 nm. An insulating layer having an opening is provided on the surface of the wiring board,
Depositing a seed metal layer on the bottom and sidewall surfaces in the opening and on the surface of the insulating layer;
The seed layer is immersed in a plating solution while maintaining the surface of the seed layer in a vacuum or in an inert atmosphere, and the opening is filled with aluminum or an aluminum alloy by plating,
A method for forming an aluminum wiring, comprising removing a metal layer containing aluminum or an aluminum alloy other than in the opening.   5. The aluminum wiring according to claim 4, further comprising a step of depositing the seed metal layer on the surface of the adhesive layer after depositing an adhesive layer on the bottom and side wall surfaces in the opening and the surface of the insulating layer. Forming method.   6. The method of forming an aluminum wiring according to claim 4, wherein the seed metal layer has a thickness of 1 to 30 nm.   7. The method for forming an aluminum wiring according to claim 1, wherein the opening has a groove width of 10 to 100 nm or a hole diameter of 10 to 100 nm.   An insulating layer having an opening is provided on an upper portion of a main surface of a semiconductor wafer having a plurality of circuit element regions formed on a semiconductor substrate, and the aluminum wiring forming method according to claim 1 is used in the opening. A method of manufacturing a semiconductor integrated circuit device, comprising manufacturing a semiconductor integrated circuit device.   A wiring board; an insulating layer having an opening on the surface of the wiring board; a seed metal layer deposited on the bottom and side wall surfaces in the opening; and aluminum or an aluminum alloy filled in the opening by plating. Features aluminum wiring. A semiconductor substrate, a semiconductor wafer having a plurality of circuit element regions formed on the semiconductor substrate, an insulating layer having an opening formed on an upper portion of the main surface of the semiconductor wafer, and bottom and sidewall surfaces in the opening A semiconductor integrated circuit device comprising: a seed metal layer deposited on the substrate; and aluminum or an aluminum alloy filled in the opening by plating.

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