JP2010278330A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a coating property of a barrier metal. <P>SOLUTION: A semiconductor device includes an insulating film formed on a cap insulating film 1d, a wiring groove formed in the insulating film, a via hole formed in a bottom surface of the wiring groove, and a barrier metal film covering at least a sidewall of the via hole. The via hole includes a plurality of holes differing in diameter, wherein the plurality holes are connected along the thickness to decrease in diameter downward, and a plane substantially parallel with the cap insulating film is provided at a connection portion of the plurality of holes. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  With the progress of miniaturization and integration of semiconductor devices, the miniaturization of multilayer wiring formed on the upper layer of a transistor formed on a silicon substrate is rapidly progressing. The multilayer wiring includes a wiring connecting the transistor elements in the horizontal direction and a through via connecting the wiring in the vertical direction. After 65 nm node, use copper (Cu) as a wiring material, and use a SiOCH film mainly composed of silicon (Si), carbon (C) and oxygen (O) having a low dielectric constant as a material for an inter-wiring insulating film. Has become commonplace. When forming a wiring pattern of copper, a dual damascene structure in which the wiring and the via are simultaneously formed is most popular.

  In the via first dual damascene processing method in which the dual damascene structure is formed first from the through via, as shown in FIG. 14A, a via etching stopper film 401, an inter-via insulating film 402, and a wiring are formed on the lower wiring 140. The etching stopper film 403 and the inter-wiring insulating film 404 are sequentially formed, and the wiring groove 141 and the via 142 are sequentially processed up to the respective etching stopper films. Thereafter, the via etching stopper film 401 and the wiring etching stopper film 403 are simultaneously removed to form a dual damascene structure. The via etching stopper film 401 is a cap insulating film having a Cu barrier property. In the via first dual damascene processing method, the via etching stopper film 401 and the wiring etching stopper film 403 are removed at the same time. Therefore, a cap insulating film is often used also for the wiring etching stopper film 403.

In general, a cap insulating film is a silicon carbide film (SiC) mainly composed of silicon (Si) and carbon (C), a silicon carbonitride film (SiCN film) obtained by adding nitrogen to SiC, and a silica carbon obtained by adding oxygen. A composite film (SCC (Silica-carbon-composite) film) or the like is used. Further, when the inter-wiring insulating film is a low-k film having a high C concentration, a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film) is laminated on the cap insulating film in order to improve the etching stop property. Sometimes. Conversely, for the purpose of preventing oxidation at the Cu interface, the cap insulating film may be grown on an extremely thin SiN film having a thickness of about 5 nm to 10 nm.

  The wiring etching stopper film can also protect the periphery of the via opening. Thereby, the via can maintain a vertical shape without being deformed during the processing of the wiring groove. For this reason, a dual damascene shape having vertical vias has been common.

  In recent years, with the miniaturization of devices, the application of a low-k film to a wiring interlayer film has been studied to reduce parasitic capacitance. However, since the low-k film has a low film strength and a high coefficient of thermal expansion, there is a concern that the reliability of via wiring affected by stress such as electromigration (EM) or stress-induced voids (SiV) may be affected. In general, the stress is considered to affect the movement and growth of microvoids existing in the Cu wiring, and it is considered that when a low-k material is used, the growth of voids is accelerated for the reasons described above. Therefore, it is effective to reduce the micro voids in the Cu wiring by improving the Cu embedding property or the like in order to suppress the deterioration of the via wiring reliability due to the application of the low-k material. In other words, high Cu embeddability without microvoids is strongly required for the application of the low-k film. However, in reality, the difficulty of embedding Cu in a vertical-shaped via is increasing due to miniaturization of devices.

  In addition, as part of the parasitic capacitance reduction, it is required to eliminate the wiring etch stopper film (stopperless). However, as shown in FIG. 14B, the stopper-less structure easily causes a shoulder drop at the opening of the via 142 and a taper shape of the sidewall of the via 142. Patent Document 1 proposes a partially tapered via wiring in which only the vicinity of the opening of the via is partially tapered in order to eliminate the wiring etching stopper film and improve the Cu embedding property. Partially tapered vias have an apparent aspect ratio that is smaller than vertical vias, and therefore can be expected to improve Cu embedding properties compared to vertical vias.

  In Patent Document 2, the via sidewall angle is prevented from becoming a negative angle. As a result, it is described that there is no shape that causes stress concentration on the via sidewall, stress migration is reduced, and the reliability of the wiring is further increased. Patent Document 2 adopts a configuration having at least two maximum values in the via sidewall angle and having a minimum value between these maximum values. As a result, the diameter of the via hole is rapidly increased in the middle portion of the via sidewall, and the substantial aspect ratio of the via hole is smaller than that of the simple tapered shape. Therefore, it is described that the embedding property of metal is improved.

JP 2008-47582 A JP 2004-356521 A

C. Hashimoto et al, “New taper-etching technology using oxygen ion plasma”, J. Am. Vac. Scl. Technol. B 8 (3), 1990, 529-532.

  However, the technique described in the above document has a problem that it is not suitable for a resputtering process for improving the barrier metal coverage. In the resputtering process, the barrier metal film formed on the bottom surface of the wiring groove and the bottom surface of the via is resputtered by ion bombardment using argon (Ar) ions, etc. This is a process for improving the barrier metal coverage by re-adhering. Since the barrier metal resputtering speed depends on the incident angle of ions, the amount of resputtering varies depending on the taper angle of the side wall. For this reason, the barrier metal is sputtered on the side wall of the tapered via, and there is a portion where the barrier metal cannot be reattached. Therefore, in the above conventional technique, the coverage of the barrier metal film cannot be improved by the resputtering process.

According to the present invention,
An insulating film formed on the ground,
A wiring groove formed in the insulating film;
A connection hole formed in the bottom surface of the wiring groove;
A barrier metal film covering at least the side wall of the connection hole;
Have
The connection hole is composed of a plurality of holes having different diameters,
The plurality of holes are connected in the depth direction so that the diameter decreases toward the bottom,
A semiconductor device is provided that has a plane substantially parallel to the base at a connection portion of the plurality of holes.

Moreover, according to the present invention,
Forming an insulating film;
Forming a connection hole penetrating the insulating film;
Filling the connection hole with a filler;
Forming a mask covering the opening of the connection hole on the insulating film;
A first etching step of removing a part of the mask and the filler and exposing a part of a side wall of the connection hole;
Removing the insulating film from the exposed sidewall of the connection hole to form a wiring groove and a connection hole;
Covering at least the side wall of the connection hole with a barrier metal film;
Including
In the second etching step,
A plurality of holes having different diameters from the bottom surface of the wiring groove are connected in the depth direction so that the diameter decreases downward, and the connection hole is formed at a connection portion of the plurality of holes. A method of manufacturing a semiconductor device is provided that forms a plane substantially parallel to the surface.

  According to the present invention, the plurality of holes having different diameters are connected in the depth direction so that the diameter is reduced downward, and the connection portion includes the connection hole having a surface substantially parallel to the base. Thereby, the barrier metal can be resputtered on the horizontal surface of the connection hole, and the barrier metal can be reattached to the side wall of the connection hole. Therefore, the barrier metal coverage on the side wall of the connection hole can be improved.

  According to the present invention, the barrier metal coverage on the side wall of the connection hole can be improved.

It is sectional drawing which shows the semiconductor device which concerns on embodiment. It is a figure explaining the manufacturing method of the semiconductor device which concerns on embodiment. It is a figure explaining the manufacturing method of the semiconductor device which concerns on embodiment. It is a figure explaining the manufacturing method of the semiconductor device which concerns on embodiment. It is a figure which shows the manufacturing apparatus used with the manufacturing method of the semiconductor device which concerns on embodiment. It is a figure explaining the manufacturing method of the semiconductor device which concerns on an Example. It is a figure explaining the manufacturing method of the semiconductor device which concerns on an Example. It is a figure explaining the manufacturing method of the semiconductor device which concerns on an Example. It is a figure explaining the manufacturing method of the semiconductor device which concerns on an Example. It is a figure which shows the result of having observed the cross section of the via wiring shape of an Example with TEM (transmission electron microscope). It is a figure which shows the probability cumulative distribution of the via resistance of the via wiring of an Example. It is a figure which shows the result of the defect number of the large-scale via chain in the via wiring of an Example. It is a figure which shows the result of the reliability evaluation with respect to the stress cause void (Stress-Induced Voiding, SIV) of the via wiring of an Example. It is a figure which shows the conventional via wiring. It is a correlation diagram of the etching rate by oxygen ion and an ion incident angle.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

FIG. 1 is a cross-sectional view showing the semiconductor device of this embodiment. This semiconductor device includes an insulating film 2a formed on a cap insulating film 1d as a base, a wiring groove 6 formed in the insulating film 2a, and a via hole (connection hole) 7 formed in the bottom surface of the wiring groove 6. And a barrier metal film 2b covering the sidewalls of the wiring trench 6 and the via hole 7. The via hole 7 includes an upper via hole 5 and a lower via hole 3 having different diameters. The upper via hole 5 and the lower via hole 3 are connected in the depth direction downward in this order. The diameter of the lower via hole 3 is (d ₁ ), which is smaller than the diameter of the upper via hole 5 (opening diameter d _2a > bottom diameter d _2b ). At the connection portion between the lower via hole 3 and the upper via hole 5, a surface 4 substantially parallel to the cap insulating film 1d is formed.

  More specifically, in the semiconductor device of this embodiment, the lower layer Cu wiring structure 1 and the upper layer Cu wiring structure 2 formed by the damascene method are formed in this order on a silicon substrate (not shown). The semiconductor substrate is a substrate on which a semiconductor device is configured, and examples thereof include a single crystal silicon substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin film transistor), and a substrate for manufacturing a liquid crystal.

  The lower layer Cu wiring structure 1 includes an insulating film 1a, a lower Cu wiring 1c embedded in the insulating film 1a, a barrier metal film 1b covering the side and bottom surfaces of the lower Cu wiring 1c, and a cap insulating film 1d covering the lower Cu wiring 1c. It consists of. The upper-layer Cu wiring structure 2 includes an insulating film 2a, an upper Cu wiring 2c embedded in the insulating film 2a, a barrier metal film 2b that covers the side wall and the bottom surface of the upper Cu wiring 2c, and a cap that covers the upper Cu wiring 2c. It consists of an insulating film 2d.

The connection portion between the lower via hole 3 and the upper via hole 5 may be provided with a surface 4 substantially parallel to the cap insulating film 1d. It is more preferable to have a horizontal plane composed of an inclination. The width of the horizontal plane 4 can be 5 nm or more. In other words, when the difference between the diameter d _2b of the bottom surface of the upper via hole 5 and the diameter d ₁ of the lower via hole 3 is Δd (d _2b −d ₁ ), Δd can be 5 nm or more. The upper limit of Δd can be 100 nm or less.

  As shown in FIG. 1, the side wall of the upper via hole 5 may be formed in a tapered shape. In this case, the inclination angle of the side wall of the upper via hole 5 is set to 60 ° to 90 °. Note that the inclination angle of the side wall referred to in the present embodiment is defined as 0 ° in a direction parallel to the base cap insulating film 1d. When the depth of the upper via hole 5 is D, D can be 20% or less of the entire depth of the via hole 7. For example, 20 nm ≦ D ≦ 40 nm can be satisfied, and 0.8 ≦ D / Δd ≦ 8 is preferably satisfied.

  Further, the side wall of the upper via hole 5 may be formed in a staircase shape. In this case, it is possible to adopt a multi-stage structure by a combination of a horizontal plane having an inclination angle of 0 ° to 10 ° and an inclined surface having an inclination angle of 60 ° to 90 °.

  The side walls of the wiring trench 6 and the lower via hole 3 are preferably formed in a vertical shape, which is acceptable if the inclination angle is in the range of 60 ° to 90 °, but more preferably 80 ° to 90 °.

  The bottom surface of the lower via hole 3 is embedded in the lower Cu wiring 1c by a resputtering process. In other words, the anchors are dug into the lower layer Cu wiring 1c.

  In the present embodiment, the lower Cu wiring 1c is covered with a cap insulating film 1d. The upper Cu wiring 2c is covered with a cap insulating film 2d. The cap insulating film is formed on the upper surface of the Cu wiring and has a function of preventing Cu oxidation and Cu diffusion into the insulating film, and a role as an etching stop layer during processing. The cap insulating films 1d and 2d can contain silicon (Si) and carbon (C) as main components. For example, a SiN film, a SiCN film, a SiC film, or the like can be used. By using the low dielectric constant cap insulating film, the transmission delay of the wiring signal can be improved. The cap insulating film is also called a barrier insulating film.

The insulating film 2a is a film (interlayer insulating film) for insulating and separating the upper Cu wiring 2c, and the insulating film 1a is a film for insulating and separating the lower Cu wiring 1c. When the insulating films 1a and 2a are low dielectric constant insulating films, it is possible to reduce the capacitance between the multilayer wirings connecting the semiconductor elements. For example, the insulating films 1a and 2a can be films mainly composed of Si, C, and oxygen (O), and have a relative permittivity higher than that of a silicon oxide film (relative permittivity 3.9 to 4.5). A low material can be used. Examples of such a low dielectric constant insulating film include a porous insulating film in which a silicon oxide film is made porous to reduce the relative dielectric constant, and specifically, the carbon / silicon ratio (C / Si) in the film. SiOCH film having a thickness greater than 1, HSQ (Hydrogen Silsesquioxane) film, SiOC (for example, Black Diamond ^™ , CORAL ^™ , Aurora ^™ ) film. The porous insulating film preferably has a plurality of independent pores, and more preferably has an average pore diameter of 0.8 nm or less. More specifically, as the insulating films 1a and 2a, a structure having a trimeric cyclic siloxane structure and an unsaturated or saturated carbon chain being bonded to silicon constituting the cyclic siloxane structure is adopted. Can do.

  The lower Cu wiring 1c and the upper Cu wiring 2c are mainly composed of Cu, but a metal element other than Cu may be included in the member made of Cu in order to improve the reliability of the wiring. Further, a metal element other than Cu may be formed on the upper surface or side surface of the Cu wiring.

  The barrier metal films 1b and 2b are conductive films having a barrier property against the metal elements constituting the wiring. The barrier metal film 2b covers the side and bottom surfaces of the upper Cu wiring 2c, and prevents the metal element (Cu) constituting the wiring from diffusing into the insulating film 2a and the lower Cu wiring structure 1. As the barrier metal films 1b and 2b, for example, a refractory metal such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), tungsten carbonitride (WCN), nitrides thereof, or a laminated film thereof Is used.

  Next, an example of the method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 2-4 show cross-sectional views.

  First, as shown in FIG. 2A, a lower layer Cu wiring structure 201 is formed using a general damascene process. That is, the lower Cu wiring 201c is embedded in a groove formed in the insulating film 201a in advance, and excess metal other than in the groove is removed by, for example, a CMP method (Chemical Mechanical Polishing) or the like. Next, the side surface and outer periphery of the lower Cu wiring 201c are covered with a barrier metal film 201b, and the upper surface of the lower Cu wiring 201c is covered with a cap insulating film 201d. The CMP method is a method of flattening the unevenness of the wafer surface that occurs during the multilayer wiring formation process by polishing the wafer by bringing it into contact with a rotating polishing pad while flowing a polishing liquid on the wafer surface. In the wiring formation by the damascene method, in particular, after a metal is buried in the wiring groove or via hole, it is used for removing a surplus metal portion and obtaining a flat wiring surface.

  Next, an insulating film 202 is formed on the lower Cu wiring 201c. Here, a process for forming a SiOCH film as the insulating film 202 will be described as an example. An example of the SiOCH film is a film having a composition ratio of Si: O: C = 1: 0.9: 2.7. A SiOCH film having a large C content has high resputtering resistance, and can suppress deformation of the wiring structure, an increase in the dielectric constant of the Low-k film, and the like. The SiOCH film can be formed by a plasma CVD (Chemical Vapor Deposition) method. The plasma CVD method is, for example, a method in which a gaseous raw material is continuously supplied to a reaction chamber under reduced pressure, a molecule is excited by plasma energy, and a continuous film is formed on a substrate by a gas phase reaction or a substrate surface reaction. It is a technique to form.

  FIG. 5 shows an outline of an apparatus used for forming a high C concentration SiOCH film. The reservoir 301 is a container filled with a monomer raw material that becomes the insulating film 202. The raw material pressure feeding unit 302 is a part that pressurizes the raw material in the reservoir 301, and an inert gas such as helium (He) is used as the pressure feeding gas. The carrier gas supply unit 303 is a part that supplies an inert gas such as He that transports the monomer raw material as a carrier gas. The liquid mass flow 304 is a device that controls the flow rate of the raw material to be supplied. The gas mass flow 305 is a device that controls the flow rate of the carrier gas. The vaporizer 306 is an apparatus for vaporizing the monomer raw material. The reactor 307 is a processing chamber in which a raw material that has become a gas is deposited by plasma polymerization. The RF power source 309 is a device that supplies electric power for converting the monomer raw material that has become gas and the carrier gas into plasma. The substrate 308 is a semiconductor substrate. The exhaust pump 310 is an apparatus that exhausts the raw material gas and the carrier gas introduced into the reactor 307.

The monomer raw material is sent out from the reservoir 301 by the pressurized gas from the raw material pressure feeding unit 302, and the flow rate is controlled by the liquid mass flow 304. On the other hand, carrier gas is supplied from the carrier gas supply unit 303, and the flow rate is controlled by the gas mass flow 305. The raw material and the carrier gas are mixed immediately before the vaporizer 306 and introduced into the vaporizer 306. A heated heater block (not shown) exists in the vaporizer 306, where the liquid monomer material is vaporized and introduced into the reactor 307. In the reactor 307, by applying high frequency power of 13.56 MHz, the vaporized monomer raw material and carrier gas are turned into plasma, and a high C concentration SiOCH film is formed on the substrate 308 by plasma polymerization. The raw material monomer is preferably 0.1 g / min or more and 10 g / min or less, more preferably 2 g / min or less. The flow rate of the carrier gas is preferably 0.05 × 10 ³ sccm or more and 5 × 10 ³ sccm or less, more preferably 2 × 10 ³ sccm or less. The pressure in the reactor 307 is preferably 0.13 to 1.3 kPa. The output of the RF power source is preferably 2 kW or less, more preferably 1 kW or less.

  The high C concentration SiOCH film can be formed, for example, from a raw material having a cyclic organic silica structure and represented by the following general formula (1). Among these, a material having a structure represented by the following formula (2) or (3) is particularly preferable as a raw material having a cyclic organic silica structure.

In formula (1), R ₁ and R ₂ are an unsaturated carbon compound or a saturated carbon compound (alkyl group), and the unsaturated group is any of a vinyl group, a propenyl group, an isopropenyl group, a methylpropenyl group, and a dimethylpropenyl group. The alkyl group is any one of a methyl group, an ethyl group, a propyl group, an isopropyl group, and a butyl group. R1 and R2 may be the same or different.

Returning to FIG. 2A, an SiO ₂ film is formed as a hard mask 203 on the insulating film 202 by a plasma CVD method. A hard mask refers to an insulating film that serves as a protective layer to be laminated on an interlayer insulating film when it is difficult to perform direct CMP due to a decrease in strength due to the lower dielectric constant of the interlayer insulating film. Next, a via hole (through-hole via) 204 that penetrates the insulating film 202 is formed with the hard mask 203 left.

  Next, as shown in FIG. 2B, after filling the via hole 204 with a resist (filler) 205, a multilayer mask (low-temperature oxide film 206, antireflection film 207, resist 208) covering the opening of the via hole 204. Is formed on the insulating film 202. A trench groove pattern 209 is formed by a lithography process using the multilayer mask (FIG. 2B).

Next, as shown in FIGS. 2C and 2D, a part of the multilayer mask and the resist 205 is removed and a part 204a of the side wall of the via hole 204 is exposed (first etching process). Specifically, the multilayer mask is removed in order from the upper layer to the width of the target wiring groove, and the resist 205 is removed excessively until reaching the upper portion of the via hole 204, thereby forming the resist non-filling portion 210 in the via hole 204. It forms (FIG.2 (c)). Then, by utilizing the high processing selectivity between the SiO ₂ film (hard mask 203) and the SiOCH film (insulating film 202), the insulating film 202 is exposed to be processed into a shape free of shoulder drop, and the via hole 204 is processed. A horizontal plane is formed in the opening (FIG. 2D). As the etchant, a mixed gas (first etching gas) containing a CHF gas composed of three elements of carbon (C), hydrogen (H), and fluorine (F) can be used. A gas selected from the group consisting of nitrogen (N ₂ ), tetrafluorocarbon (CF ₄ ), difluoromethane (CH ₂ F ₂ ), and oxygen (O ₂ ) may be mixed.

Next, as shown in FIGS. 3E, 3F, and 3G, the insulating film 202 is removed from the exposed sidewall 204a of the via hole to form the wiring trench 6 and the via hole (second etching step). . Specifically, the resist non-filling portion 210 is tapered at the initial stage of processing of the wiring trench 6 (FIG. 3E). Since the resist unfilled portion 210 not protected by the resist 205 is also etched from the side wall direction of the via hole 204, the processing of the wiring groove 6 proceeds to taper. When the taper reaches the resist 205, the resist 205 prevents the etchant from being supplied from the side wall direction of the via hole 204 (the etching from the side wall direction of the via hole 204 is not performed), and the taper is stopped (FIG. 2 ( f)). From there, the processing of the wiring trench 6 is further advanced, so that only the resist unfilled portion 210 is etched toward the side wall of the via hole 204, and the diameter of the resist unfilled portion 210 is enlarged (FIG. 2 (g)). As the etchant, a mixed gas containing oxygen gas (second etching gas) can be used. Specifically, a gas selected from the group consisting of Ar, N ₂ , CF ₄ , CHF ₃ and CH ₂ F ₂ may be mixed with the oxygen gas. By doing so, first, the upper via hole 5 is formed. Upper via hole 5 has a diameter (opening diameter _{d 2a>} bottom diameter _{d 2b)} is smaller than and connected to the wiring groove 6 and the diameter _{d 3} of the wiring groove 6. Further, the bottom surface 4 of the upper via hole 5 is formed substantially parallel to the bottom surface of the via hole 204. The bottom surface of the upper via hole 5 is preferably formed with an inclination of 0 ° to 10 ° with respect to the bottom surface of the via hole 204. It is also possible to make the inclination angle of the side wall of the upper via hole 5 60 ° or more by performing etching while keeping the peripheral edge of the opening portion of the via hole 204 in a horizontal plane and further stopping the taper in the middle. .

Next, as shown in FIG. 3 (h), the resist 205 is removed from the bottom surface 4 of the upper via hole 5 by, for example, ashing, and is further generated from a mixed gas of an oxidizing gas containing oxygen atoms (O) and a fluoride gas. The cap film 201d at the bottom of the via hole is removed by the plasma. O ₂ gas or carbon dioxide gas (CO ₂ ) can be used for the ashing and oxidizing gas, and it is particularly preferable to use O ₂ plasma.

  Next, as shown in FIG. 4I, a first barrier metal film 212 is formed by PVD (physical vapor deposition). The first barrier metal film 212 at the bottom of the lower via hole 3 is resputtered by Ar ion sputtering, and Cu in the lower Cu wiring 201c is dug to form a punch-through portion 213 (FIG. 4 (j)). Next, the second barrier metal film 214 is formed by the PVD method (FIG. 4K). For example, the wiring groove 6 and the via hole 7 are filled with Cu or a Cu alloy by the electroplating method to produce the upper Cu wiring 215, and the upper Cu wiring 215 is covered with the cap insulating film 216 (FIG. 4L). The PVD method may be a normal sputtering method. However, in order to improve the embedding characteristics, the film quality, and the uniformity of the film thickness within the wafer surface, for example, a long throw sputtering method, a collimated sputtering method, an ion sputtering method, or the like. It is also possible to use a sputtering method with high directivity such as a knitted sputtering method. When sputtering an alloy, a metal film other than the main component is previously contained in the metal target at a solid solubility limit or less, so that the formed metal film can be used as an alloy film. Thereafter, the semiconductor device is completed through an arbitrary process.

  It continues and demonstrates the effect of this embodiment, using FIG. According to the present embodiment, a plurality of holes having different diameters (upper via hole 5 and lower via hole 3) are connected in the depth direction so that the diameter is reduced downward, and the connection portion is substantially connected to the base. A via hole 7 having a parallel surface 4 is provided. Thereby, the barrier metal can be resputtered on the horizontal plane 4 in the via hole 7, and the barrier metal can be reattached to the side wall of the via hole 7. Therefore, the barrier metal coverage on the side wall of the via hole 7 can be improved.

  Further, by providing such a via hole 7, the inclination angle of the side wall of the via hole 7 can be easily increased. Therefore, the resputtering process can be used together, and Cu embedding becomes easy. Further, the width Δd of the horizontal surface 4 of the via hole 7 is set to 5 nm or more, and an inclination of 0 ° to 10 ° with respect to the cap insulating film 1d serving as a base, whereby the barrier metal re-sputtered in an appropriate amount is formed on the sidewall of the via hole 7. Reattach to. Therefore, even if the taper angle of the side wall of the via hole 7 is 30 ° to 60 °, the barrier metal is supplied from the horizontal surface 4 to the side wall of the via hole 7. Resputtering can be suppressed. Therefore, barrier metal coverage can be improved.

  Non-Patent Document 1 shows a correlation example between the etching rate by oxygen ions and the ion incident angle. An example of this is shown in FIG. This correlation example can be considered equivalent to the correlation between the taper angle and the resputtering speed. That is, when the side wall of the via (c in FIG. 15) is 90 ° and the bottom surface of the wiring groove is 0 ° (a in FIG. 15), the wiring groove has a taper angle of 30 to 60 ° (b in FIG. 15). The resputtering speed is more than double that of the bottom surface. Therefore, depending on the taper angle, resputtering becomes excessive, and the barrier metal film is insufficient in the taper portion. Furthermore, this causes deterioration of the Cu seed coverage and the accompanying increase in microvoids, and ultimately degrades the reliability of the via wiring.

  When using the manufacturing method described in Patent Document 1, a taper shape having a taper angle of 60 ° or more is required in consideration of the combined use with the resputtering process. However, since the etching rate becomes maximum near 45 °, the taper angle is usually stable at 45 to 50 °. In the example described in Patent Document 1, the taper angle is 53 °, and sufficient resputtering cannot be performed in consideration of the increase in the resputtering speed on the tapered surface.

  In the semiconductor device of this embodiment, the barrier metal coverage on the side wall of the via hole 7 can be improved, and the Cu embedding property can be improved. Therefore, the manufacturing yield and reliability of the through-hole via can be improved.

  Embodiments including specific material configurations of the present invention will be described below with reference to the drawings.

(Example)
6 to 9 are cross-sectional views showing a method for manufacturing a semiconductor device in an embodiment of the present invention. A first wiring layer 601 was formed on a silicon substrate (not shown) by a single damascene method (FIG. 6A). That is, the lower Cu wiring 601c is embedded in a groove previously formed in the insulating film 601a, and excess metal other than in the groove is removed by a CMP method. Next, the side surface and outer periphery of the lower Cu wiring 601c are covered with a barrier metal film 601b, and the upper surface of the lower Cu wiring 601c is covered with a cap insulating film 601d. Note that the second and subsequent wiring layers formed on the upper portion by the dual damascene method or the single damascene method can be formed by the same method as the first wiring layer 601. The wiring interlayer insulating film 601a that forms the first wiring layer 601 may be different from the wiring interlayer insulating film 602 that forms the second and subsequent wiring layers. For example, the wiring interlayer insulating film 601a forming the first wiring layer 601 has an SiOCH film having a relative dielectric constant of 3.1, and the wiring interlayer insulating film 602 forming the second wiring layer and later has a relative dielectric constant of 2.5. The SiOCH film may be used.

  A SiOCH film having a thickness of 210 nm and a relative dielectric constant of 2.5, which becomes the wiring interlayer insulating film 602, is formed on the first wiring layer 601 from the raw material having the cyclic organic silica structure represented by the above formula (2). A film was formed by plasma CVD.

Thereafter, a surface modification layer is formed by He plasma treatment for a treatment time of 15 to 30 seconds. In the same chamber, a SiO ₂ film having a thickness of 80 nm is used as a hard mask 603, and plasma CVD using SiH ₄ as a source gas. The film was formed by the method. The SiO ₂ film of the hard mask 603 may be used SiO ₂ film using TEOS (tetraethoxysilane) as a source gas. Further, the He plasma treatment and the SiO ₂ hard mask film formation may be performed in separate chambers. Thereafter, a through-hole via 604 is formed by an existing through-hole etching process (FIG. 6B).

  Next, a resist 605 having a thickness of 250 nm is applied to fill the through-hole via 604 (FIG. 6C).

Next, in order to form unevenness on the surface of the resist 605 in the filling portion to the through-hole via 604, the entire surface of the resist 605 is etched back using oxygen plasma. (FIG. 6 (d)). At this time, the etch-back conditions of the resist 605 are, for example, an O ₂ flow rate of 0.1 × 10 ^{3 to} 0.3 × 10 ³ sccm, a pressure: 1.3 to 4 Pa (10 to ³⁰ mtorr), and an RF power: 0.5 to It is preferable to set 1.5 kW and time: 10 to 60 seconds.

  Thereafter, a resist 606 having a thickness of 250 nm is applied again on the hard mask 603, and a multilayer resist mask including the low-temperature oxide film 607, the antireflection film 608, and the resist 609 is formed. A trench pattern 610 is formed through an exposure process using the multilayer resist mask (FIG. 7E).

Next, the hard mask 603 of the trench pattern 610 is exposed by an existing resist processing process (FIG. 7F). Using the processing selectivity between the hard mask 603 and the resist 606, only the resist 606 is partially removed from the upper portion of the through-hole via 604 to form an unfilled portion 611 (FIG. 7G). The depth (ΔD) of the unfilled portion 611 is preferably 20 to 40 nm. When the hard mask 603 is etched after the unfilled portion 611 is formed, isotropic etching having processing selectivity between the SiO ₂ film (hard mask 603) and the SiOCH film (wiring interlayer insulating film 602) is used. Thus, the wiring interlayer insulating film 602 is exposed without dropping the shoulder (FIG. 7H). At this time, the etching conditions of the hard mask 603 are, for example, Ar: 0.4 × 10 ³ to 1 × 10 ³ sccm, CF ₄ : 0 to 0.35 × 10 ³ sccm, CHF ₃ : 20 to 40 sccm, Pressure: 4 It is preferable to set to 6.7 Pa (30 to 50 mtorr), RF power: 0.5 to 1.5 kW, and time: 40 to 60 seconds.

Next, the wiring interlayer insulating film 602 is dry-etched under the oxygen flow rate-containing etching conditions, and the filler resist 605 is also dry-etched at a similar rate. As the dry etching progresses, the wiring interlayer insulating film 602 in the unfilled portion 611 begins to fall off (FIG. 8I). By proceeding with the trench etching as it is, the diameter of the non-filled portion 611 is enlarged (FIG. 8 (j)) and becomes a two-stage shape (FIG. 8 (k)). At this time, the trench etching conditions are, for example, Ar: 0.2 × 10 ^{3 to} 0.6 × 10 ³ sccm, CF ₄ : 0.3 × 10 ^{3 to} 0.5 × 10 ³ sccm, O ₂ : 5 to 10 sccm. The pressure is preferably set to 4 to 6.7 Pa (30 to 50 mtorr), the RF power is set to 0.2 to 1 kW, and the time is set to 5 to 20 seconds.

After the through-hole via 604 to form a two-step shaped to interconnect trenches and the upper via hole, fillers resist 605, the resist 606 is removed by ashing using _{O 2,} subsequently a mixed gas of _CF 4, Ar and _{O 2} The via bottom cap insulating film 601d is opened by dry etching using, thereby forming an opening (lower via hole) 612 (FIG. 8L).

  Next, Cu oxide, etching products, and the like on the surface of the Cu wiring in the opening 612 are removed by chemical treatment, and the opening 612 is cleaned. At this time, the chemical solution preferably contains fluorine. Further, a first barrier metal film 613 having a thickness of 3 to 5 nm is formed by ionization sputtering (FIG. 9 (m)). The first barrier metal film 613 at the bottom of the via is resputtered by Ar ion sputtering, and Cu of the first wiring layer is dug by 5 to 20 nm to form a punch-through portion 614 (FIG. 9 (n)). A second barrier metal film 615 having a thickness of 5 to 10 nm is formed by sputtering (FIG. 9 (o)). At this time, ALD (Atomic Layer Deposition) may be used for forming the barrier metal films 613 and 615. The first barrier metal film 613 is preferably a tantalum nitride or nitrogen-containing tantalum film.

  Thereafter, Cu or Cu alloy is embedded on the barrier metal film 615 by electroplating to form an upper Cu wiring 616, and then heat treatment is performed at 350 ° C. for 2 minutes in a nitrogen atmosphere for Cu grain growth. Then, excess Cu and hard mask 603 are removed by CMP. After the second wiring layer is formed by the CMP process, a cap insulating film 617 is formed by a CVD method to form a two-layer wiring using the SiOCH film (FIG. 9 (p)). At this time, Cu or Cu alloy may be CuAl or other Cu alloy.

  Among the methods shown in this embodiment, three types of via wirings in which the depth (ΔD) of the resist unfilled portion 611 is 0 to 20 nm, 20 to 40 nm, and 40 nm or more in the step shown in FIG. The evaluation was as follows.

1. Observation by TEM (Transmission Electron Microscope) FIG. 10 is a diagram showing a result of observing a cross section of a via wiring shape with a TEM (Transmission Electron Microscope). When the depth (ΔD) of the resist unfilled portion 611 is reduced to 0 to 10 nm, the via wiring shape becomes a vertical shape without shoulder drop as shown in FIG. 10A (hereinafter referred to as a vertical via). On the other hand, when the depth (ΔD) of the resist unfilled portion 611 is set to 20 to 40 nm, it can be seen that a two-stage shape corresponding to the unfilled portion depth is obtained as shown in FIG. Hereinafter referred to as a two-stage via). Further, when the depth (ΔD) of the resist unfilled portion 611 was processed at 40 to 100 nm, a taper shape with a taper angle of 45 ° was formed as shown in FIG. 10C (hereinafter referred to as a taper via). Thus, it has been found that the via wiring shape can be controlled by the resist filling amount of the through-hole via 604. The two-stage via has a structure corresponding to FIG. 1, and a via hole 7 connecting the upper via hole 5 and the lower via hole 3 is formed on the bottom surface of the wiring groove 6. A substantially horizontal surface 4 is formed at the connection portion between the upper via hole 5 and the lower via hole 3. The bottom surface 4 of the connection portion between the upper via hole 5 and the lower via hole 3 has an inclination of 5 ° with respect to the underlying cap insulating film. Further, Δd was 50 nm and D / Δd was 0.66.

2. Evaluation of Via Resistance FIG. 11 shows a probability cumulative distribution of each via resistance in the above-described three types of via wiring shapes. The taper via had a large variation on the low resistance side, while the vertical via and the two-stage via could reduce the variation. Since the via bottom of the tapered via is exposed in the etchant supply direction, the via diameter is likely to be enlarged during the opening process of the cap insulating film 601d shown in FIG. For this reason, it was considered that the taper via greatly varied toward the low resistance side. On the other hand, the vertical via and the two-stage via were considered to be able to reduce variations because the size variation hardly occurred when the cap insulating film 601d was opened.

3. Evaluation of Number of Defects in Large-Scale Via Chain FIG. 12 shows the result of comparison of the number of defects in the large-scale via chain in the three types of via wiring shapes described above. Compared to vertical and tapered vias, the number of defects in the two-stage via was greatly reduced to half that of the vertical via.

4). Reliability Evaluation for Stress-Induced Voiding (SIV) FIG. 13 shows the results of the SiV reliability test in the three types of via wiring shapes described above. As a defect determination of the SiV reliability, a case where the resistance value per unit via of the SiV evaluation chain increased by 10% was defined as an SiV defect. Assuming that the lower layer wiring and the upper layer wiring connected through the through holes are M1 and M2, respectively, the pattern of M2 / M1 = 0.14 / 3.0 μm was subjected to high-temperature storage up to 1000 hours. As a result, the taper via defect rate was 20%. In contrast to the rise to near, the defect rate was 0% for the vertical via, and about 1% for the two-stage via (1 piece in the measured TEG), indicating high reliability.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable. For example, in the present embodiment, an example in which the base is a cap insulating film has been described, but the base may be a substrate. Other aspects of the invention are described below.

As another aspect of the present invention, a cap insulating film mainly composed of silicon (Si) and carbon (C) formed on a Cu wiring, and a wiring layer mainly composed of Si, C and oxygen (O). A Cu dual damascene wiring connected to the underlying Cu wiring is formed in the wiring interlayer insulating film via the through-hole via, and the through-hole via is at least two different. There is a semiconductor device having a multi-stage structure having a diameter, wherein the connection part having a different diameter of the multi-stage through-hole via has a horizontal plane of 0 ° to 10 °.
Another aspect of the semiconductor device is characterized in that a difference in different diameters of the multistage through-hole via is at least 5 nm or more.
Furthermore, the via bottom of the step-structure through-hole via is buried in the underlying Cu wiring.
Further, the wiring insulating film is a carbon-rich SiOCH film having a carbon / silicon ratio (C / Si) in the film larger than 1.
Furthermore, the carbon-rich SiOCH film is a film characterized in that the average pore diameter is less than 0.8 nm and each pore is an independent pore.
Furthermore, the cap insulating film is any one of SiCN, SiC, SiN, or a laminated film thereof. Alternatively, the cap insulating film is a composite film containing an unsaturated hydrocarbon and amorphous carbon, or a laminated film of the SiCN or SiC and the film and the composite film.
Furthermore, the carbon-rich SiOCH film has a cyclic organic silica structure represented by the general formula (1).
Furthermore, the cyclic organic silica structure has a structure shown in the general formulas (2) and (3).

According to another aspect of the present invention, a method of manufacturing a semiconductor device includes a cap insulating film mainly composed of Si and C formed on a Cu wiring, and Si and C mainly composed of oxygen (O). A method of manufacturing a semiconductor device, wherein a Cu dual damascene wiring connected to a lower Cu wiring via a through-hole via is formed in the wiring interlayer insulating film and has a laminated structure. In the step of forming the dual damascene wiring in such a laminated structure, a step of burying a filler in a through hole via formed by a known dry etching step, and a trench by a known multilayer mask and a lithography step on the through hole via. A step of forming a groove pattern, and the multilayer mask containing a CHF-based gas composed of three elements of carbon (C), hydrogen (H), and fluorine (F). By removing by dry etching using a gas, further excessive partially removing the through hole via the fill by advancing the etching, and forming a non-filled portion in the through-hole via, the O ₂ at the same time the filler and the wiring insulating film by dry etching using a mixed gas containing forming the trench by dry etching, the step of processing the through-hole via the opening in multiple stages shape, O ₂ or And a step of removing the filling material using an oxidizing gas containing oxygen (O).
Furthermore, the mixed gas containing the CHF-based gas includes Ar, N ₂ , CF ₄ , CH ₂ F ₂ , O ₂ , or a plurality of these gases.
Furthermore, the mixed gas containing O ₂ includes any one of Ar, N ₂ , CF ₄ , CH ₂ F ₂ , and CHF ₃ , or a plurality of these gases.
Furthermore, the wiring insulating film is a SiOCH film having a composition ratio C / Si of 1 or more.

  According to the above aspect, in the via first dual damascene processing method of the wiring interlayer insulating film formed on the Cu wiring, the through hole via is processed into a multistage structure having at least two different diameters simultaneously with the trench groove processing. Thus, the aspect ratio of the through-hole via is reduced and the Cu burying property is improved. As a result, the manufacturing yield and reliability of through-hole vias are improved.

DESCRIPTION OF SYMBOLS 1 Lower layer Cu wiring structure 1a Insulating film 1b Barrier metal film 1c Lower Cu wiring 1d Cap insulating film 2 Upper layer Cu wiring structure 2a Insulating film 2b Barrier metal film 2c Upper Cu wiring 2d Cap insulating film 3 Lower via hole 4 Bottom surface 5 of connection part Upper via hole 6 Wiring groove 7 Via hole 140 Lower wiring 141 Wiring groove 142 Via 201 Lower layer Cu wiring structure 201a Insulating film 201b Barrier metal film 201c Lower Cu wiring 201d Cap insulating film 202 Insulating film 203 Hard mask 204 Via hole 204a Via hole Side wall portion 205 Resist 206 Low temperature oxide film 207 Antireflection film 208 Resist 209 Trench groove pattern 210 Unfilled portion 212 First barrier metal film 213 Punch through portion 214 Second barrier metal film 215 Upper Cu wiring 216 Cap insulating film 301 Reservoir 302 Raw material pumping unit 303 Carrier gas supply unit 304 Liquid mass flow 305 Gas mass flow 306 Vaporizer 307 Reactor 308 Substrate 309 RF power supply 310 Exhaust pump 401 Via etching stopper film 402 Inter-via insulating film 403 Wiring etching stopper film 404 Inter-wiring insulating film 601 First wiring layer 601a Insulating film 601b Barrier metal film 601c Lower Cu wiring 601d Cap insulating film 602 Wiring interlayer insulating film 603 Hard mask 604 Through hole via 605 Resist 606 Resist 607 Low temperature oxide film 608 Antireflection film 609 Resist 610 Trench pattern 611 Unfilled portion 612 Opening 613 First barrier metal film 614 Punch-through portion 615 Second barrier metal film 616 Upper Cu wiring 617 Cap insulating film

Claims (19)

An insulating film formed on the ground,
A wiring groove formed in the insulating film;
A connection hole formed in the bottom surface of the wiring groove;
A barrier metal film covering at least the side wall of the connection hole;
Have
The connection hole is composed of a plurality of holes having different diameters,
The plurality of holes are connected in the depth direction so that the diameter decreases downward,
A semiconductor device having a plane substantially parallel to the base at a connection portion of the plurality of holes.   2. The semiconductor device according to claim 1, wherein a connection portion of the plurality of holes has a surface having an inclination of 0 ° to 10 ° with respect to the base.   The semiconductor device according to claim 1, wherein a side wall of the connection hole is formed in a tapered shape.   4. The semiconductor device according to claim 1, wherein Δd ≧ 5 nm, where Δd is a difference between a diameter of a bottom surface of the upper hole and an opening diameter of the lower hole.   The semiconductor device according to claim 1, wherein the base is a cap insulating film containing silicon (Si) and carbon (C) as main components. It further has a metal wiring whose upper surface is covered with the cap insulating film,
The semiconductor device according to claim 1, wherein a bottom surface of the connection hole enters the metal wiring.   The semiconductor device according to claim 1, wherein the insulating film contains Si, C, and oxygen (O) as main components.   The semiconductor device according to claim 7, which is a SiOCH film having a carbon / silicon ratio (C / Si) in the insulating film of greater than 1.   The semiconductor device according to claim 8, wherein the insulating film has a plurality of holes that are independent of each other, and the average hole diameter of the holes is 0.8 nm or less.   10. The semiconductor device according to claim 8, wherein the insulating film has a trimeric cyclic siloxane structure, and an unsaturated or saturated carbon chain is bonded to silicon constituting the cyclic siloxane structure.   The semiconductor device according to claim 1, wherein an inclination angle of a side wall of the connection hole is 60 ° to 90 °. Forming an insulating film;
Forming a connection hole penetrating the insulating film;
Filling the connection hole with a filler;
Forming a mask covering the opening of the connection hole on the insulating film;
A first etching step of removing a part of the mask and the filler and exposing a part of a side wall of the connection hole;
Removing the insulating film from the exposed sidewall of the connection hole to form a wiring groove and a connection hole;
Covering at least the side wall of the connection hole with a barrier metal film;
Including
In the second etching step,
A plurality of holes having different diameters from the bottom surface of the wiring groove are connected in the depth direction so that the diameter decreases downward, and the connection hole is formed at a connection portion of the plurality of holes. A method for manufacturing a semiconductor device, wherein a surface substantially parallel to the surface is formed.   The method for manufacturing a semiconductor device according to claim 12, wherein in the second etching step, a surface having an inclination of 0 ° to 10 ° with respect to a bottom surface of the connection hole is formed in the connection portion. The second etching step further includes a step of removing the filler,
In the first etching step, the mask and the filler are removed using a first etching gas containing a CHF-based gas composed of three elements of carbon (C), hydrogen (H), and fluorine (F),
In the second etching step,
The insulating film is removed using a second etching gas containing oxygen gas,
14. The method for manufacturing a semiconductor device according to claim 12, wherein the filler is removed using an oxidizing gas containing oxygen atoms (O). The method for manufacturing a semiconductor device according to claim 14, wherein the first etching gas includes a gas selected from the group consisting of Ar, N ₂ , CF ₄ , CH ₂ F _2, and O ₂ . The method for manufacturing a semiconductor device according to claim 14, wherein the second etching gas includes a gas selected from the group consisting of Ar, N ₂ , CF ₄ , CHF _3, and CH ₂ F _2. .   Forming a cap insulating film composed mainly of silicon (Si) and carbon (C) covering the lower wiring between the step of forming a lower wiring and the step of forming the insulating film; The method for manufacturing a semiconductor device according to claim 12, further comprising: 18. The method of manufacturing a semiconductor device according to claim 12, wherein in the step of forming the insulating film, the insulating film is formed from a raw material represented by the following general formula (1) having a cyclic organic silica structure. .

In formula (1), R ₁ and R ₂ are an unsaturated carbon compound or a saturated carbon compound (alkyl group), and the unsaturated group is any of a vinyl group, a propenyl group, an isopropenyl group, a methylpropenyl group, and a dimethylpropenyl group. The alkyl group is any one of a methyl group, an ethyl group, a propyl group, an isopropyl group, and a butyl group. R1 and R2 may be the same or different. The method for manufacturing a semiconductor device according to claim 18, wherein the raw material having a cyclic organic silica structure has a structure represented by the following formula (2) or formula (3).

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