JP2005310880A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for improving the reliability of a semiconductor device. <P>SOLUTION: A liner film 13 and an interlayer insulating film 3 are laminated on an interlayer insulating film 1 in which a lower layer wiring 2 is embedded, and a through hole 6 is formed therein. A tantalum nitride film 7 is formed on the surface of the through hole 6 and the lower layer wiring 2, and a tantalum film 8 is formed thereon. A first metal layer 10 is formed on the tantalum film 8, and a second metal layer 11 for filling the through hole 6 is formed thereon. The first metal layer 10 and second metal layer 11 comprise copper or copper-based metal, and the second metal layer 11 is formed by electrolytic plating method using the first metal layer 10 as a seed layer. The ratio of the thickness of the tantalum film 8 to that of the tantalum nitride film 7 is set to be 4 or over. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a metal layer made of copper or a copper-based metal and a method for manufacturing the same.

  As the dimensions of semiconductor devices are reduced, copper wiring has been used instead of conventional aluminum wiring. Usually, the copper wiring is formed using a damascene method. For example, a barrier metal layer and a seed layer are sequentially formed on the surface of the hole provided in the interlayer insulating film, and then a plating layer filling the hole is formed using an electrolytic plating method.

  In a semiconductor device having such a copper wiring, reliability is improved by reviewing a barrier metal layer, a seed layer, a plating layer, or annealing conditions performed after the plating layer is formed. For example, in Patent Document 1, an amorphous barrier film is formed on a (002) -oriented titanium film, and these are used as a barrier metal layer, whereby the (111) orientation of the seed layer and the plating layer on the barrier metal layer. As a result, the reliability of the semiconductor device is improved.

  Patent Documents 2 to 7 also disclose techniques related to copper wiring.

JP 2000-183064 A Japanese Patent Laid-Open No. 11-283379 Japanese Patent Laid-Open No. 11-26394 JP-A-11-307476 JP 2001-148383 A JP 2002-155390 A JP 2001-189287 A

  As described above, the technique of Patent Document 1 attempts to improve the reliability of the semiconductor device by enhancing the (111) orientation of the seed layer and the plating layer. However, the (111) orientation of the seed layer and the plating layer is improved. However, there is a case in which the expected effect cannot be obtained and sufficient reliability of the semiconductor device cannot be secured.

  Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of improving the reliability of a semiconductor device.

  The method for manufacturing a semiconductor device according to the present invention includes (a) a step of forming a hole in an interlayer insulating film, (b) a step of forming a tantalum nitride film on the surface of the hole, and (c) the tantalum nitride. Forming a tantalum film on the film; (d) forming a first metal layer made of copper or a copper-based metal on the tantalum film; and (e) electrolysis using the first metal layer as a seed layer. Forming a second metal layer made of copper or a copper-based metal and filling the hole on the first metal layer using a plating method, and the tantalum nitride formed in the step (b) The ratio of the film thickness of the tantalum film formed in the step (c) to the film thickness is set to 4 or more.

  According to the method for manufacturing a semiconductor device of the present invention, since the first metal layer is formed on the laminated film of the tantalum nitride film and the tantalum film, the (111) orientation of the first metal layer is reduced. When the second metal layer is formed on the first metal layer by the electrolytic plating method using the first metal layer as a seed layer, the (111) orientation of the second metal layer is also reduced. Therefore, the crystal grain size of the second metal layer is increased. In the present invention, since the ratio of the tantalum film thickness to the tantalum nitride film thickness is set to 4 or more, the crystal grain size of the second metal layer is significantly increased. Therefore, the bamboo structure in the second metal layer can be reliably maintained, and generation of void growth nuclei in the second metal layer can be suppressed. As a result, the reliability of the semiconductor device is improved.

  FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device according to the present embodiment includes an interlayer insulating film 1 in which a lower layer wiring 2 is embedded. The lower wiring 2 is formed by laminating a metal layer (not shown) made of copper or a copper-based metal and a conductive barrier metal layer (not shown) interposed between the metal layer and the interlayer insulating film 1. The upper surface of the structure is exposed from the interlayer insulating film 1. A semiconductor substrate (not shown) on which a semiconductor element is formed exists below the interlayer insulating film 1, and the semiconductor element formed on the semiconductor substrate and the lower layer wiring 2 are electrically connected. The interlayer insulating film 1 is made of, for example, a silicon oxide film.

  A liner layer 13 is formed on the interlayer insulating film 1 and the lower layer wiring 2. The liner layer 13 is made of, for example, a silicon nitride film. An interlayer insulating film 3 made of, for example, a silicon oxide film is formed on the liner layer 13.

  A through hole 6 extending from the upper surface of the interlayer insulating film 3 to the upper surface of the lower layer wiring 2 is formed in the liner layer 13 and the interlayer insulating film 3. The through hole 6 is formed by the connection hole 4 and the groove 5. Yes. The trench 5 is formed on the interlayer insulating film 3 and opens toward the upper surface of the interlayer insulating film 3. The connection hole 4 communicates with the groove 5 and is formed in the lower part of the interlayer insulating film 3 and the liner layer 13. The connection hole 4 partially exposes the upper surface of the lower layer wiring 2.

  A tantalum nitride film (hereinafter referred to as “TaN film”) 7 is formed on a portion of the upper surface of the lower layer wiring 2 exposed by the connection hole 4 and on the surface of the through hole 6. A tantalum film (hereinafter referred to as “Ta film”) 8 is formed thereon. The TaN film 7 and the Ta film 8 constitute a barrier metal layer 9. In the semiconductor device according to the present embodiment, the ratio of the thickness of the Ta film 8 to the thickness of the TaN film 7 is set to 4 or more. That is, the value obtained by dividing the thickness of the Ta film 8 by the thickness of the TaN film 7 is 4 or more. For example, the film thicknesses of the TaN film 7 and the Ta film 8 are set to 10 nm and 45 nm, respectively.

  A first metal layer 10 is formed on the Ta film 8 of the barrier metal layer 9. A second metal layer 11 that fills the through hole 6 is formed on the first metal layer 10. The first metal layer 10 and the second metal layer 11 are made of copper or a copper-based metal. As described later, the second metal layer 11 is formed by an electrolytic plating method using the first metal layer 10 as a seed layer.

  Of the barrier metal layer 9, the first metal layer 10 and the second metal layer 11 filling the through hole 6, the portion filling the groove 5 functions as an upper layer wiring, and the portion filling the connection hole 4 is the upper layer wiring. And function as a contact plug that electrically connects the lower layer wiring 2.

  The liner layer 13, the barrier metal layer in the lower wiring 2 and the barrier metal layer 9 are connected to the interlayer insulating films 1 and 3 of copper atoms contained in the lower wiring 2, the first metal layer 10 and the second metal layer 11. Demonstrate the ability to prevent diffusion.

  Next, a method for manufacturing the semiconductor device according to the present embodiment shown in FIG. 1 will be described. 2 to 6 are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of steps. As shown in FIG. 2, first, the lower layer wiring 2 is embedded in the interlayer insulating film 1, and the liner layer 13 and the interlayer insulating film 3 are sequentially formed on the interlayer insulating film 1 and the lower layer wiring 2. Then, by performing dry etching, the groove 5 is formed in the upper part of the interlayer insulating film 3 and the connection hole 4 is formed in the lower part and the liner layer 13. Thereby, the through hole 6 is completed in the interlayer insulating film 3 and the liner layer 13.

  Next, as shown in FIG. 3, a TaN film 7 having a film thickness of 10 nm is formed on the entire surface by, eg, sputtering. As a result, the TaN film 7 is formed on the upper surface of the interlayer insulating film 3, the surface of the through hole 6, and the upper surface of the lower layer wiring 2 exposed by the connection hole 4. Then, as shown in FIG. 4, a Ta film 8 having a film thickness of 45 nm is formed on the TaN film 7 by using, for example, a sputtering method. Thereby, a barrier metal layer 9 composed of the TaN film 7 and the Ta film 8 is formed. In this example, the ratio of the thickness of the Ta film 8 to the thickness of the TaN film 7 is set to 4.5.

  Next, as shown in FIG. 5, the first metal layer 10 having a thickness of 80 nm used as a seed layer is formed on the Ta film 8 by using, for example, a sputtering method. Then, as shown in FIG. 6, for example, a second metal layer 11 having a thickness of 600 nm is formed on the first metal layer 10 by using an electrolytic plating method using the first metal layer 10 as a seed layer. At this time, a copper sulfate electrolytic plating solution is used. Thereby, the through hole 6 is filled with the second metal layer 11. Then, the structure obtained after the formation of the second metal layer 11 is annealed at 100 ° C. in a nitrogen atmosphere.

  Next, the barrier metal layer 9, the first metal layer 10, and the second metal layer 11 on the interlayer insulating film 3 are removed using a CMP method. Thereby, the semiconductor device shown in FIG. 1 is obtained.

  As described above, in the present embodiment, since the laminated film of the TaN film 7 and the Ta film 8 is adopted as the barrier metal layer 9, when the first metal layer 10 is formed on the barrier metal layer 9, the first metal layer 10 is formed. The (111) orientation of the metal layer 10 decreases. When the second metal layer 11 is formed on the first metal layer 10 by the electrolytic plating method using the first metal layer 10 as a seed layer, the (111) orientation of the second metal layer is also reduced. Therefore, the crystal grain size of the second metal layer 11 is increased. In this embodiment, since the film thickness ratio of the Ta film 8 to the TaN film 7 is set to 4 or more, the crystal grain size of the second metal layer 11 is significantly increased. Therefore, the bamboo structure in the second metal layer 11 can be reliably maintained, and generation of void growth nuclei in the second metal layer 11 can be suppressed. As a result, the reliability of the semiconductor device is improved. This will be described in detail below.

  In general, the cause of electromigration in copper wiring made of copper or a copper-based metal is considered to be dominated by surface diffusion rather than grain boundary diffusion. However, when electromigration is evaluated, wiring having a thick width tends to have a shorter life than wiring having a narrow width, and this tendency cannot be explained by surface diffusion that does not depend on the wiring width. This trend is thought to occur because the actual wiring life is determined by the fastest growing void. In other words, as the wiring width increases, the wiring structure changes from a bamboo structure to a polycrystalline structure, and this causes many defect structures that become void growth nuclei such as grain boundary triple points in the wiring. Increasing the wiring is thought to shorten the life of the wiring. Therefore, as the crystal grain size of the wiring increases, the grain boundary tends to form a bamboo shape. To maintain the wiring bamboo structure and suppress the generation of void growth nuclei, the crystal grain size of the wiring is increased. Is effective. That is, in the present embodiment, by increasing the crystal grain size of the second metal layer 11, generation of void growth nuclei therein can be suppressed.

  As described above, the second metal layer 11 is formed by an electrolytic plating method using the first metal layer 10 as a seed layer. In order to increase the crystal grain size of the second metal layer 11, the (111) orientation of the first metal layer 10 that is the seed layer is decreased, and each orientation of the first metal layer 10 is further increased. It needs to be even. FIG. 7 is a diagram showing the relationship between the material of the barrier metal layer 9 and the (111) orientation of the first metal layer 10. As shown in FIG. 7, when the Ta film is used as the barrier metal layer 9, the (111) orientation degree of the first metal layer 10 is 47120 cps, and when the TaN film is used, it is 10570 cps. In the case of adopting (denoted as “Ti film” in FIG. 7), it becomes 210170 cps. And when the laminated film of TaN film and Ta film is employ | adopted as the barrier metal layer 9 like this Embodiment, the (111) orientation degree of the 1st metal layer 10 will be 7400 cps.

  From the above results, it can be understood that a stacked film of a TaN film and a Ta film is excellent as the barrier metal layer 9 in order to reduce the (111) orientation of the first metal layer 10.

  8 shows the ratio of the film thickness of the Ta film 8 to the film thickness of the TaN film 7 in the barrier metal layer 9 (hereinafter referred to as “Ta / TaN film thickness ratio”) and (111) of the first metal layer 10. It is a figure which shows the relationship with orientation. As shown in FIG. 8, when the film thickness ratio of Ta / TaN increases, the (111) orientation of the first metal layer 10 decreases. FIG. 9 is a diagram showing the relationship between the Ta / TaN film thickness ratio and the (110) orientation of the Ta film 8. As shown in FIG. 9, when the film thickness ratio of Ta / TaN increases, the (110) orientation of the Ta film 8 increases. From these facts, it is considered that the increase in the (110) orientation of the Ta film 8 due to the increase in the Ta / TaN film thickness ratio is a cause of the decrease in the (111) orientation of the first metal layer 10.

  FIG. 10 is a diagram showing the relationship between the Ta / TaN film thickness ratio and the crystal grain size of the second metal layer 11. As shown in FIG. 10, as the Ta / TaN film thickness ratio increases, the crystal grain size of the second metal layer 11 increases. The rate of increase in the crystal grain size of the second metal layer 11 gradually decreases gradually until the Ta / TaN film thickness ratio is 3.5. However, when the Ta / TaN film thickness ratio is 4.0, the increase rate of the crystal grain size of the second metal layer 11 is significantly increased, and the crystal grain size is about 5 μm.

  As described above, when the Ta / TaN film thickness ratio is 4.0, the crystal grain size of the second metal layer 11 is significantly increased. Therefore, the bamboo structure of the second metal layer 11 can be reliably maintained by setting the Ta / TaN film thickness ratio to 4.0 or more as in the present embodiment. As a result, generation of void growth nuclei in the second metal layer 11 can be suppressed, and the reliability of the semiconductor device according to the present embodiment is improved.

  The crystal grain size of the second metal layer 11 when the semiconductor device according to the present embodiment is manufactured by the manufacturing method described with reference to FIGS. 2 to 6 is about 5.0 μm. On the other hand, in the manufacturing method described with reference to FIGS. 2 to 6 described above, the second metal in the case where the film thickness of the Ta film 8 is 10 nm, that is, the film thickness ratio of Ta / TaN is set to 1. The crystal grain size of the layer 11 is about 2.5 μm.

  The film thickness of the TaN film 7 of the barrier metal layer 9 is preferably set to 8 nm or more as in the present embodiment. This is because if the thickness of the TaN film 7 is less than 8 nm, the characteristics of the barrier metal layer 9 are deteriorated during high-temperature annealing that is normally performed after the formation of the second metal layer 11.

  In the present embodiment, the barrier metal layer 9 is formed using the sputtering method, but may be formed using the PVD method or the CVD method. Further, as a method of forming the barrier metal layer 9, even when a method of forming a film once, performing etching after that, and forming a film again is adopted, a final Ta / TaN film is formed. If the thickness ratio is 4 or more, the same effect as the present invention can be obtained.

  In the present embodiment, the first metal layer 10 that functions as a seed layer is formed by a sputtering method, but may be formed by a PVD method, a CVD method, or a plating method. Furthermore, as a method for forming the first metal layer 10, a method may be employed in which film formation is performed once, etching is performed thereafter, and film formation is performed again.

It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention in process order. It is a figure which shows the relationship between the material of a barrier metal layer, and the (111) orientation of a 1st metal layer. It is a figure which shows the relationship between the film thickness ratio of Ta / TaN in a barrier metal layer, and the (111) orientation of a 1st metal layer. It is a figure which shows the relationship between the film thickness ratio of Ta / TaN in a barrier metal layer, and the (110) orientation of Ta film. It is a figure which shows the relationship between the film thickness ratio of Ta / TaN in a barrier metal layer, and the crystal grain diameter of a 2nd metal layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Interlayer insulating film, 6 Through-hole, 7 Tantalum nitride film, 8 Tantalum film, 10 1st metal layer, 11 2nd metal layer

Claims (4)

(A) forming a hole in the interlayer insulating film;
(B) forming a tantalum nitride film on the surface of the hole;
(C) forming a tantalum film on the tantalum nitride film;
(D) forming a first metal layer made of copper or a copper-based metal on the tantalum film;
(E) forming a second metal layer made of copper or a copper-based metal and filling the hole on the first metal layer using an electroplating method using the first metal layer as a seed layer. ,
The method of manufacturing a semiconductor device, wherein a ratio of a film thickness of the tantalum film formed in the step (c) to a film thickness of the tantalum nitride film formed in the step (b) is set to 4 or more. A method of manufacturing a semiconductor device according to claim 1,
In the step (b), the film thickness of the tantalum nitride film is set to 8 nm or more. An interlayer insulating film;
A hole provided in the interlayer insulating film;
A tantalum nitride film provided on the surface of the hole;
A tantalum film provided on the tantalum nitride film;
A first metal layer made of copper or a copper-based metal provided on the tantalum film;
A second metal layer provided on the first metal layer and made of copper or a copper-based metal and filling the hole;
The ratio of the film thickness of the said tantalum film | membrane with respect to the film thickness of the said tantalum nitride film | membrane is set to 4 or more. The semiconductor device according to claim 3,
The semiconductor device, wherein a film thickness of the tantalum nitride film is set to 8 nm or more.

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