JP2005303602A - Ad converter measuring circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an AD converter measuring circuit capable of using an LSI tester that does not need a DC measuring unit to perform a test in short period of time in testing an AD converter. <P>SOLUTION: This AD converter measuring circuit is provided with a DA converter 204 for converting a digital signal into an analog signal and inputting the analog signal to an AD converter 102 of a measuring object, a counter 208 for generating an expected value of an output of the AD converter 102, and an EX-OR gate 211 and a flip-flop 212 for comparing an actual measured value being the output of AD converter 102 with the expected value being an output of the counter 208 and outputting a comparison result. In addition, the AD converter measuring circuit has an accuracy correction circuit 401 consisting of a flip-flop 402 for shifting a signal of the comparison result and an AND gate 404 for receiving the comparison result and an output of the flip-flop 402. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an AD converter measurement circuit that enables a unit test of an AD converter mounted on a semiconductor integrated circuit (hereinafter referred to as LSI: Large Scale Integration).

  A conventional unit test method for an AD converter will be described. In FIG. 6, reference numeral 101 denotes an LSI semiconductor device, and reference numeral 102 denotes an AD converter. The DC measurement unit 103 that can output an arbitrary voltage of the LSI tester is connected to supply an analog voltage to the input terminal 104. The digital output (m bits) 105 analog-digital converted by the AD converter 102 is taken into the memory of the LSI tester. Similarly, the analog input voltage is changed to increment or decrement, and the digital output value is stored in the memory. Then, the accuracy of the AD converter can be calculated by performing a soft operation for comparing the digital output value stored in the memory with an ideal value. Judgment is made based on the accuracy, and if it is within the allowable range of the product warranty, it is determined to be a non-defective product and if it is out of the range, it is determined to be a defective product.

In addition, Patent Document 1 filed as a prior patent discloses that in an LSI in which an AD converter and a DA converter are mixedly mounted, the AD converter and the DA converter can be simultaneously tested without outputting the output of the AD converter to the outside. It is only known that it is a circuit that enables it.
JP-A-11-326465

  However, the conventional test method cannot be tested without using an LSI tester that requires a DC measurement unit that can output an arbitrary voltage. In addition, there is a problem that a test time is required for the application, calculation and determination of the analog input voltage by the DC measurement unit.

  The present invention provides an AD converter measurement circuit that does not require a DC measurement unit, enables testing of an AD converter using a digital (input) -digital (output) -only LSI tester, and reduces the test time. For the purpose.

  In order to achieve the above object, an AD converter measurement circuit of the present invention includes a DA converter that converts a digital signal into an analog signal and inputs the analog signal to an AD converter to be measured, and an expected value that generates an expected value of the output of the AD converter. A generation unit and a comparison unit that compares an actual measurement value that is an output of the AD converter with an expected value and outputs a comparison result are provided.

  The above configuration includes a precision correction circuit configured by a flip-flop that shifts a signal of the comparison result and an AND gate that receives the output of the comparison result and the flip-flop.

  The above configuration includes H accuracy correction circuits connected in series via a selector, and an accuracy adjustment circuit that controls the selector to control the number of accuracy correction circuits connected in series.

  The AD converter measuring circuit of the present invention is connected to the outside of the AD converter to be measured and performs a test. Since the input terminal of the AD converter is connected to the output terminal of the DA converter, the input signal from the tester is an input to the DA converter and may be a digital value. Also, a mechanism is provided that compares the AD converted value with the ideal value generated by the counter and outputs an L or H value, and the test output is only the L or H determination result. Therefore, since both input and output are digital values, it is possible to perform a test using a digital (input) -digital (output) LSI tester without using a DC measurement unit.

  Therefore, it is possible to test AD converters with a digital (input) -digital (output) LSI tester in a short time without the need for a DC measurement unit, and with a precision within an arbitrary tolerance range. Is possible.

  According to the present invention, a wide variety of LSI testers can be used, and the test time can be greatly shortened, so that the test cost can be reduced.

  With the accuracy correction circuit, it is possible to determine pass / fail with a digital value in accordance with the accuracy of the AD converter under test within the allowable range.

  There are H accuracy correction circuits composed of flip-flops and AND gates inside, and using a selector and an accuracy adjustment circuit to control it, it is possible to judge pass / fail with digital values according to the accuracy within an arbitrary tolerance range And

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing a configuration of a first embodiment of an AD converter measurement circuit according to the present invention.

  In FIG. 1, 201 is an AD converter measurement circuit, 202 is a DA converter input terminal for supplying a digital value, 203 is an n-bit digital input signal, 204 is an n-bit DA converter, 205 is a clock, 206 is a clock generator, 207 Is a clock frequency determination signal, 208 is an m-bit counter, 209 is a count-up / down designation signal, 210 is an m-bit counter output, 211 is an EX-OR gate, 212 is an EX-OR gate output signal, 213 is a flip-flop, Reference numeral 214 denotes an output of the flip-flop, 215 denotes an OR gate, and 216 denotes output data.

  A signal flow of the AD converter measuring circuit configured as described above will be briefly described.

  An n-bit digital value and a clock signal 205 from the DA converter input terminal 202 are input to the AD converter measurement circuit 201. The input digital signal 203 is converted into an analog value by the n-bit DA converter 204 and input to the input terminal 104. An analog value converted by the DA converter 204 can be input to the m-bit AD converter 102 to be measured, and a digital output 105 can be obtained.

  Next, the expected value generating means includes a clock generator 206 and an operation selectable counter 208. That is, it is generated using the m-bit counter 208 that increments and decrements the ideal expected value of the AD converter 102. The clock signal 205 is input to the clock generator 206 and the clock frequency determination signal 207 is input, whereby the input clock signal 205 is frequency-divided into a frequency considering the specifications of the DA converter 204 and the AD converter 102 to perform clock conversion. I do. By inputting this clock to the m-bit counter 208 and the count up / down designation signal 209, the counter output 210 counts up or down in synchronization with the output of the clock generator 206, and the AD converter 102 is ideal. Realize the expected value.

  The comparison means compares the actual measurement value, which is the output 105 of the AD converter 102, with the expected value, and outputs a comparison result. In other words, the actual digital output value of the AD converter 102 obtained as described above and the expected value are compared for each bit using the EX-OR gate 211. However, considering the fact that the actual value and the expected value are deviated at the change point, the data at the change point is adjusted by passing through the flip-flop 213. The result 214 of each bit is further passed through an m-input OR gate 215, so that the output data 216 outputs L if it is a non-defective product and outputs H if it is defective.

  A change in data in each part of the AD converter measurement circuit 102 will be described with reference to the timing chart of FIG. FIG. 2 shows an example in which the AD converter 102 to be measured is an 8-bit AD converter, and Vpp is 2 V, VREFH is 2 V, VREFL is 0 V, 1 LSB is 7.8 mV, and conversion is performed after 2.5 clocks. Further, the DA converter 204 in the AD converter measurement circuit is a 10-bit DA converter, and uses a Vpp of 2V, VREF of 2V, and 1LSB of 1.95 mV.

  2, 205 is a clock signal, 203 is 10-bit DA converter input data, 104 is an input terminal for receiving DA converter output data and inputting AD converter input data, 105 is an 8-bit AD converter output (data), 210 Is an 8-bit counter output (data), 212 is an EX-OR output signal (data), and 214 is an output (data) of the flip-flop 213.

  The digital signal 203 input from the LSI tester is incremented from 0 to 1023 which is the maximum value in 10 bits. Digital (input) -analog (output) conversion is performed by the DA converter 204, and an analog value that increases by 1 LSB, that is, 1.95 mV, is obtained at the input terminal 104 every time the digital input is incremented by one. Since the output voltage of the DA converter 204 is connected to the input of the AD converter 102, the analog value of the input terminal 104 is converted from analog (input) to digital (output) by the AD converter 102. Every time the analog input value increases by 1 LSB of the AD converter 102, that is, 7.8 mV, a digital output incremented by 1 is obtained. However, here, the AD converter 102 having the characteristic of being converted after 2.5 clocks is taken as an example, and since the conversion is performed after waiting for 2.5 clocks, the digital output 105 shown in FIG. 2 is obtained.

  Next, a path for generating the ideal expected value of the AD converter 102 will be described. First, the input clock signal 205 is input to the clock generator 206. Here, because the conversion of the AD converter 102 is performed after 2.5 clocks, the clock of the rising timing is generated after waiting for 2.5 clocks after starting to increment the input of the DA converter 204.

  Thereafter, in this example, 1LSB of the AD converter 102 is 7.8 mV, which is four times 1.95 mV, which is 1LSB of the DA converter 204, so that a clock obtained by dividing the input clock signal by 4 is generated. When the clock generated by the clock generator 206 is input to the m-bit counter 208, an m-bit digital value counter output 210 incremented from 0 is generated at the rising point of the clock. This is an expected value in the AD converter 102.

  The result of comparing the values of the digital output 105 and the counter output 210 using the EX-OR gate 211 is an output signal 212. L is output when the digital output 105 and the counter output 210 are the same, and H is output when they are different. However, an error may occur at a point where data changes in the digital output 105 and the counter output 210. Therefore, by using the flip-flop 213, the error at the change point is removed from the value of the output signal 212, and the result becomes the output (data) 214. The logical sum of the output 214 by the m-bit OR gate 215 becomes the output data 216 of the AD converter measurement circuit 201. When the AD converter 102 is a non-defective product, L is output, and when it is defective, H is output.

The invention according to the first embodiment makes it possible to perform a test using a digital (input) -digital (output) LSI tester in which both input and output are digital values. In addition, it is possible to perform the test by the function test of the logic part, and it is not necessary to apply the analog input using the DC measurement unit compared with the conventional method, and the test by the software calculation is not required. Time can be greatly reduced.
(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIGS. In the invention of the first embodiment, when the AD converter 102 has a high accuracy, operates stably at a low speed, or has a low bit, it can be measured without any problem. There is a problem that if the accuracy is as low as possible, such as a malfunction at the changing point, it will be defective.

 Therefore, the invention of the second embodiment provides an AD converter measurement circuit that corrects the accuracy within the allowable range in order to solve the problems in the first embodiment.

  FIG. 3 is a diagram showing the configuration of the second embodiment of the AD converter measurement circuit according to the present invention.

 In FIG. 3, 401 is an accuracy correction circuit, 402 is a flip-flop, 403 is a flip-flop output, 404 is an AND gate, and 405 is an output of the AND gate. What is newly added to FIG. 1 of the first embodiment is an accuracy correction circuit 401 composed of a flip-flop 402 and an AND gate 404, and the output data 214 of the flip-flop 213 is shifted by one clock by the flip-flop 402. Then, the AND of the input data (214) of the flip-flop 402 and the output data 403 is taken by the AND 404, whereby the output 405 in which the accuracy within the allowable range is corrected can be obtained.

  A change in data in each part of the accuracy correction circuit 401 will be described with reference to a timing chart of FIG. FIG. 4 shows an example of the AD converter 102 and the DA converter 204 that are the same as those in FIG. 2 used in the description of the first embodiment. Assume that outputs of 0 and 2 are obtained when 1 is expected in the AD converter output 105 as shown in FIG. Here, it is assumed that the error in accuracy is within the allowable range of product warranty. In this case, the output 210 of the counter 208 is 1 because it is an expected value, and when compared with the EX-OR gate 211, the EX-OR gate output 212 outputs 1 at a location where the values of the output 105 and the output 210 are different. . The output data 214 is obtained by passing the output 212 through the flip-flop 213. Up to this point, the circuit is the same as that of the first embodiment, but by passing this flip-flop 213 through the flip-flop 402, an output 403 obtained by shifting the data of the output 214 by one clock can be obtained. By considering the logical product of AND 214 and 403 by AND 404, it is possible to obtain an output 405 in which an error within an allowable range is corrected. The logical sum of the m-bit OR gate 215 of the output 405 becomes the output of the AD converter 201, and if the AD converter 102 is a non-defective product considering the guaranteed accuracy of the product, the output data 216 is “0” expected value. L is output as PASS, and H is output if defective.

  Further, by connecting H accuracy correction circuits 401 of the present invention in series, the allowable range can be set to an arbitrary value.

According to the invention of the second embodiment, a test can be performed with an accuracy within an allowable range which is a problem of the invention of the first embodiment.
(Embodiment 3)
A third embodiment of the present invention will be described with reference to FIG. By connecting H precision correction circuits 401 of the invention of the second embodiment in series, the allowable range can be set to an arbitrary value. However, in this method, the number of connections of the accuracy correction circuit 401 must be determined from the time of production of the performance board, and there is a problem that it is not easy to change the allowable range at the evaluation stage.

 Therefore, in the invention of the third embodiment, in order to solve the problems in the second embodiment, the allowable range is adjusted by controlling with an external signal without redesigning the number of connections of the performance board. An AD converter measuring circuit having a function is provided.

FIG. 5 is a diagram showing the configuration of the third embodiment of the AD converter measurement circuit according to the present invention.
FIG. 5 shows the input 214 of the accuracy correction circuit 401 in FIG. 3, where 601 is an accuracy designation signal for designating an allowable range, 602 is an accuracy adjustment circuit, 603 is an accuracy adjustment signal, and 604 is a selector. A configuration newly added to FIG. 3 of the second embodiment is an accuracy adjustment circuit 602, H selectors 604, and H accuracy correction circuits 401. The accuracy adjustment circuit 602 outputs from the accuracy designation signal 601 an accuracy adjustment signal 603 for setting to which input terminal of the H accuracy correction circuits 401 the 214 signals should be connected in order to set the allowable range to be adjusted. . This signal 603 controls the selectors 604 provided at the input portions of the H accuracy correction circuits 401 to connect the required number of accuracy correction circuits 401.

  In order to describe the signal transmission path, the H accuracy correction circuits 401 in FIG. 5 are called correction circuits 1 to H in the order in which the output (signal) 214 is transmitted, and signals are transmitted through the selector 604 between the accuracy correction circuits 401. These are called selectors 1 to H in order. When the precision adjustment circuit 401 controls the selector H to connect the output 214 and the OR gate 215, the output 214 is directly connected to the OR gate 215 without passing through the precision correction circuit 401. This is the first embodiment. A guarantee equivalent to that of FIG. Next, when the selector 214 is controlled to connect the output 214 and the accuracy correction circuit H, and the selector H is controlled to connect the accuracy correction circuit H and the OR gate 215, the output 214 passes through one accuracy correction circuit. Thus, the circuit connected to the OR gate 215 can be assured equivalent to that of FIG. 3 which is the invention of the second embodiment. In order to adjust the allowable range in this way, when J accuracy correction circuits 401 need to be connected, the selector HJ is connected so that the J accuracy correction circuits 401 closer to the output can be connected. When control is performed so that the output 214 is connected to the accuracy correction circuit H-J + 1 and the output from the accuracy correction circuit 401 is controlled to the next stage from the selector H-J + 1 to the selector H, the output 214 is output to the accuracy correction circuit H. The circuit is connected to the OR gate 215 via J accuracy correction circuits 401 from −J + 1 to the accuracy correction circuit H.

  With this structure, the number of accuracy correction circuits 401 to be used in the AD converter measurement circuit can be controlled by designating an allowable range from the outside, so that tests can be performed with an accuracy within an arbitrary allowable range. It becomes.

  According to the invention of the third embodiment, it is possible to test the hardware configuration, which is a problem of the invention of the second embodiment, without redesigning it to an accuracy within an arbitrary allowable range.

  The AD converter measurement circuit of the present invention does not require a DC measurement unit, enables testing of the AD converter using a digital (input) -digital (output) only LSI tester, and shortens the test time. It is effective and useful as an AD converter measurement circuit or the like.

It is a block diagram of the AD converter measuring circuit of 1st Embodiment concerning this invention. It is a timing chart of a 1st embodiment concerning the present invention. It is a block diagram of the AD converter measuring circuit of 2nd Embodiment concerning this invention. It is a timing chart of a 2nd embodiment concerning the present invention. It is a block diagram of the AD converter measuring circuit of 3rd Embodiment concerning this invention. It is explanatory drawing of the measurement of AD converter concerning the conventional measuring method.

Explanation of symbols

101 LSI semiconductor device 102 AD converter (m bits)
103 DC measurement unit 104 Analog input terminal 105 Digital output signal (m bits)
106 Logic Unit 201 AD Converter Measurement Circuit 202 DA Converter Input Terminal (Digital)
203 Digital input signal (n bits)
204 DA converter (n bits)
205 clock 206 clock generator 207 clock frequency determination signal 208 counter (m bits)
209 Count up / down designation signal 210 Counter output (m bits)
211 EX-OR gate 212 EX-OR gate output 213 Flip flop 214 Flip flop output 215 OR gate 216 Output data 401 Accuracy correction circuit 402 Flip flop 403 Flip flop output 404 AND gate 405 AND gate output 601 Accuracy designation signal 602 Accuracy adjustment circuit 603 Accuracy adjustment signal 604 Selector

Claims (3)

  A DA converter that converts a digital signal into an analog signal and inputs the analog signal to an AD converter to be measured; an expected value generation unit that generates an expected value of the output of the AD converter; an actual value that is an output of the AD converter; An AD converter measuring circuit provided with comparing means for comparing values and outputting a comparison result. The AD converter measurement circuit according to claim 1, further comprising: a flip-flop that shifts a comparison result signal; and an accuracy correction circuit that includes an AND gate that receives the comparison result and the output of the flip-flop.   The AD converter measurement circuit according to claim 2, further comprising: H accuracy correction circuits connected in series via a selector; and an accuracy adjustment circuit that controls the selector to control the number of series connection of the accuracy correction circuits.

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