WO2019064460A1

WO2019064460A1 - Signal processing device and testing method

Info

Publication number: WO2019064460A1
Application number: PCT/JP2017/035334
Authority: WO
Inventors: 晴幸倉地
Original assignee: 三菱電機株式会社
Priority date: 2017-09-28
Filing date: 2017-09-28
Publication date: 2019-04-04
Also published as: TW201916598A; DE112017007828T5; JP6537740B1; DE112017007828B4; JPWO2019064460A1; TWI664822B

Abstract

This signal processing device (10) comprises an A/D conversion unit (14), a test signal supply unit (12), a determination unit (15), and an output unit (16). The A/D conversion unit (14) converts an analog signal into a digital signal and outputs the digital signal. The test signal supply unit (12) supplies an analog test signal corresponding to a test bit pattern to the A/D conversion unit (14). When the level of the analog test signal supplied to the A/D conversion unit (14) has switched, the determination unit (15) determines whether test bit values of the digital signal that has been converted and output by the A/D conversion unit (14) differ from before and after the switching of the level of the analog test signal. The output unit (16) outputs the results of the determination by the determination unit (15).

Description

Signal processing apparatus and test method

The present invention relates to a signal processing apparatus and a test method.

In a system in which an analog circuit and a digital circuit are mixed, a converter represented by an AD converter and a DA converter is used to mutually convert an analog signal and a digital signal. In this type of system, if the converter fails, the normal conversion process of the analog signal and the digital signal can not be performed, and as a result, the normal operation of the system becomes difficult. For this reason, it is desirable to accurately detect converter failure.

Various test methods have been proposed to detect transducer failure. For example, Patent Document 1 discloses a technique for detecting the presence or absence of a failure by inputting an analog test signal to an AD converter and determining whether output data is within a predetermined conversion standard value range. Proposed. However, in this test method, it is difficult to detect a fault when the lower output bit of the AD converter is fixed to 1 or 0 without changing and the output data contains small noise. .

Further, Patent Document 2 discloses a technique of inputting a plurality of reference voltages to an AD converter and judging whether the actual output value and the normal output value match. According to this technique, it is also possible to detect an abnormality in which a certain bit of output data of the AD converter is fixed to 0 or 1.

Japanese Patent Application Publication No. 2007-285764 JP-A-8-56160

As described above, in the technique described in Patent Document 1, it is difficult to detect a failure in which some bits of digital data are fixed to 1 or 0.

Further, the technology described in Patent Document 2 detects the abnormality by performing coincidence determination between the actual output value of the AD converter and the normal output value, so although the existence of the abnormality can be detected, the type of the abnormality can not be identified. . For example, when an abnormality occurs in which the value of some bits of data is fixed to 0 or 1, the existence of an abnormality can be detected, but the abnormality is an abnormality in which a part of bits is fixed. In order to identify things, further analysis of the output value is required.

The same problem occurs when testing a DA converter.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to facilitate detection of a type of fault in which the bit value is fixed.

In order to achieve the above object, a signal processing apparatus according to the present invention converts AD signals into digital signals and outputs the converted signals, and supplying means for supplying AD test units with analog test signals corresponding to test bit patterns. When the level of the analog test signal supplied to the AD conversion means is switched, the value of the bit to be tested of the digital signal converted and output by the AD conversion means is before and after the level change of the analog test signal. And determining means for determining whether or not to switch, and output means for outputting the result of the determination by the determining means.

According to the present invention, it is determined whether or not the value of the bit to be tested of the digital signal converted from the analog test signal by the AD conversion means and output is switched before and after the level of the analog test signal is switched. Be done. For this reason, it is possible to determine the occurrence of a type of failure in which the bit value is fixed based on the output value of the AD conversion means without comparing the input value and the output value of the AD conversion means. Therefore, it is possible to easily detect the type of failure in which the bit value is fixed.

Block diagram of the signal processing device according to the first embodiment of the present invention A diagram showing an example of a pattern table stored in the storage unit of FIG. 1 Flow chart of test process performed by the signal processing device according to the first embodiment Diagram showing flags immediately after initialization for changes in flags and their values A diagram showing that all the bit values of the output data of the AD converter have been switched for the change of the flag and its value The figure which shows that the least significant bit of the output data of AD conversion part is fixed to zero about the change of a flag and its value Diagram showing that the least significant bit is fixed to 1 for changes in flags and their values First figure showing another example of the pattern table according to the first embodiment A second diagram showing another example of the pattern table according to the first embodiment. The 3rd figure which shows the other example of the pattern table which relates to the form 1 of execution Block diagram of a signal processing apparatus according to Embodiment 2 of the present invention Flow chart of test process executed by signal processing apparatus according to Embodiment 2 Block diagram of signal processing apparatus according to Embodiment 3 of the present invention Flow chart of test process executed by signal processing apparatus according to the third embodiment Block diagram of a signal processing apparatus according to Embodiment 4 of the present invention Flow chart of operation test process executed by signal processing device according to the fourth embodiment Flow chart of test process executed by signal processing device according to Embodiment 5 of the present invention Block diagram of a signal processing apparatus according to a sixth embodiment of the present invention The figure which shows the example of the pattern table which concerns on Embodiment 7 of this invention. Flow chart of test process executed by signal processing device according to seventh embodiment The block diagram of the signal processing device concerning the embodiment 8 of the invention Block diagram of a signal processing apparatus according to a first modification of the present invention Block diagram of signal processing device according to modification 2 of the present invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1
The signal processing apparatus 10 according to the present embodiment converts an analog signal into a digital signal by using an AD converter and outputs the digital signal, and supplies a test signal to the AD converter. And a test function for performing an operation test of the AD converter by monitoring a change.

Hereinafter, an operation of converting an input analog signal into a digital signal by an AD converter and outputting the digital signal is referred to as a normal operation, and an operation of testing the AD converter is referred to as a test operation. In the following description, the signal may be either a voltage signal or a current signal.

As shown in FIG. 1, the signal processing apparatus 10 operates as an input terminal 101 to which an analog signal is input, an output terminal 102 for outputting a digital signal after conversion, a storage unit 11 which stores data, and A test signal supply unit 12 that generates an analog test signal for test, a selection unit 13 that selects a signal input to the AD conversion unit 14, an AD conversion unit 14 that functions as an AD converter, and an AD conversion unit 14 The determination unit 15 includes a determination unit 15 that determines whether or not there is a failure, and an output unit 16 that outputs information indicating that the AD conversion unit 14 has a failure.

The input terminal 101 is a terminal for externally inputting an analog signal to be converted into a digital signal by the signal processing apparatus 10. For example, a temperature sensor, an illuminance sensor, a speed sensor, another sensor, or a device that outputs an analog signal is connected to the input terminal 101. For example, a direct current voltage in the range of −10 to +10 V or a direct current in the range of 0 to 20 mA is input to the input terminal 101.

The output terminal 102 is a terminal that outputs in parallel the value of each bit of the digital signal converted by the signal processing device 10. An apparatus using an output signal of the signal processing device 10 is connected to the output terminal 102. For example, a 16-bit digital signal indicating an integer included in the range of -32768 to +32767, or a 15-bit digital signal indicating an integer included in the range of 0 to 32767 is output from the output terminal 102, for example.

The storage unit 11 includes, for example, a nonvolatile memory such as an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a flash memory. The storage unit 11 stores various data used by the signal processing device 10. The stored data includes a pattern table 111 for generating an analog test signal for testing the AD conversion unit 14. The storage unit 11 functions as a storage unit in the claims, although not limited thereto.

The pattern table 111 is a list of two predefined test bit patterns. Each test bit pattern is used to determine whether or not the values of the bits making up the digital signal output from the AD conversion unit 14 are switched without being fixed. The pattern table 111 according to the present embodiment is a list of two test bit patterns, as illustrated in FIG. These test bit patterns are determined such that the values of all the bits to be tested are complementary to each other. That is, the value of one test bit pattern is the one's complement of the other test bit pattern.

The test signal supply unit 12 generates an analog test signal corresponding to the test bit pattern at the time of test operation, and supplies the analog test signal to the AD conversion unit 14 via the selection unit 13. The test signal supply unit 12 functions as a supply unit in the claims, although not limited thereto.

More specifically, the test signal supply unit 12 includes a test signal generation module 121. The test signal generation module 121 is configured to include a DA conversion circuit, and generates an analog test signal from the test bit pattern of the pattern table 111. The test signal generation module 121 has a conversion characteristic corresponding to the inverse conversion of the conversion characteristic of the AD conversion unit 14. Based on this conversion characteristic, the test signal generation module 121 generates an analog test signal having a signal level that causes the AD conversion unit 14 to output a digital signal equal to the test bit pattern read from the storage unit 11. The test signal supply unit 12 sequentially reads the test bit pattern from the pattern table 111 to generate an analog test signal. Thereby, the test signal supply unit 12 changes the signal level of the analog test signal, and switches the value of each bit of the digital signal output from the AD conversion unit 14. The test signal supply unit 12 outputs the generated analog test signal to the selection unit 13.

The selection unit 13 selects an analog signal to be A / D conversion supplied from the outside via the input terminal 101 during normal operation and supplies it to the AD conversion unit 14, and is supplied from the test signal supply unit 12 during test operation. The selected analog test signal is supplied to the AD conversion unit 14. In the following description, an analog signal supplied to the input terminal 101 may be referred to as a non-test signal in order to clarify the distinction from the analog test signal.

The AD conversion unit 14 corresponds to an AD conversion circuit. The AD conversion unit 14 outputs, to the output terminal 102 and the determination unit 15, a digital signal obtained by converting the supplied analog signal by discretizing and quantizing the supplied analog signal with a predetermined sampling period and resolution. During normal operation, the AD conversion unit 14 converts a non-test signal supplied from the selection unit 13, that is, an analog signal to be converted supplied from the outside via the input terminal 101 into a digital signal and outputs it. In operation, the analog test signal supplied from the selection unit 13 is converted into a digital signal and output. The digital signal output from the AD conversion unit 14 during the test operation has a value equal to the test bit pattern from which the test signal supply unit 12 generates the supplied analog test signal if the operation is normal. . The AD conversion unit 14 functions as an AD conversion unit in the claims, although not limited thereto.

The determination unit 15 includes an MPU (Micro Processer Unit). When the level of the analog test signal is switched, the determination unit 15 determines whether or not the value of a bit forming a digital signal which is converted from the analog test signal by the AD conversion unit 14 and output is switched. Specifically, the determination unit 15 determines whether the values of the plurality of bits to be tested of the digital signal are different before and after the level of the analog test signal is changed. It is determined whether or not a failure has occurred in which the value is fixed. Since the level of the analog test signal corresponds to the test bit pattern, the determination unit 15 determines whether or not the bit value of the digital signal is switched when the test bit pattern corresponding to the analog test signal is switched. It will be. The determination method will be described later. In order to make this determination, determination unit 15 is provided with a flag constituted by data indicating whether or not the value of each bit constituting the digital signal has been switched. Details of the flag will be described later. Although the determination part 15 is not limited, it functions as a determination means of a claim.

The output unit 16 is configured to include, for example, a network interface controller (NIC), a light emitting diode (LED), or a buzzer for communicating with an external device via a network. The output unit 16 outputs the result of the determination by the determination unit 15. In detail, the output unit 16 outputs information indicating that the AD conversion unit 14 has a failure, when the determination unit 15 determines that a failure in which the value of the bit is fixed has occurred. This information may be data indicating the detailed content of the failure, or may be indicated by the light emission of an LED or the alarm sound of a buzzer. The output unit 16 functions as an output unit of the claims, although not limited thereto.

The control unit 17 includes an MPU, a read only memory (ROM), and a random access memory (RAM). The control unit 17 comprehensively controls each component of the signal processing apparatus 10 by the MPU executing a program stored in the ROM or the storage unit 11 using the RAM as a work area. The control unit 17 may double as the determination unit 15 and the output unit 16.

Subsequently, processing executed by the signal processing device 10 will be described with reference to FIGS. The control unit 17 causes the selection unit 13 to select an analog signal supplied to the input terminal 101 during normal operation of the signal processing device 10. Thereby, the signal processing apparatus 10 converts the analog signal supplied to the input terminal 101 into a digital signal by the AD conversion unit 14 and executes a normal conversion operation to output from the output terminal 102.

On the other hand, the control unit 17 executes the test process shown in FIG. 3 in order to test the operation of the AD conversion unit 14. This test process is started at a predetermined timing.

The following operations are all performed under the control of the control unit 17. However, in order to facilitate understanding, the control unit 17 is not mentioned one by one. In the test process, the signal processing apparatus 10 selects an analog test signal as a signal input to the AD conversion unit 14 (step S1). Specifically, the selection unit 13 selects an analog test signal output from the test signal supply unit 12.

Next, the signal processing device 10 initializes a flag provided in the determination unit 15 (step S2). The flag is data indicating whether or not the value of each bit constituting the digital signal output from the AD conversion unit 14 has been switched. The flag according to the present embodiment is configured as hardware by two latch arrays. However, the method of realizing the flag is not limited to this, and may be realized as a flag field by software.

In the flag initialization process, the value "FFFFh" is substituted into the first latch, and the value "0000h" is substituted into the second latch. FIG. 4A shows the state of the flag immediately after the completion of initialization. "FFFFh" indicates a 16-bit pattern in which all bit values are "1", and indicates that the last "h" is expressed in hexadecimal.

Next, the signal processing apparatus 10 selects the first test bit pattern from the pattern table 111 (step S3). Specifically, the test signal supply unit 12 reads out from the storage unit 11 the first test bit pattern constituting the pattern table 111. For example, the test signal supply unit 12 reads a test bit pattern “11... 11” from the pattern table 111 shown in FIG.

Next, the signal processing apparatus 10 generates an analog test signal of a level corresponding to the selected test bit pattern, and supplies the analog test signal to the AD conversion unit 14 (step S4). Specifically, the test signal generation module 121 of the test signal supply unit 12 generates an analog signal for causing the AD conversion unit 14 to output a digital signal equal to the selected test bit pattern, by DA conversion. For example, in step S4 following the selection of the first test bit pattern of FIG. 2 in step S3, the test signal generation module 121 outputs a digital signal “11... 11” to the AD conversion unit 14 Generate an analog test signal to

Next, the signal processing apparatus 10 updates the flag in accordance with the bit value of the digital signal output from the AD conversion unit 14 (step S5). Specifically, the determination unit 15 updates the value of the first latch array using the result of the AND operation of the output value of the AD conversion unit 14 and the value of the first latch array, and the output value of the AD conversion unit 14 The value of the second latch array is updated using the result of the OR operation with the value of the two latch array. For example, when the analog test signal of the level corresponding to the first test bit pattern in FIG. 2 is generated, the value of the first latch array is the result of the AND operation when the AD conversion unit 14 is operating normally. The value is updated to "FFFFh" and the value of the second latch array is updated to "FFFFh" as a result of the OR operation. However, when the operation of the AD conversion unit 14 becomes abnormal, for example, when the value of the least significant bit is fixed to zero, the value of the first latch array is updated to "FFFEh" as the result of the AND operation and the value of the second latch array is It is updated to "FFFEh" as a result of the OR operation.

Next, the signal processing apparatus 10 determines whether the currently selected test bit pattern is the last test bit pattern (step S6). Specifically, the determination unit 15 determines whether or not the test bit pattern to which the last number is assigned is selected in the pattern table 111.

When it is determined that the test bit pattern is not the last (step S6; No), the signal processing apparatus 10 selects the next test bit pattern (step S7). Specifically, the test signal supply unit 12 reads the test bit pattern with the next number from the pattern table 111 from the storage unit 11. For example, the test signal supply unit 12 reads a test bit pattern “00... 00” as a second test bit pattern next to the first test bit pattern shown in FIG.

Subsequent to step S7, the signal processing device 10 repeats the process of step S4 and subsequent steps. As a result, analog test signals corresponding to the test bit patterns constituting the pattern table 111 are sequentially generated, and the flag is updated each time the level of the analog test signal is changed. For example, when the analog test signal corresponding to the second test bit pattern in FIG. 2 is generated, when the AD converter 14 is operating normally, as shown in FIG. 4B, the first latch array is The value is updated to "0000h" as the result of the AND operation, and the value of the second latch array is updated to "FFFFh" as the result of the OR operation.

Here, when the operation of the AD conversion unit 14 becomes abnormal, for example, when the value of the least significant bit (LSB) is fixed to zero, as shown in FIG. 4C, the value of the first latch array is the result of AND operation “0000h And the value of the second latch array is updated to "FFFEh" as a result of the OR operation. Also, when the value of the least significant bit is fixed to 1, as shown in FIG. 4D, the value of the first latch array is updated to "0001h" as the result of the AND operation and the value of the second latch array is "FFFFh". Updated to As described above, by comparing the value of the first latch array with the value of the second latch array, it is possible to determine a case in which the value of each bit is fixed to 1 and a case in which the value of each bit is fixed to zero.

When it is determined in step S6 that the currently selected test bit pattern is the last test bit pattern (step S6; Yes), the signal processing apparatus 10 performs analog test signals for each of the bits to be tested. It is determined whether or not it has switched before and after the level change (step S8). In other words, the signal processing device 10 determines whether or not the value becomes both 1 and 0 for each bit to be tested. Specifically, determination unit 15 determines whether the value of the first latch array is “0000h” and the value of the second latch array is “FFFFh” as shown in FIG. 4B. It is determined whether the values of the bits to be tested among the bits constituting the digital signal output from the AD conversion unit 14 have different values. For example, when the flag is in the state shown in FIG. 4B, it is determined that all the bit values are switched, and when the flag is in the state shown in FIGS. 4C and 4D, it is determined that the value of the least significant bit is not switched. Ru.

When it is determined that the value of the bit is switched (Step S8; Yes), the signal processing device 10 selects a non-test signal as a signal input to the AD conversion unit 14 (Step S9). Specifically, the selection unit 13 controls the switch element to switch the signal transmission path, and connects the input terminal 101 and the AD conversion unit 14 to select a non-test signal. At this time, the output unit 16 may output information indicating that the AD conversion unit 14 is operating normally. Thereafter, the signal processing device 10 ends the test process.

On the other hand, when it is determined that the value of the bit is not switched (Step S8; No), the signal processing device 10 outputs an error (Step S10). Specifically, the output unit 16 outputs the result of the determination by the determination unit 15. The information output from the output unit 16 includes information indicating that the AD conversion unit 14 has failed, information indicating the position of a bit whose value is fixed among the bits constituting the digital signal, and information fixed. Information may be included that indicates whether the value is one or zero. Thereafter, the signal processing device 10 ends the test process. However, following step S10, the signal processing device 10 may select a non-test signal as the signal input to the AD conversion unit 14.

As described above, the signal processing apparatus 10 determines whether or not the value of each bit of the digital signal output from the AD conversion unit 14 is switched before and after the level of the analog test signal is switched during the test operation. . Therefore, without comparing the input value and the output value of the AD conversion unit 14, it is possible to determine the occurrence of a type of failure in which the bit value of the AD conversion unit 14 is fixed. Therefore, it is possible to easily detect the type of failure in which the bit value is fixed.

In addition, the determination unit 15 uses, as a flag indicating whether each bit is fixed, a first latch array that performs an AND operation and a second latch array that performs an OR operation. This flag has different values depending on whether the bit value is switched or fixed. Therefore, the signal processing apparatus 10 outputs an error only when the value of the bit is fixed. Therefore, regardless of whether or not the actual output value of the AD conversion unit 14 is normal, an error is output when a failure of a type in which the bit value is fixed occurs. As a result, it is possible to improve the detection accuracy of the type of failure in which the bit value is fixed.

The storage unit 11 stores a predetermined test bit pattern, and the test signal supply unit 12 generates an analog test signal of a level corresponding to the test bit pattern. Thus, only by storing the appropriate test bit pattern in advance in the storage unit 11, an appropriate analog test signal can be generated and the test process can be performed.

The storage unit 11 may store the pattern table 111 by various methods. For example, the function of the storage unit 11 may be implemented by an analog circuit designed in advance. In particular, when the width of the test bit pattern is narrow and the number of test bit patterns is small, it becomes relatively easy to realize the function of the storage unit 11 by an analog circuit, and the signal processing device 10 The capacity of the storage element to be configured can be saved or the storage element can be omitted.

Also, the pattern table 111 is not limited to the example shown in FIG. For example, even using the pattern tables 111 shown in FIGS. 5A, 5B, and 5C, the operation of the AD conversion unit 14 can be tested.

The pattern table 111 shown in FIG. 5A has two test bit patterns, similar to the one illustrated in FIG. The bit values of these test bit patterns are in a complementary relationship.

The pattern table 111 shown in FIG. 5B has three test bit patterns. As shown in FIG. 5B, the pattern table 111 having three or more test bit patterns includes, for each bit to be tested, a bit pattern having a value of 1 and a test bit pattern having a value of zero. Including. The same applies to the case where the pattern table 111 has two test bit patterns. In this case, as described above, the bit values are complementary. The pattern table 111 shown in FIG. 5B is an example when the digital signal output from the AD conversion unit 14 is 8 bits, but can be applied regardless of the number of bits of the digital signal.

The test bit patterns shown in FIG. 2 and FIGS. 5A and 5B are test bit patterns for testing all bits of digital data output from the AD conversion unit 14. However, the target of the test may be limited to only some bits of the digital data output from the AD conversion unit 14, for example, the lower 8 bits. In this case, the pattern table 111 may store, for example, two bit patterns complementary only in the lower eight bits as illustrated in FIG. 5C. In this case, only the bit to be tested may be evaluated as the flag.

Second Embodiment
Subsequently, the second embodiment will be described focusing on differences from the above-described first embodiment. The same reference numerals are used for configurations that are the same as or equivalent to those of the first embodiment. In the first embodiment, the test bit pattern stored in storage unit 11 is directly used for the test operation, but in the present embodiment, a plurality of test bit patterns are obtained by arithmetic processing from a plurality of digital data. To generate an analog test signal.

In the present embodiment, as shown in FIG. 6, the storage unit 11 stores a plurality of digital data 112. Each of the digital data 112 is, for example, a bit pattern equal to the test bit pattern constituting the pattern table 111 according to the first embodiment (see FIG. 2).

The test signal supply unit 12 includes an addition module 122. The addition module 122 is configured to include an adder for adding digital values. The addition module 122 reads the digital data 112 from the storage unit 11 and adds an offset value to the value indicated by the digital data 112. The offset value may be a value defined in advance and stored in the auxiliary storage device, or may be a fixed value designed as an addition circuit. Then, the addition module 122 outputs the test bit pattern indicating the sum obtained by the addition to the test signal generation module 121. The test signal generation module 121 generates an analog test signal based on the test bit pattern output from the addition module 122. The addition module 122 functions as adding means of the claims, but not limited thereto.

Subsequently, a test process performed by the signal processing device 10 will be described with reference to FIG. As shown in FIG. 7, in the test process according to the present embodiment, the same processes as steps S1 to S2 according to the first embodiment are executed.

Subsequent to step S2, the addition module 122 reads the first digital data 112 from the storage unit 11 (step S21). If the plurality of digital data 112 is equal to the test bit pattern shown in FIG. 2, the first digital data 112 is equal to the first test bit pattern in FIG. However, the present invention is not limited to this, and the order in which the digital data 112 is read is arbitrary.

Next, the test signal supply unit 12 supplies an analog test signal of a level corresponding to the test bit pattern obtained by adding the offset value to the read digital data 112 (step S22). Specifically, the test signal generation module 121 generates, by DA conversion, an analog signal for causing the AD conversion unit 14 to output a digital signal equal to the test bit pattern output from the addition module 122. Here, if the offset value is zero, the test bit pattern is equal to the digital data 112.

Next, the signal processing device 10 executes step S5 similar to that of the first embodiment. Subsequent to step S5, the signal processing device 10 determines whether the current digital data 112 is the last digital data 112 stored in the storage unit 11 (step S23).

If the determination in step S23 is negative (step S23; No), the addition module 122 reads the next digital data 112 and adds an offset value to generate a new test bit pattern (step S24). This offset value is the same value as the offset value used in step S22 following step S21.

Subsequent to step S24, the signal processing device 10 repeats the processes after step S22. As a result, each time an offset value is added to the digital data 112 to generate a test bit pattern, an analog test signal of a level corresponding to the test bit pattern is generated.

When the determination in step S23 is affirmed (step S23; Yes), the signal processing device 10 executes the processes of steps S8 to S10 similar to those of the first embodiment.

As described above, the test signal supply unit 12 includes the addition module 122, and the test bit obtained by adding the offset value which is a fixed value to the different digital data 112 by the addition module 122, as described above Generate an analog test signal corresponding to the pattern. Thus, the set of test bit patterns used in the test operation can be changed to various ones by simply setting the offset value appropriately. For example, if the digital data 112 is equal to the test bit pattern shown in FIG. 5C, the bit to be tested can be changed simply by changing the offset value. Similarly, even if the digital data 112 is equal to the test bit pattern shown in FIG. 2, the bit to be tested is changed only by changing the offset value, for example, a test bit pattern equal to that shown in FIG. 5C. You can get

Third Embodiment
Subsequently, the third embodiment will be described focusing on differences from the above-described second embodiment. In addition, about the structure the same as that of the said Embodiment 2, or equivalent, an equivalent code | symbol is used. The signal processing device 10 according to the present embodiment is different from that according to the second embodiment in that the adjusting unit 18 is provided as shown in FIG.

In the second embodiment, it is assumed that the AD conversion unit 14 has certain characteristics. However, in actuality, even if the level of the analog signal supplied to the AD conversion unit 14 is constant, the value of the output digital signal may fluctuate due to various factors represented by temperature drift. Such variations may make it difficult to properly detect a fault in which the bit value is fixed. In the signal processing apparatus 10 according to the present embodiment, the above-described fluctuation is compensated by the adjustment unit 18, and a digital signal suitable for the operation test is output to the AD conversion unit 14. Hereinafter, the signal processing device 10 according to the present embodiment will be described.

The adjustment unit 18 is realized by the MPU. The adjustment unit 18 adjusts the offset value so that the difference between the value indicated by the test bit pattern output from the addition module 122 and the value of the digital signal output from the AD conversion unit 14 becomes zero. . Specifically, the adjustment unit 18 is a test bit pattern to which the offset value is added, and a value of a digital signal converted and output from the analog test signal corresponding to the test bit pattern by the AD conversion unit 14. ,. Then, the adjustment unit 18 causes the AD conversion unit 14 to output a digital signal equal to the initial test bit pattern by correcting the offset value so that the difference becomes 0 based on the comparison. The adjustment unit 18 functions as an adjustment unit in the claims, although not limited thereto.

Subsequently, processing executed by the signal processing device 10 will be described with reference to FIG. As shown in FIG. 9, in the test process according to the present embodiment, the same processes as steps S1 to S2 and S21 to S22 according to the second embodiment are executed.

Subsequent to step S22, the signal processing apparatus 10 determines whether the difference between the current test bit pattern and the value of the digital signal output from the AD conversion unit 14 is equal to or greater than a threshold (step S31). Specifically, the AD conversion unit 14 converts the adjustment unit 18 from the value indicated by the test bit pattern output from the addition module 122 and the analog test signal generated based on the test bit pattern. It is determined whether the difference between the value of the digital signal output and the value of the digital signal output is equal to or greater than a predetermined threshold value. The threshold may be zero or a non-zero value.

When it is determined that the difference is not equal to or more than the threshold (Step S31; No), the signal processing device 10 shifts the processing to Step S5. On the other hand, when it is determined that the difference is equal to or more than the threshold (step S31; Yes), the signal processing device 10 adjusts the offset value so as to reduce the difference (step S32). Specifically, the adjustment unit 18 subtracts the difference obtained by subtracting the value of the test bit pattern output from the addition module 122 from the value of the digital signal output from the AD conversion unit 14 from the offset value. Thus, the offset value is corrected.

After that, the signal processing apparatus 10 executes the process of step S5 and subsequent steps as in the second embodiment.

As described above, the signal processing apparatus 10 includes the adjustment unit 18 that adjusts the offset value. By the adjustment unit 18 adjusting the offset value, the AD conversion unit 14 outputs a digital signal suitable for the test, and the signal processing apparatus 10 accurately determines whether the bit value is fixed or not. It can be diagnosed.

Fourth Embodiment
Subsequently, the fourth embodiment will be described focusing on differences from the above-described first embodiment. The same reference numerals are used for configurations that are the same as or equivalent to those of the first embodiment. The signal processing device 10 according to the present embodiment is different from that according to the first embodiment in that the signal processing device 10 according to the present embodiment includes a timer 19 for periodically executing a test process, as shown in FIG.

In the first embodiment, an analog test signal different from the non-test signal input from the input terminal 101 of the signal processing device 10 is supplied to the AD conversion unit 14 for the operation test of the AD conversion unit 14. In the midst of the above, the signal processing device 10 could not exhibit its original function. However, when the switching of the bit value of the digital signal output from the AD conversion unit 14 can be confirmed in the state where the non-test signal is supplied, it is not necessary to perform the operation test. Hereinafter, an example in which the periodic test process is omitted in such a case will be described with reference to FIGS.

The timer 19 is configured to include a quartz oscillator or an oscillation circuit. The timer 19 outputs a trigger signal indicating the start time of the test to the test signal generation module 121 at a constant cycle. The constant cycle is, for example, 8 hours, 24 hours, or 1 week, but is not limited thereto, and may be any length.

Subsequently, the operation test process executed by the signal processing device 10 will be described with reference to FIG. The operation test process may be started by turning on the power of the signal processing apparatus 10, or may be started when instructed by the user of the signal processing apparatus 10.

In the operation test process, the signal processing device 10 selects a non-test signal as a signal input to the AD conversion unit 14 (step S41). Next, the signal processing device 10 executes flag initialization processing (step S42). This initialization process is equivalent to the initialization process of step S2 according to the first embodiment shown in FIG.

Next, the signal processing device 10 updates the flag in accordance with the bit value of the digital signal output from the AD conversion unit 14 in response to the level of the non-test signal (step S43). Specifically, the determination unit 15 updates the value of each of the two latch arrays using the value of the digital signal that is converted from the non-test signal by the AD conversion unit 14 and output. More specifically, the determination unit 15 updates the value of the first latch array using the result of the AND operation of the output value of the AD conversion unit 14 and the value of the first latch array, and the output value of the AD conversion unit 14 The value of the second latch array is updated using the result of the OR operation with the value of the two latch array.

Next, the signal processing apparatus 10 determines whether the current time is the start time of the test process (step S44). Specifically, the test signal supply unit 12 determines whether or not the trigger signal is output from the timer 19.

When it is determined that it is not the start time of the test process (Step S44; No), the signal processing device 10 repeatedly executes the process after Step S43. Thus, the flag is repeatedly updated using the digital signal output from the AD converter 14 based on the non-test signal. Usually, since the level of the non-test signal changes from moment to moment, the flag is updated based on a plurality of levels.

On the other hand, when it is determined that it is the start time of the test process (step S44; Yes), the signal processing apparatus 10 determines whether or not the level of the non-test signal has changed before and after the change for each bit to be tested. Is determined (step S45). In other words, the signal processing apparatus 10 determines whether the value becomes both 1 and 0 for each bit to be tested. Specifically, determination unit 15 determines whether the value of the first latch array is “0000h” and the value of the second latch array is “FFFFh” as shown in FIG. 4B. It is determined whether the value of each of the bits to be tested among the bits constituting the digital signal output from the AD conversion unit 14 has been switched.

When the determination in step S45 is affirmed (step S45; Yes), the signal processing device 10 shifts the process to step S42 without executing the test process (step S46). Thus, the operation test using the non-test signal is repeatedly performed.

On the other hand, when determination of step S45 is denied (step S45; No), the signal processing apparatus 10 performs a test process (step S46). This test process is equivalent to the series of processes shown in FIG.

Next, the signal processing apparatus 10 determines whether or not there is an error output in the test process of step S46 (step S47). When it is determined that there is no error output (Step S47; No), the signal processing device 10 repeats the processes after Step S42. On the other hand, when it is determined that there is an error output (step S47; Yes), the signal processing device 10 ends the operation test process.

As described above, the test signal supply unit 12 periodically generates an analog test signal and supplies the analog test signal to the AD conversion unit 14. For this reason, test processing is performed regularly. Therefore, when the AD converter 14 fails, this failure can be detected in a relatively short time.

In addition, the determination unit 15 determines whether or not the value of the bit making up the digital signal converted and output from the non-test signal by the AD conversion unit 14 switches, and the test signal supply unit 12 generates the non-test signal. If it is determined that the bit value has been switched based on the generation of the next analog test signal is omitted. Thereby, the failure of the AD converter 14 can be detected from the non-test signal. In addition, the execution of the test process can be omitted to reduce the load on the test of the signal processing device 10.

Embodiment 5
Subsequently, the fifth embodiment will be described focusing on differences from the above-described fourth embodiment. In addition, about the structure the same as that of the said Embodiment 4, or equivalent, an equivalent code | symbol is used. Since the test process according to the fourth embodiment is the same as that of the first embodiment, the same reference numerals as those of the first embodiment are used for the test process.

In the test process according to the fourth embodiment, as in the first embodiment, analog test signals at levels corresponding to the plurality of test bit patterns are sequentially generated. However, when it is possible to confirm switching of a part of bit values to be tested in a state where a non-test signal is supplied to the AD conversion unit 14, a test bit pattern for switching the bit values There is no need to generate an analog test signal using. Therefore, in the test process, one or a plurality of bits which can not confirm the switching of bit values based on the non-test signal may be intensively tested. Below, such a test process is demonstrated.

As shown in FIG. 12, in the test process according to the present embodiment, step S1 similar to that of the first embodiment is performed. Next, the signal processing device 10 refers to the flag (step S51). Specifically, the test signal generation module 121 refers to the values of the first latch array and the second latch array.

Next, the signal processing apparatus 10 selects a first test bit pattern corresponding to a value not output from the AD conversion unit 14 based on the non-test signal (step S52). Specifically, the test signal generation module 121 extracts one or more test bit patterns to be tested from the pattern table 111 from the values of the first latch array and the second latch array, and extracts the extracted test bit patterns. Select the first test bit pattern among them.

Here, the value is switched for a bit in which the value of the first latch array changes from 1 which is the initial value to zero and the value of the second latch array changes from 0 which is the initial value to 1 Have already been diagnosed. Therefore, the test bit pattern to be tested is a test bit pattern for testing the switching of bits other than such diagnosed bits. In other words, it can be said that the test bit pattern to be tested is obtained by excluding the test bit pattern for testing a diagnosed bit from the pattern table 111. For example, in the example shown in FIG. 5B, if the lower 2 bits are already diagnosed, it is not necessary to test using the first test bit pattern, so the second and third test bit patterns are test signals. It is extracted by the generation module 121. Such extraction of test bit patterns is achieved by extracting one test bit pattern in which the value is 1 for each undiagnosed bit and one test bit pattern in which the value is zero. With regard to the diagnosed bits, the value of the extracted test bit pattern may be either 1 or 0, and the use of the test bit pattern for outputting both 1 and 0 is omitted.

Subsequent to step S52, the signal processing device 10 executes steps S4 to S10 similar to those of the first embodiment. However, the last test bit pattern in step S6 means the last test bit pattern among the test bit patterns extracted in step S52. Further, the next test bit pattern in step S7 means the next test bit pattern when selecting the test bit pattern extracted in step S52 in order from the smaller number.

As described above, based on both the analog test signal and the non-test signal, the determination unit 15 determines whether or not the value of the bit forming the digital signal output from the AD conversion unit 14 is switched. . Further, the test signal supply unit 12 generates an analog test signal by excluding the test bit pattern for which the test becomes unnecessary by the determination of the determination unit 15 based on the non-test signal. Therefore, when the value of the non-test signal includes a value corresponding to the test bit pattern constituting the pattern table, the test signal supply unit 12 generates an analog test signal based on the test bit pattern. It will be omitted. In other words, the test signal supply unit 12 determines the switching of all the test target bits among the plurality of test bit patterns by the determination based on the non-test signal. Supply of analog test signal corresponding to test bit pattern is omitted. This can reduce the time required for test processing.

In the present embodiment, a part of the test bit patterns is extracted from the pattern table 111 by referring to the flag, but the present invention is not limited to this. For example, by recording the value of the non-test signal and excluding the test bit pattern corresponding to the recorded value, a part of the test bit patterns may be extracted from the pattern table 111.

Sixth Embodiment
Subsequently, the sixth embodiment will be described focusing on differences from the above-described first embodiment. The same reference numerals are used for configurations that are the same as or equivalent to those of the first embodiment. The signal processing device 10 according to the present embodiment differs from that according to the first embodiment in that two AD converters are provided as shown in FIG.

In the first embodiment, one test circuit including the test signal supply unit 12 and the determination unit 15 is arranged for one AD converter, but a common test circuit is used for a plurality of AD converters. By arranging, the operation test may be efficiently performed in a compact configuration. In the following, an example in which one test circuit is arranged for two AD converters will be described.

The signal processing apparatus 10 includes an input terminal 103 to which a signal is input from the outside, an output terminal 104 for outputting a signal to the outside, and an AD conversion unit 142 functioning as an AD converter.

The input terminal 103 and the output terminal 104 are configured to be equivalent to the input terminal 101 and the output terminal 102, respectively. As a result, the analog signal of two channels is input to the signal processing device 10, and the digital signal of two channels is output from the signal processing device 10.

The selection unit 13 selects a signal input to the AD conversion unit 142 from an analog test signal and a signal input from the input terminal 103, and supplies the selected signal to the AD conversion unit 142.

The AD conversion unit 142 outputs a digital signal obtained by converting the input signal to the output terminal 104 and the determination unit 15. The operation test of the

AD conversion units

14 and 142 may be performed separately. In this case, the selection unit 13 selects one of the AD conversion unit 14 and the AD conversion unit 142 to supply an analog test signal. The test signal supply unit 12 switches and supplies the analog test signal to the AD converter 14 and the AD converter 142. Then, the operation test of the AD conversion unit 142 is performed at a timing different from the operation test of the AD conversion unit 14. In addition, the operation test of the

AD conversion units

14 and 142 may be performed simultaneously. In this case, the determination unit 15 executes two tests in parallel. When the two tests are executed in parallel, the first latch array and the second latch array for diagnosing the output from the AD conversion unit 14, the third latch array for diagnosing the output from the AD conversion unit 142, and A fourth latch array is used.

The output unit 16 is configured as in the first embodiment. The information output from the output unit 16 according to the present embodiment may include information indicating which one of the

AD converters

14 and 142 has failed.

As described above, the signal processing apparatus 10 includes the

AD conversion units

14 and 142, and it is determined whether or not the value of the bit forming the digital signal output from these converters is fixed. . Thus, even when any of the two

AD conversion units

14 and 142 fails, the failure can be detected.

In the present embodiment, the two

AD conversion units

14 and 142 have been described as an example, but even if the number of AD converters is three or more, a failure may be detected as in the present embodiment. it can.

Embodiment 7
Subsequently, a seventh embodiment will be described focusing on differences from the above-described first embodiment. The same reference numerals are used for configurations that are the same as or equivalent to those of the first embodiment. The signal processing device 10 according to the present embodiment differs from that according to the first embodiment in that a pattern table 111 shown in FIG. 14 is used.

In the first embodiment, an example in which a failure is detected by independently testing for each bit that the bit value of the digital signal output from the AD conversion unit 14 is switched has been described. However, the failure of the AD converter includes an abnormality in which the value of the output bit interlocks with the change of the adjacent bit. If such an error is detected, it is possible to further improve the detection accuracy of the failure of the AD converter. Hereinafter, an example of detecting an abnormal state in which bit values are interlocked will be specifically described.

As shown in FIG. 14, all of the test bit patterns constituting the pattern table 111 according to the present embodiment are bit patterns in which the value of any one bit is different from the value of the other bits. In the case of testing the operation of the AD conversion unit 14 using the pattern table 111, the test signal supply unit 12 performs a test in the order in which the positions of bits having values different from other bits advance one by one. An analog test signal corresponding to the bit pattern will be generated. In the example shown in FIG. 14, only one bit of the bit pattern whose value is 1 is carried up from the least significant bit, and then only one bit of the bit pattern whose value is zero. Analog test signals are generated such that the digit is incremented from the least significant bit one by one.

Subsequently, a test process performed by the signal processing device 10 will be described with reference to FIG. In this test process, processes similar to steps S1 to S8 of the test process according to the first embodiment shown in FIG. 3 are performed. However, in addition to the first latch array and the second latch array, flags used in this test process include flag data indicating whether or not switching of bit values affected by other bit values has occurred. The flag data may be implemented on hardware by a latch circuit or may be implemented as a flag field on software.

In step S5, the signal processing device 10 updates the flag including the flag data. Specifically, determination unit 15 determines whether or not the test bit pattern selected from pattern table 111 is equal to the value of the digital signal output from AD conversion unit 14 every time step S5 is performed. To Then, if these values are different, the determination unit 15 determines the position of the bit that is only 1 or 0 among the test bit patterns selected from the pattern table 111 and the bit that has a value equal to this bit The flag data is updated by adding the data indicating the position of and as the data indicating the abnormality associated with the bit value.

When the determination in step S8 is affirmed (step S8; Yes), the signal processing apparatus 10 determines whether interlocking of bit values has occurred (step S71). Specifically, the determination unit 15 refers to the flag data and determines whether the flag data includes data indicating an abnormality such that the value of one bit is linked to the value of another bit.

When it is determined that interlocking of bit values has not occurred (step S71; No), the signal processing device 10 shifts the processing to step S9. On the other hand, when it is determined that interlocking of bit values has occurred (step S71; Yes), the signal processing device 10 outputs an error (step S10). The information output in step S10 after the determination in step S71 is affirmed includes information on an abnormality in which the bit value is interlocked. The information on the abnormality may include information indicating that an abnormality has occurred and information indicating the position of the interlocking bit.

As described above, in the signal processing apparatus 10, in addition to the detection of the failure in which the bit value is fixed, the value of one of the bits constituting the digital signal output from the AD conversion unit 14 is another bit. It is possible to detect an abnormality that works in conjunction with the Such anomalies can be caused, for example, by crosstalk noise.

For example, an abnormality may occur in the digital signal output from the AD conversion unit 14 such that the second least significant bit always has the same value as the least significant bit. In the case where such an abnormality occurs, when the pattern table 111 shown in FIG. 2 is used, when the first test bit pattern is selected, the AD conversion unit 14 outputs a digital “11... 11”. A signal is output, and when the second test bit pattern is selected, the AD conversion unit 14 outputs a digital signal "00... 00". As a result, it is not possible to detect an abnormality in which bit values are interlocked.

On the other hand, by using the pattern table 111 according to the present embodiment, in addition to the failure in which the value of the bit is fixed, the abnormality in which the value of the bit interlocks with the change in the value of the adjacent bit is detected. It will be possible. Therefore, the detection rate of the failure generated in the AD conversion unit 14 can be improved.

In the present embodiment, the analog test signal is generated such that the position of the only zero or one bit in the bit pattern advances one by one, but is not limited thereto. For example, the analog test signal may be generated such that the position of the only zero or one bit of the bit pattern advances downward one by one. That is, the test signal supply unit 12 may supply the analog test signal corresponding to the test bit pattern to the AD conversion unit 14 so that the position of the bit that is only 1 or 0 changes one by one.

Eighth Embodiment
Subsequently, an eighth embodiment will be described focusing on differences from the above-described first embodiment. The same reference numerals are used for configurations that are the same as or equivalent to those of the first embodiment. A signal processing device 30 according to the present embodiment differs from the signal processing device 10 according to the first embodiment in that the signal processing device 30 according to the present embodiment has a DA converter and performs an operation test of the DA converter as shown in FIG. ing.

In the first embodiment, a fault is detected in which the value of the bit of the digital signal output from the AD converter is fixed. On the other hand, in the case of a DA converter, the input value is fixed to 1 or zero and is not recognized correctly, and even if the bit value of the input digital signal changes, a fault may occur that does not affect the output value. In the following, an example of detecting a type of failure in which such a bit value is fixed will be described.

The signal processing device 30 has a D / A converter that converts a digital signal into an analog signal and outputs the signal, and outputs an analog signal obtained by converting a digital signal input from the outside by the D / A converter to the outside. Prepare. In addition, the signal processing device 30 performs an operation test of the DA converter by monitoring an output value when the test signal is supplied to the DA converter, and when the DA converter breaks down, detects the fault accurately. It has a function.

The signal processing device 30 includes an input terminal 301 to which a digital signal is externally input, an output terminal 302 for outputting an analog signal to the outside, a storage unit 31 storing various data, and an operation of the DA conversion unit 34. A test signal supply unit 32 that generates a digital test signal for testing the test data and supplies the digital test signal to the DA conversion unit 34, a selection unit 33 that selects a signal input to the DA conversion unit 34, and a DA that functions as a DA converter The conversion unit 34, an AD conversion unit 35 that performs AD conversion on the analog signal output from the DA conversion unit 34, a determination unit 36 that determines whether the DA conversion unit 34 is broken, and the DA conversion unit 34 And an output unit 37 configured to output information indicating that a failure has occurred. The DA conversion unit 34 functions as a DA conversion unit in the claims, although not limited thereto.

The input terminal 301 is a terminal for inputting in parallel the value of each bit of the digital signal of one channel. The input terminal 301 is connected to a sensor or a device that outputs a digital signal. For example, a 16-bit digital signal indicating an integer included in the range of -32768 to +32767 is input to the input terminal 301.

The output terminal 302 is a terminal for outputting an analog signal of one channel. The output terminal 302 is connected to an actuator or a device that uses a signal output from the signal processing device 30. From the output terminal 302, for example, a DC voltage in the range of -10 to +10 V is output as an analog signal.

The storage unit 31 is configured the same as the storage unit 11 according to the first embodiment, and stores the pattern table 311 similar to the pattern table 111 according to the first embodiment.

The test signal supply unit 32 sequentially reads the test bit pattern of the pattern table 311 from the storage unit 31 and outputs the read test bit pattern to the selection unit 33 as a digital test signal.

The selection unit 33 is configured to include a switch element. The selection unit 33 selects a signal input to the DA conversion unit 34 from a digital test signal and an analog signal input from the input terminal 301, and outputs the selected signal to the DA conversion unit 34. Hereinafter, a signal selected by the selection unit 33 as a signal different from the digital test signal will be appropriately described as a non-test signal.

The DA conversion unit 34 corresponds to a so-called DA conversion circuit. The DA converter 34 outputs an analog signal obtained by converting the supplied digital signal to the output terminal 302 and the AD converter 35. The AD conversion unit 35 corresponds to a so-called AD conversion circuit. The AD conversion unit 35 converts the analog signal output from the DA conversion unit 34 into a digital signal and outputs the digital signal to the determination unit 36.

The determination unit 36 and the output unit 37 are configured in the same manner as the determination unit 15 and the output unit 16 according to the first embodiment, respectively.

The determination unit 36 includes an MPU (Micro Processer Unit), and is configured in the same manner as the determination unit 15 according to the first embodiment. Specifically, the determination unit 36 determines whether or not the value of the bit forming the digital signal converted and output from the digital test signal by the DA conversion unit 34 and the AD conversion unit 35 is switched. More specifically, the determination unit 36 determines whether the values of the plurality of bits to be tested of the digital signal are different before and after the value of the digital test signal is changed. It is determined whether or not a failure has occurred in which the value is fixed. As in the first embodiment, the determination unit 36 updates the value of the first latch array with the result of the AND operation of the value of the first latch array and the output value of the AD conversion unit 35, and the value of the second latch array and the AD conversion By updating the value of the second latch array with the result of the OR operation with the output value of the unit 35, it is possible to determine the presence or absence of a failure.

The output unit 37 is configured in the same manner as the output unit 16 according to the first embodiment. The output unit 16 outputs information indicating that the DA conversion unit 34 has a failure, when it is determined by the determination unit 36 that a failure has occurred in which the value of the bit is fixed. This information may be data indicating the detailed content of the failure, or may be indicated by the light emission of an LED or the alarm sound of a buzzer.

The control unit 38 is configured to include an MPU, a ROM, and a RAM, and centrally controls each component of the signal processing device 30.

As described above, the signal processing apparatus 30 can supply a digital test signal to the DA converter 34 and determine whether the digital test signal is correctly recognized by the DA converter 34. Specifically, the output value of the AD conversion unit 35 is monitored to determine whether or not the value of the bit constituting the input signal interpreted by the DA conversion unit 34 is switched. Can be detected.

It should be noted that although it is possible to detect that the DA conversion unit 34 has a failure when the AD conversion unit 35 is operating normally, when the AD conversion unit 35 has a failure, it should be distinguished from the failure of the DA conversion unit 34. Is difficult. Therefore, by monitoring the analog signal output from the DA converter 34 and input to the AD converter 35, it may be determined which of the DA converter 34 and the AD converter 35 has a failure.

In the second to seventh embodiments, an example has been described in which the detection of the failure of the AD converter according to the first embodiment is modified. However, the detection of the failure of the DA converter according to the present embodiment is the embodiment It can be modified as described in 2-7. For example, when the modification described in the third embodiment is performed, the offset value is corrected so that the difference between the test bit pattern stored in storage unit 11 and the output value of AD conversion unit 35 is reduced. Just do it.

As mentioned above, although embodiment of this invention was described, this invention is not limited by the said embodiment.

For example, in the above embodiment, the

signal processing devices

10 and 30 merely convert and output the input signal, but the present invention is not limited to this. For example, as illustrated in FIG. 17, the signal processing unit 191 performs signal processing on the signal input from the input terminal 101 and outputs the processing result to the selection unit 13 as a non-test signal; The signal processing unit 192 may perform signal processing on the signal output from the conversion unit 14 and output a processing result to the output terminal 102. Further, the signal processing unit 10 may be configured by omitting any one of the signal processing unit 191 and the signal processing unit 192. Similarly, the signal processing unit 30 may be provided with a signal processing unit.

Further, as shown in FIG. 18, the signal processing apparatus 10 outputs an information based on a signal source for generating a non-test signal instead of the input terminal 101 and the output terminal 102, and an output of the AD conversion unit 14. And a part 194. Similarly, the signal processing device 30 may be provided with a signal source and an output unit that outputs information based on the output of the DA conversion unit 34.

In the above embodiment, the width of the test bit pattern forming the pattern table 111 is equal to the bit width of the digital signal output from the AD conversion unit 14, and the width of the test bit pattern forming the pattern table 311 Is described as being equal to the bit width of the digital signal input to the DA conversion unit 34, but is not limited thereto. The width of the test bit pattern stored in the

storage units

11 and 31 may be equal to the width of the bit to be tested among the input or output digital signals. For example, if the lower 8 bits are to be tested, the width of the test bit pattern may be 8 bits.

Also, the functions of the

signal processing devices

10 and 30 can be realized by dedicated hardware or by a normal computer system.

For example, the program executed by the

control units

17 and 38 may be stored in a computer readable recording medium and distributed, and the program may be installed in a computer to configure an apparatus that executes the above-described processing. .

Alternatively, the program may be stored in a disk device of a server device on a communication network represented by the Internet, for example, superimposed on a carrier wave and downloaded to a computer.

The above-described processing can also be achieved by executing the program while transferring it via the communication network.

Furthermore, the processing described above can be achieved by executing all or a part of the program on the server device and executing the program while transmitting and receiving information related to the processing via the communication network.

When the OS (Operating System) shares and realizes the above functions, or when the OS and an application cooperate to realize it, etc., only the part other than the OS may be stored and distributed in the medium. You can also download it to your computer.

Further, the means for realizing the functions of the

signal processing devices

10 and 30 is not limited to software, and part or all of the means may be realized by dedicated hardware including a circuit.

The present invention is capable of various embodiments and modifications without departing from the broad spirit and scope of the present invention. In addition, the embodiment described above is for describing the present invention, and does not limit the scope of the present invention. That is, the scope of the present invention is indicated not by the embodiments but by the claims. And, various modifications applied within the scope of the claims and the meaning of the invention are considered to be within the scope of the present invention.

The invention is suitable for the detection of converter failures.

10, 30 signal processing unit, 11, 31 storage unit, 111, 311 pattern table, 112 digital data, 12, 32 test signal supply unit, 122 addition module, 121, 321 test signal generation module, 13, 33 selection unit, 14 , 142, 35 AD conversion unit, 15, 36 determination unit, 16, 37 output unit, 17, 38 control unit, 18 adjustment unit, 19 timer, 34 DA conversion unit, 101 input terminal, 102 output terminal, 103 input terminal, 104 output terminal, 191, 192 signal processing unit, 193 signal source, 194 output unit, 301 input terminal, 302 output terminal.

Claims

AD conversion means for converting an analog signal into a digital signal and outputting it;
Supply means for supplying an analog test signal corresponding to a test bit pattern to the AD conversion means;
When the level of the analog test signal supplied to the AD conversion means is switched, the value of the bit to be tested of the digital signal converted and output by the AD conversion means is the switch of the level of the analog test signal Determining means for determining whether or not to switch before and after
An output unit that outputs the result of the determination by the determination unit;
A signal processing apparatus comprising:
The supply means is
Storage means for storing a plurality of predetermined digital data;
And adding means for obtaining the test bit pattern by adding an offset value to the plurality of digital data stored in the storage means.
Supplying the analog test signal corresponding to the test bit pattern obtained by the addition unit to the AD conversion unit;
The signal processing device according to claim 1.
The circuit further comprises adjusting means for adjusting the offset value so that the difference between the test bit pattern output from the adding means and the digital signal output from the AD converting means is reduced.
The signal processing device according to claim 2.
The test bit pattern is composed of a plurality of bit patterns,
Each of the plurality of bit patterns is a bit pattern in which the value of any one bit is different from the value of the other bits,
The supply means supplies an analog test signal corresponding to the test bit pattern to the AD conversion means so that the position in the bit pattern of the one bit changes one by one.
The signal processing device according to claim 1.
The supply means periodically supplies the analog test signal.
The signal processing apparatus according to any one of claims 1 to 4.
The determination means determines that the value of the bit to be tested of the digital signal converted and output by the AD conversion means from the non-test signal different from the analog test signal changes the level of the non-test signal Determine whether to switch at
The supply means omits generation of the next analog test signal when it is determined by the determination means that the value of the bit to be tested is switched based on the non-test signal.
The signal processing device according to claim 5.
The determination means determines that the value of the bit to be tested of the digital signal converted and output by the AD conversion means from the non-test signal different from the analog test signal changes the level of the non-test signal Determine whether to switch at
The supply means corresponds to the test bit pattern corresponding to the test bit pattern for which switching of all test target bits among the plurality of test bit patterns can be confirmed by the determination based on the non-test signal. Omit supply of analog test signal,
The signal processing apparatus according to any one of claims 1 to 4.
It further comprises another AD conversion means different from the AD conversion means for converting an analog signal into a digital signal and outputting it.
The supply means switches and supplies the analog test signal to the AD conversion means and the other AD conversion means.
The signal processing apparatus according to any one of claims 1 to 7.
DA conversion means for converting a digital signal into an analog signal and outputting it;
AD conversion means for converting an analog signal output from the DA conversion means into a digital signal;
Supply means for changing the value of the digital test signal while supplying the digital test signal to the DA conversion means;
The values of the plurality of bits to be tested of the digital signal converted from the digital test signal by the DA conversion unit and the AD conversion unit are all changed by the supply unit. Determining means for determining whether or not to switch between before and after being changed;
An output unit that outputs the result of the determination by the determination unit as a result of the test;
A signal processing apparatus comprising:
An operation test method of AD conversion means for converting an analog signal into a digital signal and outputting the digital signal,
Supplying the analog test signal to the AD conversion means while changing the level of the analog test signal;
The values of a plurality of bits to be tested of the digital signal converted and output from the analog test signal by the AD conversion means are all before and after the level of the analog test signal is changed. A determination step of determining whether or not to switch;
Test methods including:
An operation test method of DA conversion means for converting a digital signal into an analog signal and outputting it,
Supplying the digital test signal to the DA conversion means while changing the value of the digital test signal;
A plurality of bits to be tested of the digital signal converted and output from the digital test signal by the DA conversion unit and an AD conversion unit converting the analog signal output from the DA conversion unit into a digital signal A determination step of determining whether or not any of the values of the digital test signal is switched before and after the value of the digital test signal is changed;
Test methods including: