JP2012010072A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve precise A/D conversion.SOLUTION: In the A/D converter of the present invention, a digital value which represents an intermediate voltage of a power supply to a DAC2 is stored as an initial value in a register 1. The DAC2 converts the digital value of the register 1 into a voltage, and outputs it as an output voltage. A circuit 3 subtracts an analog input voltage from and then adds the output voltage to the intermediate voltage of the power supply to output the voltage as an input voltage to a comparator 5. In a memory 45, multiple setting voltages (digital preset values) and correction voltages (correction values) including errors of the DAC2 are stored. A circuit 44 outputs the correction value corresponding to the digital value of the register 1 as a selected correction value by making reference to the memory 45. A circuit 42 outputs the correction voltage as a common voltage, which is represented by the selected correction value. The comparator 5 compares the input voltage with the common voltage, and outputs the comparison result. An output control section 6 stores a following digital value in the register 1 based on the comparison result.

Description

  The present invention relates to an A / D converter that performs A (analog) / D (digital) conversion.

  FIG. 1 shows a configuration of a technique described in Japanese Patent Application Laid-Open No. 2008-103813 as a conventional A / D converter.

  A conventional A / D converter includes a comparator 101, a successive approximation register 102, a D / A converter 103, an offset value generation unit 104, an offset information storage register 105, and an offset information storage ROM as a nonvolatile storage unit. (Read Only Memory) 107.

  The successive approximation register 102 has storage areas b0 to b9 for 10 bits.

  The comparator 101 is supplied with the analog input voltage V1.

  As shown in FIG. 2, the offset information storage ROM 107 stores four patterns of 2-bit digital values and offset adjustment values for offset correction according to the range of the analog input voltage V1. Here, the digital values of the four patterns are “00, 01, 10, 11”, whereas the offset adjustment values of the four patterns are “+1, −1, −1, +1”. The four patterns of digital values “00, 01, 10, 11” and offset adjustment values “+1, −1, −1, +1” stored in the nonvolatile storage unit 107 are stored in the offset information storage register 105 when the power is turned on. Stored.

  The D / A converter 103 includes a voltage generator 103a and a reference voltage generator 103b. The voltage generation unit 103a generates a plurality of voltages by a resistance element connected in series between the first and second power supplies. The reference voltage generation unit 103b outputs an intermediate voltage among the plurality of voltages to the comparator 101 as the first reference voltage Vref.

  The comparator 101 compares the analog input voltage V1 with the i-th reference voltage Vref (i is an integer satisfying 1 ≦ i ≦ 10), and outputs the comparison result as the i-th comparison result. Here, the i-th comparison result is stored as the i-th digital value “1” or “0” in the i-th storage area of the successive approximation register 102.

  The offset value generation unit 104 stores the first and second bit storage areas of the successive approximation register 102 from the four patterns of offset adjustment values “+1, −1, −1, +1” stored in the offset information storage register 105. The offset adjustment value corresponding to the digital value stored in b0 and b1 is output as the selected offset adjustment value.

  The reference voltage generation unit 103b corrects the offset based on the selected offset adjustment value, and among the plurality of voltages, the voltage with respect to the digital value stored in the storage areas b0 to b9 for 1 to 9 bits of the successive approximation register 102 Are output to the comparator 101 as the second to tenth reference voltages Vref, respectively.

  When digital values are stored in all the 10-bit storage areas b0 to b9 of the successive approximation register 102, the digital values are A / D conversion results for the analog input voltage V1.

  FIG. 3 shows the conversion characteristics of a conventional A / D converter.

  In the conventional A / D converter, as the conversion characteristic, in order to correct the error of the A / D conversion result with respect to the analog input voltage V1, the region of the conversion error according to the range of the analog input voltage V1 by the above-described configuration. The D / A converter 103 is controlled in units of 1 LSB (Least Significant Bit).

  In the conventional A / D converter, due to this conversion characteristic, the offset adjustment value of the area defined by the digital values stored in the 1st and 2nd bit storage areas b0 and b1 is sent to the D / A converter 103, and the reference The accuracy is improved by adjusting the voltage Vref.

JP 2008-103813 A

  However, the conventional A / D converter can only perform correction in units of 1LSB due to the above-described configuration and conversion characteristics.

  In the conventional A / D converter, the conversion error region is divided according to the range of the analog input voltage V1 and the error of the A / D conversion result is corrected. Therefore, the DNL is corrected at the boundary of the correction region. (Differential-Non Linearity; differential nonlinearity) deteriorates.

  Thus, the conventional A / D converter does not realize highly accurate A / D conversion.

  In the following, means for solving the problems will be described using the reference numerals used in the embodiments for carrying out the invention in parentheses. This symbol is added to clarify the correspondence between the description of the claims and the description of the mode for carrying out the invention, and the technical scope of the invention described in the claims. Must not be used to interpret

  The A / D converter of the present invention includes a conversion result register (1), a D / A converter (2), an input voltage output circuit (3; C30, SW31, SW32, SW33), and a correction data storage memory (45 ), A correction value selection circuit (44), a voltage generation unit (41), a common voltage output circuit (42; 43, C40, SW41), a comparator (5), and an output control unit (6). is doing. In the conversion result register (1), as an initial value, a first intermediate voltage (AVref / 2) which is an intermediate voltage between the first and second power supplies (AVref-GND) supplied to the D / A converter (2) is stored. ) Is stored. The D / A converter (2) converts the digital value stored in the conversion result register (1) into a voltage and outputs it as an output voltage (Vdj). The input voltage output circuit (3; C30, SW31, SW32, SW33) is a second intermediate voltage (AVdd / AV) that is an intermediate voltage between the third and second power supplies (AVdd-GND) supplied to the comparator (5). A voltage (AVdd / 2−Va + Vdj) obtained by subtracting the analog input voltage (Va) from 2) and adding the output voltage (Vdj) is output as the input voltage (Vin). In the correction data storage memory (45), the digital set value ("0000 to 1111") representing the set voltage and the D / A converter (2) convert the set digital value ("0000 to 1111") into the set voltage. A plurality of correction values (“10, 11, 01,..., 11, 10”) representing the correction voltage (AVdd / 2 + Vhj) including an error in time are stored in advance. The correction value selection circuit (44) stores the correction value ("10, 11, 01, ..., 11, 10") stored in the correction data storage memory (45) into the conversion result register (1). A correction value corresponding to the stored digital value is output as a selected correction value. The voltage generator (41) generates a plurality of voltages by a resistance element connected in series between the first and second power supplies (AVref-GND). The common voltage output circuit (42; 43, C40, SW41) selects a correction voltage (Vc = AVref / 2 + Vhj) represented by a selection correction value from among a plurality of voltages, and sets it as a common voltage (Vcom = AVdd / 2 + Vhj). Output. The comparator (5) compares the input voltage (Vin) and the common voltage (Vcom) and outputs the comparison result. The output control unit (6) executes processing for storing the next digital value in the conversion result register (1) based on the comparison result of the comparator (5), and performs the above processing n times (n is an integer of 1 or more). As a result of the execution, the digital value stored in the conversion result register (1) is output as an A (analog) / D (digital) conversion result for the analog input voltage (Va).

  According to the A / D converter of the present invention, the comparison result of the comparator (5) is converted into the output voltage (Vdj) by the D / A converter (2) and fed back to the input side of the comparator (5). A binary search is performed on the analog input voltage (Va) from the first intermediate voltage (AVref / 2) which is an intermediate voltage between the first and second power supplies (AVref-GND) supplied to the D / A converter (2). Do. At this time, high accuracy A / D conversion is realized by changing the common voltage (Vcom) supplied to the common side of the comparator (5) in consideration of the error of the D / A converter (2). Can do.

FIG. 1 shows a configuration of a technique described in Japanese Patent Application Laid-Open No. 2008-103813 as a conventional A / D converter. FIG. 2 shows the contents stored in the offset information storage ROM 107 of FIG. FIG. 3 shows the conversion characteristics of a conventional A / D converter. FIG. 4 shows a configuration of the A / D converter according to the embodiment of the present invention. FIG. 5 shows the contents stored in the correction data storage RAM 45 of FIG. FIG. 6 shows an operation principle of the A / D converter according to the embodiment of the present invention. FIG. 7 is a diagram for explaining the operation in the user mode as the operation of the A / D converter according to the embodiment of the present invention.

  Hereinafter, an A / D converter according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 4 shows a configuration of the A / D converter according to the embodiment of the present invention.

  The A / D converter according to the embodiment of the present invention includes a conversion result register 1, a D / A converter 2, an input voltage output circuit 3, a common voltage control circuit 4, a comparator 5, and an output control unit 6. It has.

  The conversion result register 1 has a storage area of n bits (n is an integer of 1 or more). For example, when n is 4, the storage area is represented by b3 to b0. In the conversion result register 1, a binary digital value representing the first intermediate voltage AVref / 2, which is an intermediate voltage between the first power supply (power supply voltage AVref) and the second power supply (ground voltage GND), is used as an initial value. Stores the value. In this case, 1 is stored in the conversion result register 1 as a digital value representing the first intermediate voltage AVref / 2 in the storage area b3 of the first bit, and 0 is stored in the other storage areas b2 to b0. (See j = 1 in FIG. 6).

  The D / A converter 2 converts the digital value stored in the n-bit storage areas b3 to b0 of the conversion result register 1 into a set voltage in a range from “0 to AVref”, and outputs the jth output voltage Vdj. (J is an integer satisfying 1 ≦ j ≦ n).

  The input voltage output circuit 3 receives an analog input voltage Va and generates an analog signal from the second intermediate voltage AVdd / 2, which is an intermediate voltage between the third power supply (power supply voltage AVdd) and the second power supply (ground voltage GND). A voltage AVdd / 2−Va + Vdj obtained by subtracting the input voltage Va and adding the jth output voltage Vdj is output to the comparator 5 as the jth input voltage Vin.

  The input voltage output circuit 3 includes a sampling capacitor C30 and switches SW31, SW32, SW33. Here, the sampling capacitor C30 and the switches SW31, SW32, and SW33 will be described when the operation is described.

  The common voltage control circuit 4 includes a voltage generator 41, a common voltage output circuit 42, a correction value selection circuit 44, and a correction data storage RAM (Random Access Memory) 45.

  The voltage generation unit 41 generates (generates) a plurality of voltages by a resistance element connected in series between the first power supply (power supply voltage AVref) and the second power supply (ground voltage GND).

  The common voltage output circuit 42 includes a correction voltage selection unit 43, a sampling capacitor C40, and a switch SW41. Here, the sampling capacitor C40 and the switch SW41 will be described when the operation is described.

In the correction data storage RAM 45, set digital values and correction values are stored in advance for 2 ⁿ codes. Here, the set digital value for 2 ⁿ codes represents a set voltage and is a binary digital value for n bits. For example, when n is 4, as shown in FIG. 5, the set digital value for 2 ⁿ codes is represented by “0000 to 1111”. In this case, the set voltages represented by the set digital values “0000 to 1111” for 2 ⁿ codes are represented by “0 to AVref”, respectively. The correction value for 2 ⁿ codes represents the correction voltage Vc. For example, as shown in FIG. 5, ^second correction value of ⁿ code amount is, ^{2 n} code amount set digital value to the "0000 to 1111", respectively "10,11,01, ..., 11, 10" Is represented by The correction voltage Vc represented by the correction values “10, 11, 01,..., 11, 10” for 2 ⁿ codes is represented by AVref / 2 + Vhj. The correction voltage includes an error when the D / A converter 2 converts the set digital value “0000 to 1111” into the set voltage “0 to AVref”.

The correction value selection circuit 44 is a storage area for n bits of the conversion result register 1 among the correction values “10, 11, 01,..., 11, 10” for 2 ⁿ codes stored in the correction data storage RAM 45. A correction value corresponding to the digital value stored in b3 to b0 is output as a selection correction value.

The correction voltage selection unit 43 of the common voltage output circuit 42 includes a switch group corresponding to correction values for 2 ⁿ codes, and selects a correction voltage Vc = AVref / 2 + Vhj represented by the selection correction value from a plurality of voltages. . At this time, the common voltage output circuit 42 outputs the correction voltage Vc = AVref / 2 + Vhj to the comparator 5 as the jth common voltage Vcom = AVdd / 2 + Vhj.

  The comparator 5 compares the jth input voltage Vin with the jth common voltage Vcom, and outputs the comparison result to the output control unit 6 as the jth comparison result.

  The output control unit 6 executes processing for storing the next digital value in the conversion result register 1 based on the comparison result of the comparator 5. The process is shown below.

  When the j-th input voltage Vin is larger than the j-th common voltage Vcom, the output control unit 6 converts the j-th input voltage Vin as a binary digital value representing a voltage lower than the j-th common voltage Vcom. 0 is stored in the j-th storage area of the result register 1 (see FIG. 6). At this time, if j is not n, the output control unit 6 stores 1 in the storage area of the (j + 1) -th bit of the conversion result register 1 (see FIG. 6).

  As a j-th comparison result, when the j-th input voltage Vin is equal to or lower than the j-th common voltage Vcom, the output control unit 6 outputs a binary digital value representing a voltage higher than the j-th common voltage Vcom. 1 is stored in the j-th storage area of the conversion result register 1 (see FIG. 6). At this time, if j is not n, the output control unit 6 stores 1 in the storage area of the (j + 1) -th bit of the conversion result register 1 (see FIG. 6).

  The output control unit 6 outputs the digital value stored in the n-bit storage areas b3 to b0 of the conversion result register 1 as the analog input voltage Va when the result of executing the above process n times, that is, j is n. Is output as an A (analog) / D (digital) conversion result (see FIG. 6).

  As described above, according to the A / D converter according to the embodiment of the present invention, as a first effect, the comparison result of the comparator 5 is converted into the output voltage Vdj by the D / A converter 2 and By performing feedback, the analog input voltage Va is subjected to a binary search from the first intermediate voltage AVref / 2 that is an intermediate voltage between the first and second power supplies (AVref-GND) supplied to the D / A converter 2. . At this time, highly accurate A / D conversion can be realized by changing the common voltage Vcom supplied to the common side of the comparator 5 in consideration of the error of the D / A converter 2.

In the present invention, as described above, the set digital values “0000 to 1111” and correction values “10, 11, 01,..., 11, 10” for 2 ⁿ codes stored in the correction data storage RAM 45 are stored. A mode in which the A / D converter is used to operate is referred to as a “user mode”.

The error of the D / A converter 2 may be different for each semiconductor integrated circuit to be mounted. For this reason, in the user mode, it is preferable to use a correction value according to a semiconductor integrated circuit to be mounted instead of a fixed correction value. That is, for each semiconductor integrated circuit to be mounted, the correction voltage represented by the correction value “10, 11, 01,..., 11, 10” is measured in advance, and the set digital value “0000 to 1111” and the correction value “10, 11” are measured. , 01,..., 11, 10 ″ are preferably stored in the correction data storage RAM 45 in advance in a mode for storing 2 ⁿ codes. In the present invention, this mode is referred to as a “test mode”.

  The test mode is executed before the user mode is executed.

In the test mode, the conversion result register 1 stores the target setting digital value among the setting digital values “0000 to 1111” for 2 ⁿ codes. For example, it is assumed that the target setting digital value is “0100”.

  Next, a high-precision analog input voltage Va is input to the analog voltage corresponding to the target setting digital value “0100” using a high-precision LSI tester or the like. At this time, the D / A converter 2 converts the target setting digital value “0100” stored in the conversion result register 1 into a voltage and outputs it as an output voltage Vdj.

  The input voltage output circuit 3 receives the analog input voltage Va and receives the analog input voltage from the second intermediate voltage AVdd / 2 that is an intermediate voltage between the third and second power sources (AVdd-GND) supplied to the comparator 5. The voltage AVdd / 2−Va + Vdj obtained by subtracting Va and adding the output voltage Vdj is output to the comparator 5 as the input voltage Vin.

  The comparator 5 compares the input voltage Vin and the common voltage Vcom, and outputs the comparison result.

The correction voltage selection unit 43 of the common voltage output circuit 42 is provided with the target correction value among the correction values “10, 11, 01,..., 11, 10” for 2 ⁿ codes. For example, it is assumed that the target correction value is “11”. The correction voltage selection unit 43 selects the correction voltage Vc = AVref / 2 + Vhj represented by the target correction value “11” from the plurality of voltages. At this time, the common voltage output circuit 42 outputs the correction voltage Vc = AVref / 2 + Vhj to the comparator 5 as the common voltage Vcom = AVdd / 2 + Vhj.

  As a comparison result, when the input voltage Vin and the common voltage Vcom match, the target setting digital value “0100” and the target correction value “11” at that time are associated with each other and stored in the correction data storage RAM 45.

Now, the test mode is executed with the target setting digital value “0100”, but the test mode is executed for the setting digital values “0000 to 1111” for 2 ⁿ codes.

  As described above, according to the A / D converter according to the embodiment of the present invention, the second effect is that the error of the D / A converter 2 may be different for each semiconductor integrated circuit to be mounted. , A correction voltage in consideration of the error of the D / A converter 2 is measured in advance for the set digital value “0000 to 1111” for each semiconductor integrated circuit, and correction values “10, 11, 01,. By storing a plurality of 10 ″ in the correction data storage RAM 45 in advance, in the user mode, it is possible to use a correction value according to the semiconductor integrated circuit to be mounted instead of a fixed correction value. Accurate A / D conversion can be realized.

  In this case, in the A / D converter according to the embodiment of the present invention, in order to realize the second effect, the input voltage Vin and the common voltage Vcom are changed while changing the target correction value, that is, changing the correction voltage. The matching target correction value is preferably stored in the correction data storage RAM 45 in association with the target setting digital value.

  In the present invention, the contents of the correction data storage RAM 45 can be maintained even when the power to the semiconductor integrated circuit is turned off, and the nonvolatile data such as a flash memory can be used as long as it can be rewritten in the test mode. Good.

  Next, the operation of the A / D converter according to the embodiment of the present invention will be described.

  Here, the switch SW32 of the input voltage output circuit 3 is provided between the analog input terminal and the connection node. A switch SW33 of the input voltage output circuit 3 is provided between the D / A converter 2 and the connection node. An analog input voltage Va is supplied to the analog input terminal. A sampling capacitor C30 of the input voltage output circuit 3 is provided between the connection node and the input-side terminal of the comparator 5. A switch SW31 of the input voltage output circuit 3 is provided between the power supply for supplying the second intermediate voltage AVdd / 2 and the input-side terminal of the comparator 5. The switches SW31, SW32, SW33 are turned on according to the control signal.

  A sampling capacitor C 40 of the common voltage output circuit 42 is provided between the correction voltage selection unit 43 of the common voltage output circuit 42 in the common voltage control circuit 4 and the common side terminal of the comparator 5. A switch SW41 of the common voltage output circuit 42 is provided between the power source that supplies the second intermediate voltage AVdd / 2 and the common side terminal of the comparator 5. The switch SW41 is turned on according to the control signal.

  The A / D converter according to the embodiment of the present invention executes the above-described test mode and user mode.

"Test mode"
The test mode is executed for each semiconductor integrated circuit. In the test mode, the processes (a), (b), and (c) are executed in this order.

  Here, as a specific example, the set digital value is 4 bits, the correction value is 2 bits, the set voltage AVref is 3.2 [V], the power supply voltage AVdd is 3.2 [V], the sampling capacitor C30, A case where the capacitance of C40 is C [F], the analog input voltage Va is 0.8 [V], and the target setting digital value Da is “0100” (binary number) will be described.

Further, it is assumed that 1LSB = 3.2V / 2 ⁴ = 0.2V. In this case, the ideal digital value for 0.8V is 4 {0.8V / 0.2V = 4 (binary 0100)}.

  Further, when 4 is applied to the D / A converter 2, the output voltage Vdj of the D / A converter 2 is set to 0.81 V (error voltage Verr = + 0.01 V).

  The correction voltage selection unit 43 in the common voltage control circuit 4 outputs 1.61 V as the correction voltage when the correction value is “11”, and 1 as the correction voltage when the correction value is “10”. .60V is output, 1.59V is output as the correction voltage when the correction value is "01", and 1.58V is output as the correction voltage when the correction value is "00".

Process (a)
Using a high-precision LSI tester or the like, an analog input voltage Va = 0.8 V is supplied to the analog input terminal as a high-precision analog voltage.

  On the input side of the comparator 5, a control signal is supplied to the switches SW31 and SW32. At this time, the switches SW31 and SW32 are turned on according to the control signal, and the analog input voltage Va = 0.8V and the second intermediate voltage AVdd / 2 = 1.6V are supplied to both electrodes of the sampling capacitor C30. The sampling capacitor C30 stores a charge Qi = 0.8C.

  On the other hand, on the common side of the comparator 5, a correction value representing the first intermediate voltage AVref / 2 is given to the correction voltage selection unit 43 as a target correction value, and a control signal is supplied to the switch SW41. At this time, the switch SW41 is turned on according to the control signal, and the first intermediate voltage AVref / 2 represented by the target correction value is output from the correction voltage selection unit 43 as the correction voltage, and the correction voltage is applied to both electrodes of the sampling capacitor C40. The first intermediate voltage AVref / 2 = 1.6V and the second intermediate voltage AVdd / 2 = 1.6V, which are voltages, are supplied, and the charge Qc = 0C is stored in the sampling capacitor C40.

Process (b)
On the input side of the comparator 5, the supply of control signals to the switches SW31 and SW32 is stopped. At this time, the switches SW31 and SW32 are turned off, and the charge Qi = 0.8C of the sampling capacitor C30 is held. The input voltage Vin supplied to the input-side terminal of the comparator 5 becomes the second intermediate voltage AVdd / 2.

  Next, the target setting digital value “0100” is stored in the conversion result register 1 as an ideal digital value representing the analog input voltage Va = 0.8 V, and a control signal is supplied to the switch SW33. At this time, the switch SW33 is turned on in response to the control signal, and the output voltage Vdj is output from the D / A converter 2.

  Since the sampling capacitor C30 holds the charge Qi = 0.8C, the input voltage Vin becomes Vin = 1.61V from 0.8C = (Vin−0.81V) C.

  On the other hand, on the common side of the comparator 5, the supply of the control signal to the switch SW41 is stopped. At this time, the switch SW41 is turned off, and the charge Qc = 0C of the sampling capacitor C40 is held. The common voltage Vcom supplied to the common side terminal of the comparator 5 maintains the state of the second intermediate voltage AVdd / 2 = 1.6V, which is a correction voltage.

Process (c)
Next, in order to make the error voltage Verr 0 while maintaining the input voltage Vin = 1.61V, the correction value, that is, the common voltage Vcom is changed by changing the target correction value to be applied to the correction voltage selection unit 43. Let

  As a comparison result output from the comparator 5, when the input voltage Vin = 1.61V becomes the common voltage Vcom = 1.61V, the target setting digital value “0100” and the target correction value “11” at that time correspond to each other. In addition, it is stored in the correction data storage RAM 45.

Processes (a) to (c) are performed for 2 ⁴ = 16 codes.

User mode
The user mode is executed after the test mode.

  As a specific example, the set digital value is 4 bits, the correction value is 2 bits, the set voltage AVref is 3.2 [V], the power supply voltage AVdd is 3.2 [V], and the sampling capacitors C30 and C40 are static. The case where the capacitance is C [F] and the analog input voltage Va is 0.8 [V] will be described.

Further, it is assumed that 1LSB = 3.2V / 2 ⁴ = 0.2V. In this case, the ideal digital value for 0.8V is 4 {0.8V / 0.2V = 4 (binary 0100)}.

  Further, the output voltage Vdj of the D / A converter 2 when 8 is applied to the D / A converter 2 is set to 1.58 V (error voltage Verr = −0.02 V). The output voltage Vdj of the D / A converter 2 when 4 is applied to the D / A converter 2 is set to 0.81 V (error voltage Verr = + 0.01 V). The output voltage Vdj of the D / A converter 2 when 5 is applied to the D / A converter 2 is set to 1.00 V (error voltage Verr = 0.00 V).

  The correction voltage selection unit 43 in the common voltage control circuit 4 outputs 1.61 V as the correction voltage when the correction value is “11”, and 1 as the correction voltage when the correction value is “10”. .60V is output, 1.59V is output as the correction voltage when the correction value is "01", and 1.58V is output as the correction voltage when the correction value is "00".

  In the user mode, as shown in FIG. 7, the operation is divided into a “sampling period” and a “hold period”.

  In addition, in the sampling period, the conversion result register 1 is set (stored) with an initial digital value “1000”. That is, in the sampling period, the digital value of the conversion result register 1 is reset to “1000”.

"Sampling period"
In the sampling period, the processes (A), (B), and (C) are executed in this order.

Processing (A)
First, a control signal is supplied to the switches SW31 and SW41. At this time, the switches SW31 and SW41 are turned on in response to the control signal, and the second intermediate voltage AVdd / 2 = 1.6V is supplied to the sampling capacitors C30 and C40 and supplied to the input side terminal of the comparator 5. Input voltage Vin and the common voltage Vcom supplied to the common terminal of the comparator 5 are set to the second intermediate voltage AVdd / 2 = 1.6V.

Processing (B)
On the input side of the comparator 5, a control signal is supplied to the switch SW32. At this time, the switch SW32 is turned on according to the control signal, the analog input voltage Va and the second intermediate voltage AVdd / 2 are supplied to one electrode of the sampling capacitor C30, and the charge Qi = (AVdd / 2−Va). ) * C30 = (1.6V−0.8V) * C = 0.8C is stored.

  On the other hand, on the common side of the comparator 5, the correction voltage (first intermediate voltage AVref / 2 = 1) represented by the correction value “00” with respect to the digital value “1000” that is the initial value stored in the conversion result register 1. .6V) is output from the common voltage control circuit 4, the second intermediate voltage AVdd / 2 = 1.6V as the correction voltage is supplied to the other electrode of the sampling capacitor C40, and the charge Qc is supplied to the sampling capacitor C40. = (AVdd / 2−AVref / 2) * C40 = 0 is stored.

Processing (C)
Next, on the input side of the comparator 5, the supply of control signals to the switches SW31 and SW32 is stopped. At this time, the switches SW31 and SW32 are turned off, and the charge Qi = 0.8C of the sampling capacitor C30 is held.

  On the other hand, on the common side of the comparator 5, the supply of the control signal to the switch SW41 is stopped. At this time, the switch SW41 is turned off, and the charge Qc of the sampling capacitor C40 is held.

  This completes the sampling period, and then the hold period.

"Hold period"
In the hold period, processes (D), (E), (F),... Are executed in this order.

(First binary search)
Processing (D)
First, a control signal is supplied to the switch SW33 on the input side of the comparator 5. At this time, the switch SW33 is turned on in response to the control signal, and the first output voltage Vd1 = 1... From the D / A converter 2 with respect to the digital value “1000” which is the initial value stored in the conversion result register 1. 58V (error voltage Verr = −0.02V) is output. The first output voltage Vd1 = 1.58V is supplied to the other electrode of the sampling capacitor C30. Thereby, the input voltage Vin supplied to the input side terminal of the comparator 5 is expressed by Vin = AVdd / 2−Va + Vd1 = 1.6V−0.8V + 1.58V = 2.38V.

  On the other hand, the common voltage Vcom supplied to the common terminal of the comparator 5 is Vcom = Vc = AVdd / 2 + Vh1 with respect to the set digital value “1000” and the correction value “00” stored in the correction data storage RAM 45. = 1.58V.

  Therefore, the comparator 5 compares the first input voltage Vin = 2.38V with the first common voltage Vcom = 1.58V, and outputs the comparison result to the output control unit 6 as the first comparison result.

  As a first comparison result, the output control unit 6 has a first input voltage Vin = 2.38V that is higher than the first common voltage Vcom = 1.58V, so that the first common voltage Vcom = 1.58V. As a digital value representing a low voltage, 0 is stored in the first bit storage area of the conversion result register 1, and 1 is stored in the second bit storage area of the conversion result register 1 (see FIG. 6).

(Second binary search)
Processing (E)
First, a control signal is supplied to the switch SW33 on the input side of the comparator 5. At this time, the switch SW33 is turned on in response to the control signal, and the second output voltage Vd2 = 0.81V (error voltage) from the D / A converter 2 with respect to the digital value “0100” stored in the conversion result register 1. Verr = + 0.01V) is output. The second output voltage Vd2 = 0.81V is supplied to the other electrode of the sampling capacitor C30. Thus, the input voltage Vin supplied to the input side terminal of the comparator 5 is expressed by Vin = AVdd / 2−Va + Vd2 = 1.6V−0.8V + 0.81V = 1.61V.

  On the other hand, the common voltage Vcom supplied to the common terminal of the comparator 5 is Vcom = Vc = AVdd / 2 + Vh2 with respect to the set digital value “0100” and the correction value “11” stored in the correction data storage RAM 45. = 1.61V.

  Therefore, the comparator 5 compares the second input voltage Vin = 1.61 V with the second common voltage Vcom = 1.61 V, and outputs the comparison result to the output control unit 6 as the second comparison result.

  As the second comparison result, the output control unit 6 represents a voltage higher than the second common voltage Vcom because the second input voltage Vin = 1.61V is the same as the second common voltage Vcom = 1.61V. As a digital value, 1 is stored in the second bit storage area of the conversion result register 1, and 1 is stored in the third bit storage area of the conversion result register 1 (see FIG. 6). When Vin = Vcom, 0 may be stored in the storage area.

  Similarly, in the process (F), the third binary search is performed, and in the process (G), the fourth binary search is performed. As a result, the output control unit 6 outputs the digital value stored in the 4-bit storage areas b3 to b0 of the conversion result register 1 as an A / D conversion result for the analog input voltage Va.

  As described above, the A / D converter according to the embodiment of the present invention achieves the following effects.

  According to the A / D converter according to the embodiment of the present invention, the comparison result of the comparator 5 is converted into the output voltage Vdj by the D / A converter 2 and fed back to the input side of the comparator 5, whereby the analog input voltage Va is changed. The binary search is performed from the first intermediate voltage AVref / 2 which is an intermediate voltage between the first and second power supplies (AVref−GND) supplied to the D / A converter 2. At this time, highly accurate A / D conversion can be realized by changing the common voltage Vcom supplied to the common side of the comparator 5 in consideration of the error of the D / A converter 2.

  According to the A / D converter according to the embodiment of the present invention, the error of the D / A converter 2 may be different for each semiconductor integrated circuit to be mounted. Therefore, in the test mode, the set digital value “ A correction voltage in consideration of the error of the D / A converter 2 is measured in advance for 0000 to 1111 ”, and correction values“ 10, 11, 01,..., 11, 10 ”representing the correction voltage are stored in the correction data storage RAM 45 in advance. In the user mode, a correction value corresponding to the mounted semiconductor integrated circuit can be used in the user mode, and high-precision A / D conversion can be realized. Can do.

  According to the A / D converter according to the embodiment of the present invention, in the test mode, the target correction value in which the input voltage Vin and the common voltage Vcom coincide with each other while changing the target correction value, that is, while changing the correction voltage. By storing the correction data in the correction data storage RAM 45 in association with the set digital value, highly accurate A / D conversion can be realized in the user mode.

1 Conversion result register,
2 D / A converter,
3 Input voltage output circuit,
4 Common voltage control circuit,
5 Comparator,
6 Output controller,
41 Voltage generator,
42 Common voltage output circuit,
43 correction voltage selector,
44 correction value selection circuit,
45 correction data storage RAM,
C30, C40 sampling capacitors,
SW31 to SW33, SW41 switch,
AVref power supply voltage,
AVref set voltage,
AVref / 2 first intermediate voltage,
AVdd power supply voltage,
AVdd / 2 second intermediate voltage,
Va analog input voltage,
Vc correction voltage,
Vcom common voltage,
Vdj output voltage,
Vin input voltage,
101 comparator,
102 successive approximation register,
103 D / A converter,
103a voltage generator,
103b reference voltage generator,
104 Offset value generation unit,
105 Offset information storage register,
107 Offset information storage ROM,
V1 Analog input voltage

Claims (7)

A conversion result register in which a digital value representing the first intermediate voltage is stored as an initial value;
A D / A converter that converts a digital value stored in the conversion result register into a voltage and outputs the voltage as an output voltage, wherein the first intermediate voltage is supplied to the D / A converter; An intermediate voltage between the two power supplies,
A comparator that compares the input voltage with the common voltage and outputs the comparison result;
An input voltage output circuit for subtracting an analog input voltage from a second intermediate voltage and adding the output voltage to output to the comparator as the input voltage; and wherein the second intermediate voltage is applied to the comparator An intermediate voltage between the supplied third power source and the second power source;
A correction data storage memory in which a plurality of digital set values representing set voltages and correction values representing correction voltages including errors when the D / A converter converts the set digital values into the set voltages are stored in advance. When,
Among the plurality of correction values stored in the correction data storage memory, a correction value selection circuit that outputs a correction value corresponding to a digital value stored in the conversion result register as a selection correction value;
A voltage generating section for generating a plurality of voltages by a resistance element connected in series between the first and second power supplies;
A common voltage output circuit that selects the correction voltage represented by the selection correction value from the plurality of voltages and outputs the correction voltage to the comparator as the common voltage;
Based on the comparison result of the comparator, a process of storing the next digital value in the conversion result register is executed, and as a result of executing the process n times (n is an integer of 1 or more), the result is stored in the conversion result register. An A / D converter comprising: an output control unit that outputs a digital value as an A (analog) / D (digital) conversion result with respect to the analog input voltage. The output control unit, as the processing,
When the input voltage is larger than the common voltage as a comparison result of the comparator, a digital value representing a voltage lower than the common voltage is stored in the conversion result register,
The A / D converter according to claim 1, wherein when the input voltage is equal to or lower than the common voltage as a comparison result of the comparator, a digital value representing a voltage higher than the common voltage is stored in the conversion result register. The conversion result register has a storage area for n bits, 1 is stored in the storage area of the first bit as a binary digital value representing the first intermediate voltage, and 0 is stored in the other storage areas. Is stored,
The D / A converter converts a digital value stored in the n-bit storage area of the conversion result register into a voltage, and sets the jth output voltage (j is an integer satisfying 1 ≦ j ≦ n). Output,
The input voltage output unit outputs the voltage obtained by subtracting the analog input voltage from the second intermediate voltage and adding the jth output voltage to the comparator as the jth input voltage,
In the correction data storage memory, the digital setting value that represents a setting voltage and is a binary digital value for n bits, and the D / A converter sets the setting digital value for the n bits as the setting voltage. And the correction value representing the correction voltage including an error when converted into 2 ⁿ codes are stored,
The correction value selection circuit selects a correction corresponding to a digital value stored in the storage area for n bits of the conversion result register from among the correction values for 2 ⁿ codes stored in the correction data storage memory. Output the value as the selection correction value,
The common voltage output circuit selects the correction voltage represented by the selection correction value from the plurality of voltages, and outputs the correction voltage as the j-th common voltage to the comparator.
The comparator compares the j-th input voltage with the j-th common voltage, and outputs the comparison result as a j-th comparison result;
The output control unit
As the j-th comparison result, when the j-th input voltage is larger than the j-th common voltage, the conversion result register j is represented as a binary digital value representing a voltage lower than the j-th common voltage. When 0 is stored in the storage area of the bit and j is not n, 1 is stored in the storage area of the (j + 1) -th bit of the conversion result register,
As the j-th comparison result, when the j-th input voltage is less than or equal to the common voltage, the j-bit of the conversion result register is represented as a binary digital value representing a voltage higher than the j-th common voltage. If 1 is stored in the second storage area and j is not n, 1 is stored in the storage area of the (j + 1) -th bit of the conversion result register,
3. The A / D converter according to claim 2, wherein when j is n, a digital value stored in the n-bit storage area of the conversion result register is output as an A / D conversion result for the analog input voltage. . Before a user mode, which is a mode for operating the A / D converter using the digital set value and the correction value stored in the correction data storage memory, is executed.
A test mode is a mode in which the correction voltage represented by the correction value is measured in advance for each mounted semiconductor integrated circuit, and the digital setting value and the correction value are stored in advance in the correction data storage memory in a plurality of amounts. The A / D converter in any one of Claims 1-3 performed. In the test mode,
The conversion result register stores a target digital setting value among the plurality of digital setting values,
The D / A converter converts the target digital setting value stored in the conversion result register into a voltage and outputs the voltage as the output voltage,
The input voltage output circuit receives the analog input voltage, subtracts the analog input voltage from the second intermediate voltage, and outputs the input voltage to the comparator as the input voltage,
The comparator compares the input voltage and the common voltage, and outputs the comparison result,
The common voltage output circuit is provided with a target correction value among the plurality of correction values,
The common voltage output circuit outputs the correction voltage represented by the target correction value to the comparator as the common voltage,
5. When the input voltage and the common voltage match as a comparison result of the comparator, the target digital setting value and the target correction value at that time are associated with each other and stored in the correction data storage memory. A / D converter as described in 2. The test mode is a mode in which the digital set value and the correction value are stored in advance in the correction data storage memory for 2 ⁿ codes for each semiconductor integrated circuit,
In the test mode,
The conversion result register stores the target digital setting value among the digital setting values for the ²ⁿ codes,
The A / D converter according to claim 5, wherein the target correction value among the correction values for the 2 ⁿ codes is given to the common voltage output circuit. Storing, as an initial value, a digital value representing a first intermediate voltage, which is an intermediate voltage between the first and second power supplies supplied to the D / A converter, in a conversion result register;
The D / A converter converts the digital value stored in the conversion result register into a voltage and outputs it as an output voltage; and
A voltage obtained by subtracting the analog input voltage from the second intermediate voltage, which is an intermediate voltage between the third power source supplied to the comparator and the second power source, and adding the output voltage is output to the comparator as an input voltage. Process,
A correction data storage memory in which a plurality of digital set values representing set voltages and correction values representing correction voltages including errors when the D / A converter converts the set digital values into the set voltages are stored in advance. A step of outputting a correction value corresponding to a digital value stored in the conversion result register as a selected correction value from the plurality of correction values;
Selecting the correction voltage represented by the selection correction value from a plurality of voltages generated between the first and second power supplies, and outputting the correction voltage to the comparator as a common voltage;
The comparator compares the input voltage with the common voltage and outputs a comparison result;
Executing a process of storing the next digital value in the conversion result register based on the comparison result of the comparator;
A step of outputting the digital value stored in the conversion result register as an A (analog) / D (digital) conversion result for the analog input voltage as a result of executing the process n times (n is an integer of 1 or more). A / D conversion method provided.

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