JP2005303185A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct a plastic molding of a plastic molding semiconductor device without any problem by mounting a semiconductor chip with a pad provided at one side on a lead frame to bond an inner lead and the pad at a side facing to the side with the pad arranged. <P>SOLUTION: The semiconductor device molded by the resin 15 has a semiconductor chip 10 with bonding pads 13 arranged in clusters along one side of the chip mounted on the die pads 11a of a lead frame. A wiring board 20 smaller than the chip is mounted and fixed on the chip, and bonding wires 141 directly connect the internal lead closer to the pad and the chip. Bonding wires 142, 143 connect the internal lead far from the pad and the chip through the wiring board between them. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a package structure in which a semiconductor chip is mounted on a lead frame and sealed with a resin, and a manufacturing method thereof.

  In recent years, a semiconductor device (package) having a ball grid array (BGA) structure using a semiconductor chip in which all pads are provided along a predetermined side of the semiconductor chip has been considered. In this package, a chip with pads provided on one side is stacked on the side edge of the lower layer chip, thereby facilitating wire bonding while reducing the chip size (see, for example, Patent Document 1).

  However, if a chip provided with this pad on one side is used in a semiconductor device (package) having a TSOP (thin small outline package) structure, there are problems as described below.

  5A and 5B are partial cross-sectional side views schematically showing a conventional example of a semiconductor device having a TSOP structure in which a semiconductor chip having a pad provided only on one side is mounted on a lead frame and resin-sealed. It is a partially transparent top view.

  In the semiconductor device shown in FIGS. 5A and 5B, a chip 50 is mounted on a die pad portion 51a of a lead frame, and the chip is fixed to the die pad portion with an adhesive material 52, and a pair of internal leads 51b, The 51c group and the pad 53 group on one side of the chip are connected by the bonding wire 54 group, respectively, and the die pad portion 51a of the lead frame, the internal leads 51b and 51c group, the adhesive 52, the chip 50, and the bonding wire 54 group are resin 55. The lead frame extension 51d projecting on both sides of the resin is formed as a desired external terminal.

However, when assembling this semiconductor device, the pad 53 group and the internal lead 51b group on the near side can be connected as usual with the bonding wire 54 group, but the pad 53 group and the internal lead 51c group on the far side are bonded together. When trying to connect with the wire 54 group, the bonding wire 54 group must be made very long, and the bonding wire 54 group is easily washed away by the resin in the subsequent resin sealing step, so that the adjacent bonding wires 54 are connected to each other. It becomes easy to short-circuit electrically.
JP 2001-102515 A (page 4-5, FIG. 1)

  The present invention has been made to solve the above-described problems. A semiconductor chip having a pad on one side is mounted on a lead frame, and the internal lead and the pad opposite to the pad are obstructed by a bonding wire. It is an object of the present invention to provide a semiconductor device that can be connected without any problem and that can perform resin sealing without hindrance.

  According to a first aspect of the semiconductor device of the present invention, a lead frame having at least a pair of internal lead groups each having a die pad portion and a plurality of internal leads arranged, and concentrated along one side of the chip on the element forming surface side A semiconductor chip mounted on the die pad portion of the lead frame via an adhesive, and mounted on the semiconductor chip via an adhesive, and a wiring group is formed on the upper surface. A wiring board, a first bonding wire group connecting a part of the bonding pad group and an internal lead group near the bonding pad group of the semiconductor chip, a part of the bonding pad group, and the wiring board A second bonding wire group connected to one end of the wiring group, a bonding pad group of the semiconductor chip, and the other end of the wiring A third bonding wire group connecting the internal lead group on the far side, and a resin package in which the die pad portion of the lead frame, the internal lead group, the adhesive, the semiconductor chip, the wiring board, and the bonding wire group are sealed with resin It is characterized by comprising.

  According to a second aspect of the semiconductor device of the present invention, a lead frame having at least a pair of internal lead groups each having a die pad portion and a plurality of internal leads arranged therein and a concentrated arrangement along one side of the chip on the element forming surface side A first semiconductor chip having a first bonding pad group and mounted on the die pad portion of the lead frame via an adhesive, and a second bonding with the same configuration as the first semiconductor chip A first insulating property is provided on the first semiconductor chip in a state in which the bonding pad groups are adjacent to the first semiconductor chip and the arrangement of the bonding pad groups is shifted. A second semiconductor chip stacked via an adhesive, and a wiring that is mounted on the second semiconductor chip via a second insulating adhesive and has a wiring group formed on the upper surface. A first bonding wire group connecting a plate, a part of the internal lead group near the bonding pad group of the first semiconductor chip and a part of the bonding pad of the bonding pad group; A second bonding wire group connecting a part of the internal leads of the second semiconductor chip close to the bonding pad group and a part of the bonding pads of the bonding pad group; and the first semiconductor A third bonding wire group connecting a part of the bonding pads of the chip and one end of a part of the wirings on the wiring board; and a bonding pad group of the second semiconductor chip. A fourth bonding wire connecting a part of the bonding pads and one end of a part of the wirings on the wiring board A fifth bonding wire group connecting the other end portion of the wiring and the internal lead group far from the bonding pad group, a die pad portion of the lead frame, each internal lead group, and each insulating adhesive Each semiconductor chip, a wiring board, and each bonding wire group are provided with a resin package sealed with resin.

  According to the semiconductor device of the present invention, a semiconductor chip having a pad provided on one side is mounted on a lead frame, and an internal lead on the opposite side of the pad can be connected to the pad with a bonding wire without any trouble, and resin sealing Can be performed without hindrance.

<First Embodiment>
1A and 1B are a partial cross-sectional side view and a partially transparent top view schematically showing a semiconductor device having a TSOP structure according to the first embodiment of the present invention. FIG. 2 is a plan view showing an example of a pad layout in a semiconductor chip in which the pads in FIG. 1 are provided on one side.

  1A, 1B, and 2, the semiconductor device 1 includes a semiconductor chip 10, a lead frame 11 having a die pad portion 11a and internal leads 11b and 11c, a resin 15, and a wiring board 20.

  The internal leads 11b and 11c groups of the lead frame 11 are provided at positions facing each other across the die pad portion 11a, and a plurality of internal leads are arranged in each group. The semiconductor chip 10 is arranged with a group of bonding pads 13 concentrated along one side of the chip on the element forming surface side, and is mounted on the die pad portion 11a of the lead frame via the adhesive material 12.

  The wiring board 20 has an outer shape smaller than that of the chip 10, and is mounted on the almost central portion of the chip 10 via an insulating adhesive 21. On the upper surface of the wiring board 20, a group of wirings 22 having one end portion facing the bonding pad 13 group of the chip 10 and the other end portion facing the internal lead 11c group are formed.

  The bonding wire group is divided into three groups. The first bonding wire 141 group connects the internal lead 11b group near the bonding pad 13 group of the chip 10 and a part of the bonding pad 13 group. The second bonding wire 142 group connects a part of the bonding pad 13 group and one end of the wiring 22 group on the wiring board 20. The third bonding wire 143 group connects the other end of the wiring 22 and the internal lead 11c group on the side far from the bonding pad group 13 of the chip (the side opposite to the side where the bonding pad group 13 is disposed). doing.

  The resin 15 seals the die pad portion 11a of the lead frame, the internal leads 11b and 11c, the adhesives 12 and 21, the chip 10, the wiring board 20, and the bonding wires 141 to 143 to form a package.

  A lead portion (a part of the lead frame) 11d group connected to the pair of internal lead groups 11b and 11c protrudes from at least a pair of opposing sides of the resin package to serve as external terminals.

  1A and 1B, when the semiconductor device is manufactured, the wiring board 20 is mounted and fixed to the center of the chip 10 which is fixed to the die pad portion 11a of the lead frame 11. Then, a wire bonding connection is made to a part of the bonding pads of the bonding pad group 13 with respect to the internal lead 11b group on the side close to the bonding pad group. A wire bonding connection is made between a part of the bonding pads 13 and one end of the wiring 22 on the wiring board 20, and the other end of the wiring 22 and the side far from the bonding pad group (bonding) Wire bonding connection is performed between the group of internal leads 11c on the side opposite to the side where the pad group 13 is disposed.

  According to the semiconductor device having the configuration shown in FIGS. 1A and 1B, the wiring board 20 includes a group of bonding pads 13 of the chip 10 having pads provided on one side, and a group of internal leads 11c far from the bonding pad group. It has a wiring relay function for connecting to. In this way, the electrical connection to the internal lead 11c group on the side far from the bonding pad 13 group on the chip is made by relaying the wiring board 20, and the wire bonding connection is made directly without relaying the wiring board. Compared to the case, the bonding wires 142 and 143 can be short. As a result, when resin sealing is performed after the wire bonding step, there is no possibility that the bonding wires 142 and 143 group flow or the adjacent bonding wires 142 or the bonding wires 143 are electrically short-circuited, thereby improving the reliability.

  As the wiring board 20, for example, a substrate in which a Cu wiring pattern is formed on a thin insulating substrate having a thickness of 60 μm can be used. As the insulating base material, a flexible film or the like may be used. However, if a rigid type material such as a glass epoxy resin is used, wire bonding can be easily performed. Further, when a wiring board in which an aluminum wiring pattern is formed on a silicon substrate is used, problems such as warping and peeling of the wiring board hardly occur because the thermal expansion coefficient is close to that of the chip.

  Of the bonding pad group 13 on the chip, the input / output pad for signal input / output (I / O) is directly connected to the internal lead 11b on the side close to the bonding pad group 13 by wire bonding. This is preferable because the parasitic capacitance of the input / output system internal wiring is reduced and the proportion of influence of external noise is reduced.

  FIG. 3 shows an example of an array of lead frames and corresponding external terminals when the semiconductor device of FIG. 1 is applied to a memory integrated circuit device (for example, NAND flash memory).

  In FIG. 3, each internal lead 11b connected to an external terminal for input / output (I / O) for 8 bits is located on the side close to the bonding pad 13 group on the chip 10, and the adjacent bonding pad 13 group Wire bonding is directly connected between the two.

<Second Embodiment>
In the semiconductor device according to the second embodiment, an insulating adhesive is used in which two semiconductor chips each having pads of the same type and / or the same size are provided on one side, with their pad arrangement portions being close to each other and shifted. And a package structure in which resin is sealed by stacking (stacking).

  4A and 4B are a partial cross-sectional side view and a partially transparent top view schematically showing a semiconductor device having a TSOP structure according to the second embodiment of the present invention.

  The semiconductor device shown in FIGS. 4A and 4B is different from the semiconductor device of the first embodiment in that it has a chip stacked structure in which two semiconductor chips 101 and 102 are stacked, and the others are the same. Therefore, the same reference numerals as those in FIG.

  4 (a) and 4 (b), the lead frame has a die pad portion 11a and a group of at least a pair of internal leads 11b, 11c facing each other in which a plurality of internal leads are arranged.

  The first chip 101 has a first bonding pad group 131 arranged in a concentrated manner along one side of the chip on the element forming surface side, and a pad mounted on the die pad portion via the adhesive 12 is one side. It is the chip provided in.

  The second chip 102 is a single-sided pad type chip having the same structure as the first chip 101 and having the second bonding pad 132 group, and the bonding pad group is close to the first chip 101. In addition, the bonding pads are laminated on the first chip 101 with an insulating adhesive 122 interposed therebetween in a state where the arrangement of the bonding pad groups is shifted. In this case, the second chip 102 can be used as the insulating adhesive material 122 in which the insulating adhesive material on the film attached to the back surface of the wafer remains in the scribing (dicing) process for separating from the wafer individually. It is.

  The wiring board 20 is mounted on the second chip 102 via an insulating adhesive material 21, and a group of wirings 22 is formed on the upper surface. In this case, the tip of each wiring 22 of the wiring board is formed wide so that wire bonding can be easily performed.

  The bonding wire group is divided into five groups. The first bonding wire 141 group connects some bonding pads of the bonding pad 131 group of the first chip 101 and some internal leads of the internal lead 11b group on the side close thereto. The second bonding wire 142 group connects a part of the bonding pads 131 of the first chip 101 and one end of a part of the wirings 22 on the wiring board 20. The third bonding wire group connects the other end of a part of the wiring 22 group and the internal lead 11c group far from each bonding pad group. The fourth bonding wire group connects a part of the bonding pads 132 of the second chip 102 and a part of the internal leads 11b on the side close thereto. The fifth bonding wire group connects a part of the bonding pads 132 of the second chip 102 and one end of a part of the wirings 22 of the wiring board 20 on the wiring board 20.

  The resin 15 forms a package by sealing the die pad portion 11a of the lead frame, the internal leads 11b and 11c, the insulating adhesives 12, 122 and 21, the chips 101 and 102, the wiring board 20, and the bonding wires 141 to 145. .

  A lead portion (a part of the lead frame) 11d group connected to the pair of internal lead groups 11b and 11c protrudes from at least a pair of opposing sides of the resin package to serve as external terminals.

  In manufacturing the semiconductor device having the above structure, the second chip pad 131 is slightly shifted so that the first chip 101 group is exposed on the first chip 101 bonded and fixed to the die pad 11a portion of the lead frame. The chip 102 is mounted and bonded and fixed. Further, a wiring board 20 smaller than the chip is mounted on the second chip 102 and bonded and fixed. For each of the chips 101 and 102, wire bonding connection is performed between the chip and the internal lead 11b group on one side, between the chip and the wiring board 20, and between the internal lead 11c group on the other side and the wiring board 20, respectively. .

  However, when wire bonding connection is made between the first chip 101 and the second chip 102 to the substrate wiring of the same potential as shown by the circles in FIGS. 4A and 4B, first, A bump is formed on the pad 132 of the second chip 102 by wire bonding, and wire bonding is performed from the pad 131 of the first chip 101 to the bump 132 on the pad 132 of the second chip 102, and bonding has already been performed. It is possible to perform wire bonding from above the bump on the pad 132 of the second chip 102 to the substrate wiring 22.

  4 (a) and 4 (b), the wiring board 20 has a wiring relay function for the chips 101 and 102, and is less than about half of the bonding pads 131 and 132 of the chip. Performs wiring relay function. In this case, the wiring board 20 is smaller in size than the respective chips 101 and 102 on the lower layer side, requires less member cost, has a low possibility of peeling from the chip after packaging, and has high reliability.

  The present invention is not limited to the TSOP structure described above, and can be applied to, for example, a semiconductor device having a package structure having external terminals on four sides.

1 is a partially sectional side view and a partially transparent top view schematically showing a semiconductor device having a TSOP structure according to a first embodiment of the present invention; The top view which shows an example of the pad layout on the semiconductor chip of the single-sided pad system in FIG. FIG. 2 is a plan view showing an example of an arrangement of lead frames and corresponding external terminals when the semiconductor device of FIG. 1 is applied to a memory integrated circuit device. FIG. 4 is a partial cross-sectional side view and a partially transparent top view schematically showing a semiconductor device having a TSOP structure according to a second embodiment of the present invention. The partial cross section side view and partial perspective top view which show schematically the prior art example of the semiconductor device of the TSOP structure which mounted the semiconductor chip of the one side pad system on the lead frame, and was resin-sealed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... One side pad type semiconductor chip, 11a ... Die pad part, 11b, 11c ... Internal lead, 11d ... Lead part, 12, 21 ... Insulating adhesive, 13 ... Bonding pad, 141 ... First bonding wire, 142: second bonding wire, 143: third bonding wire, 15: resin, 20: wiring board, 22: wiring.

Claims (5)

A lead frame having a die pad portion and at least a pair of internal leads each having a plurality of internal leads arranged therein;
A semiconductor chip having a bonding pad group arranged in a concentrated manner along one side of the chip on the element forming surface side, and mounted on the die pad portion of the lead frame via an adhesive;
A wiring board mounted on the semiconductor chip via an adhesive and having a wiring group formed on the upper surface;
A first bonding wire group connecting an internal lead group on the side close to the bonding pad group of the semiconductor chip and a part of the bonding pad group;
A second bonding wire group connecting a part of the bonding pad group and one end of the wiring group on the wiring board;
A third bonding wire group connecting the other end of the wiring and an internal lead group far from the bonding pad group of the semiconductor chip;
And a resin package in which a die pad portion of the lead frame, an internal lead group, an adhesive, a semiconductor chip, a wiring board, and a bonding wire group are sealed with a resin.   2. The bonding pad group of the semiconductor chip, wherein a pad for inputting / outputting a signal is directly wire-bonded to an internal lead on the side close to the bonding pad group. The semiconductor device described. A lead frame having a die pad portion and at least a pair of internal leads each having a plurality of internal leads arranged therein;
A first semiconductor chip having a first bonding pad group concentratedly arranged along one side of the chip on the element forming surface side, and mounted on the die pad portion of the lead frame via an adhesive;
It has the same structure as the first semiconductor chip, has a second bonding pad group, the bonding pad groups are close to the first semiconductor chip, and the arrangement of the bonding pad groups is shifted. A second semiconductor chip laminated on the first semiconductor chip in a state via a first insulating adhesive;
A wiring board mounted on the second semiconductor chip via a second insulating adhesive and having a wiring group formed on the upper surface;
A first bonding wire group connecting a part of the internal leads of the first semiconductor chip close to the bonding pad group and a part of the bonding pads of the bonding pad group;
A second bonding wire group connecting a part of the internal leads of the second semiconductor chip close to the bonding pad group and a part of the bonding pads of the bonding pad group;
A third bonding wire group connecting a part of bonding pads of the bonding pad group of the first semiconductor chip and one end of a part of wiring of the wiring group on the wiring board;
A fourth bonding wire group connecting a part of bonding pads of the bonding pad group of the second semiconductor chip and one end of a part of wiring of the wiring group on the wiring board;
A fifth bonding wire group connecting the other end of the wiring and the internal lead group on the side far from the bonding pad group;
A semiconductor device comprising: a die pad portion of the lead frame; each internal lead group; each insulating adhesive; each semiconductor chip; a wiring board; and a resin package in which each bonding wire group is sealed with resin.   4. The semiconductor device according to claim 3, wherein the wiring board is smaller in size than each of the semiconductor chips.   2. The bonding pad group of each semiconductor chip, wherein a pad for inputting / outputting a signal is directly wire-bonded to an internal lead on the side close to the bonding pad group. 3. The semiconductor device according to 3 or 4.

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