JP3994084B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device mounted by wire bonding.

  2. Description of the Related Art Conventionally, semiconductor devices having package forms such as SOP (Small Outline Package), DIP (Dual Inline Package), PGA (Pin Grid Array), and QFP (Quad Flat Package) in which a semiconductor chip is contained in a package are known. In order to improve the mounting density, various semiconductor devices in the form of a multichip package in which a plurality of semiconductor chips are accommodated in one package have been proposed.

For example, there are the following documents concerning semiconductor devices in the form of a multichip package.
JP 2000-332194 A JP 2001-7277 A

  6A and 6B are schematic configuration diagrams of a conventional SOP type semiconductor device, where FIG. 6A is a plan view and FIG. 6B is a longitudinal sectional view. 7A and 7B are schematic configuration diagrams of a conventional SOP type semiconductor device in which the lead position for external lead is different from that in FIG. 6, and FIG. 7A is a plan view and FIG. FIG. (B) is a longitudinal sectional view.

  In the semiconductor device of FIG. 6, a semiconductor chip 20A is mounted using a lead frame 10A. As shown in FIG. 6A, the lead frame 10A has a die pad 11A for mounting a semiconductor chip having a substantially rectangular plane, and a plurality of lead frames 10A are vertically separated at a predetermined distance from the upper and lower sides of the die pad 11A. A lead 12A is disposed. Each lead 12A is provided with a bonding pad 13A on the inner inner lead portion, and the outer outer lead portion is drawn to the outside.

  On the die pad 11A, a semiconductor chip 20A having a rectangular plane is fixed. On the surface of the semiconductor chip 20A, as shown in FIG. 6A, a plurality of bonding pads 21A are arranged in the vicinity of the upper side and the lower side corresponding to the arrangement positions of the bonding pads 13A on the lead frame side. Yes. The plurality of bonding pads 21A on the semiconductor chip side are connected to the plurality of bonding pads 13A on the lead frame side by a plurality of wires 14A. The semiconductor chip 20A and the plurality of wires 14A are resin-sealed by a resin member 15A.

  In the semiconductor device of FIG. 7, since the lead frame 10B of FIG. 6 is mounted by using a lead frame 10B having a different lead drawing direction, the bonding pad arrangement position with respect to the semiconductor chip 20A of FIG. Different semiconductor chips 20B are used.

  That is, in the lead frame 10B of FIG. 7, as shown in FIG. 7A, a plurality of leads 12B are disposed laterally at a predetermined distance from the left and right sides of the die pad 11B having a rectangular plane. Yes. Each lead 12B is provided with a bonding pad 13B on the inner inner lead portion, and the outer outer lead portion is pulled out in the lateral direction.

  The semiconductor chip 20B having a rectangular plane fixed on the die pad 11B has the same function as that of the semiconductor chip 20A of FIG. 6, but in order to correspond to the arrangement position of the bonding pad 13B on the lead frame side, In addition, it is newly created separately from the semiconductor chip 20A of FIG. 6 so that a plurality of bonding pads 21B are arranged in the vicinity of the right side. The plurality of bonding pads 21B of the semiconductor chip 20B are connected to the plurality of bonding pads 13B on the lead frame side by a plurality of wires 14B, and then the semiconductor chip 20B and the plurality of wires 14B are made of resin. Resin-sealed by the member 15B.

  8A, 8B, and 8C are schematic configuration diagrams showing a conventional semiconductor device in the form of a multichip package. FIG. 8A is a plan view seen from the surface, and FIG. ) Is a bottom view seen from the back side, and FIG. 7C is a longitudinal sectional view. Elements common to those in FIG. 7 are denoted by common reference numerals.

  In this semiconductor device, for example, for the purpose of doubling the memory capacity, semiconductor chips 20B and 20C having the same function are mounted on both the front and back surfaces of the die pad 11B of the lead frame 10B as shown in FIG. .

  As shown in FIG. 8A, the lead frame 10B has a die pad 11B having a rectangular plane, and a plurality of leads 12B are disposed laterally at a predetermined distance from the left and right sides. . The plurality of leads 12B have bonding pads 13B (left bonding pads 13B-11, 13B-12,..., Right bonding pads 13B-21, 13B-22,...) On inner inner lead portions. Provided, and the outer outer lead portion is pulled out in the lateral direction.

  On the surface of the semiconductor chip 20B on the front side of the die pad 11B, a left side and a right side corresponding to the bonding pads 13B-11, 13B-12,..., 13B-21, 13B-22,. A plurality of bonding pads 21B (left bonding pads 21B-11, 21B-12,..., Right bonding pads 21B-21, 21B-22,...) Are disposed in the vicinity. The left bonding pads 21B-11, 21B-12,... Are connected to the left bonding pads 13B-11, 13B-12,. The right bonding pads 21B-21, 21B-22,... Are connected to the right bonding pads 13B-21, 13B-22,.

  When a chip having the same configuration as the front-side semiconductor chip 20B (that is, the same arrangement of bonding pads) is used as the semiconductor chip 20C on the back side of the die pad 11B, the arrangement of bonding pads is left and right as viewed from the front side of the die pad 11B. Or since it is reversed up and down, the some wire 14C cross | intersects and shorts. In order to prevent this, the semiconductor chip 20C on the back side is reversed so that the arrangement of internal element circuits and bonding pads is rotationally symmetric with respect to the semiconductor chip 20B on the front side (that is, the mirror so that the front and the back face each other). Inverted mirror chips and structures are used.

  As shown in FIG. 8B, the semiconductor chip 20C having a mirror chip structure corresponds to the bonding pads 13B-11, 13B-12,..., 13B-21, 13B-22,. Then, a plurality of bonding pads 21C (right bonding pads 21C-11, 21C-12,...) In the vicinity of the right side and the left side (as viewed from the back side, the left and right are reversed). .. Are provided on the left side bonding pads 21C-21, 21C-22,. The right bonding pads 21C-11, 21C-12,... Are connected to the left bonding pads 13B-11, 13B-12,... As viewed from the surface on the lead frame side by a plurality of wires 14C. The The right bonding pads 21C-21, 21C-22,... Are connected to the right bonding pads 13C-21, 13C-22,.

  The semiconductor chips 20B and 20C and the plurality of wires 14B and 14C are resin-sealed by the resin member 15B.

  However, the conventional semiconductor devices of FIGS. 6 and 7 and the conventional FIG. 8 have the following problems (1) and (2).

(1) Problems of Conventional FIGS. 6 and 7 For example, when the semiconductor chip 20A of FIG. 6 is mounted on the package of FIG. It cannot be connected with the wire 14A. Therefore, it is necessary to newly create the semiconductor chip 20B of FIG. 7 having the same function as the semiconductor chip 20A and having the position of the bonding pad moved.

  As described above, in the semiconductor device as shown in FIGS. 6 and 7, it is necessary to design and create a semiconductor chip for the package every time the package shape is changed. Because it is necessary to verify (operation check test), a great amount of cost and development time are required. Further, by arranging the bonding pads of the semiconductor chip 20B in accordance with the package of FIG. 7, it is necessary to increase the chip size or to have inventory for each semiconductor chip.

  In order to eliminate such inconvenience, for example, a metal wiring film for pad position conversion described in Patent Document 1 is provided on the semiconductor chip 20A of FIG. 6, and the metal wiring film of FIG. It is also conceivable to connect the bonding pads 21A on the semiconductor chip side and the bonding pads 13B on the lead frame side in FIG. 7 with wires. Alternatively, the signal position conversion unit having the wiring pattern described in Patent Document 2 is fixed to the die pad 11B in FIG. 7, and the semiconductor chip 20A in FIG. 6 is mounted on the signal position conversion unit. It is also conceivable to connect the bonding pad 21A on the semiconductor chip side in FIG. 6 and the bonding pad 13B on the lead frame side in FIG. 7 with a wire.

  However, in a configuration in which a metal wiring film as in Patent Document 1 or a signal position conversion unit as in Document 2 is provided and wire bonding is performed between bonding pads, a wiring structure for relaying or the like has not been established. As the position of the bonding pads on the chip side and the lead frame side is changed, the wiring structure for relaying etc. is changed, so for example, when probing etc. for verification of operation confirmation, new peripheral devices This is necessary, and there is a risk that the cost will increase significantly.

(2) Problem of Conventional FIG. 8 Since it is necessary to prepare two types of semiconductor chips, that is, the semiconductor chip 20B on the front side and the semiconductor chip 20C on the back side that is a mirror chip thereof, the package changes each time the package shape changes. It is necessary to design and create two kinds of semiconductor chips for the purpose, and further, it is necessary to verify the quality (probing test) by probing the two kinds of created semiconductor chips. The chip size becomes large, or it is necessary to have inventory for each semiconductor chip.

  In order to eliminate such an inconvenience, for example, a metal position film for pad position conversion described in Patent Document 1 or a signal position conversion unit having a wiring pattern described in Patent Document 2 may be used. However, similarly to the above (1), for example, when probing or the like is performed for verification of operation confirmation, a new peripheral device is required, and there is a possibility that the cost may be significantly increased.

  An object of the present invention is to solve the problems of the prior art and to provide a semiconductor device capable of easily and accurately changing the arrangement of bonding pads.

  In order to solve the above problems, in a semiconductor device according to a first aspect of the present invention, a substrate for mounting a semiconductor chip, and a plurality of leads disposed around the substrate at a predetermined distance from the substrate. And a plurality of semiconductor chips using a silicon substrate mounted on the substrate and provided with a plurality of first bonding pads, a relay member, and a plurality of first and second wires.

  The relay member includes a second bonding pad, a third bonding pad, and a plurality of wirings that electrically connect the second bonding pad and the third bonding pad. It is constructed on the plurality of semiconductor chips so as to expose the bonding pads. The plurality of first wires electrically connect the first bonding pad of each semiconductor chip and the second bonding pad of the relay member. The plurality of second wires electrically connect the lead and the third bonding pad of the relay member.

  The relay member is disposed so as to be located inside an outer edge of one region formed by the plurality of semiconductor chips, and the relay member includes the second bonding pad and the third bonding pad. And a relay chip composed of a silicon substrate on which the wiring is formed.

  In a semiconductor device of a second invention, a substrate for mounting a semiconductor chip, a plurality of leads arranged around the substrate at a predetermined distance from the substrate, and a first bonding pad mounted on the substrate Are provided with a plurality of semiconductor chips formed using a plurality of silicon substrates, a plurality of relay members, and a plurality of first and second wires.

The plurality of relay members include a second bonding pad, a third bonding pad, a wiring for electrically connecting the second bonding pad and the third bonding pad, and the second through the wiring. And a plurality of fourth bonding pads for connecting between the intermediate members electrically connected to the third bonding pads, and each of the semiconductor chips is exposed to expose the first bonding pads. Each is formed on a semiconductor chip. The plurality of first wires electrically connect the first bonding pads of the semiconductor chips and the second bonding pads of the relay members. The plurality of second wires electrically connect the lead and the third bonding pad of each relay member.

  Each of the relay members is smaller than each of the semiconductor chips and arranged to be inside the outer edge of the upper surface of each of the semiconductor chips, and each of the relay members includes the second bonding pad and A relay chip composed of a silicon substrate on which the third bonding pad and the wiring are formed is used.

  According to the semiconductor device of the first invention, the relay chip is stacked on the plurality of semiconductor chips, and the direction of the pad arrangement is changed by the relay chip. Therefore, the multichip semiconductor is not restricted by the pad arrangement. The device can be easily manufactured. In addition, since the relay chip can be configured only with bonding pads and wiring, it is possible to reduce costs required for redesign and verification of operation, development costs, and the like, compared with the case of creating a semiconductor chip with a changed pad arrangement. Furthermore, since the relay chip is stacked on the semiconductor chip, an increase in the area in the lateral direction can be suppressed and downsizing can be achieved.

  In addition, since the relay chip is fixed so as to fit inside the outer edge of one region formed by the semiconductor chip, the relay chip can be firmly fixed at a predetermined position, and the relay chip mounting and wire bonding can be easily performed. It can be done accurately. In particular, since the semiconductor chip and the relay chip are configured using a silicon substrate, wire bonding to them can be performed under substantially the same conditions, and the second and third bonding pads formed on the relay chip are connected to the second and third bonding pads. The first and second wires can be suitably bonded. In addition, the wiring of the relay chip can be changed into various forms corresponding to the conversion direction of the pad arrangement, etc., but this wiring is used when the wiring state becomes complicated and inconveniences such as short-circuiting between the wirings occur. May have a multilayer wiring structure.

  According to the semiconductor device of the second invention, the relay chips are stacked on the plurality of semiconductor chips, respectively, and the direction of the pad arrangement is changed by the plurality of relay chips, so that it is almost the same as the first invention. The effect is obtained. In addition, since the size of each relay chip can be reduced, it is possible to reduce the disconnection and the like, increase the yield of the chip, and reduce the cost.

  The semiconductor device of the first invention has a substrate for mounting a semiconductor chip, and a plurality of leads are arranged around the substrate at a predetermined distance from the substrate. A plurality of semiconductor chips using a silicon substrate on which a plurality of first bonding pads are arranged are mounted on the substrate. On the plurality of semiconductor chips, a relay member is arranged so as to be inside the outer edge of one region formed by these, and the relay member is installed so as to expose the first bonding pad. Yes.

  The relay member includes a plurality of second bonding pads, a plurality of third bonding pads, and a plurality of wirings that electrically connect the second bonding pads and the third bonding pads. A relay chip composed of a silicon substrate is used. The first bonding pad of each semiconductor chip and the second bonding pad of the relay member are electrically connected by a plurality of first wires, and the lead and the third bonding pad of the relay member are They are electrically connected by a plurality of second wires.

  In the semiconductor device of the second invention, a plurality of relay chips are used instead of the relay member of the first invention, and each of these relay chips is mounted on each semiconductor chip.

  Before describing Example 1 of the present invention, first, a reference example of the present invention will be described.

  3A, 3B, and 3C are schematic configuration diagrams of an SOP type semiconductor device showing a reference example of the present invention, and FIG. 3A is a plan view in which a part is omitted. (B) is a cross-sectional view of FIG. (A) cut in the horizontal direction, and (C) is a cross-sectional view of FIG. (A) cut in the vertical direction.

  This SOP type semiconductor device uses, for example, a lead frame 30 as a substrate for mounting a semiconductor chip. As shown in FIG. 3A, the lead frame 30 includes a die pad 31 for mounting a semiconductor chip having a substantially rectangular plane, and a plurality of lead frames 30 are laterally separated from the left and right sides of the die pad 31 by a predetermined distance. A lead 32 is disposed. The plurality of leads 32 are formed on the inner lead portion on the inner side by a first bonding pad 33 (left bonding pads 33-11, 33-12,..., Right bonding pads 33-21, 33-22,... -) Is provided, and the outer outer lead portion is pulled out in the lateral direction.

  A semiconductor chip 40 having a substantially rectangular plane is fixed to the surface of the die pad 31. The semiconductor chip 40 includes a semiconductor memory, a semiconductor integrated circuit (hereinafter referred to as “IC”), and the like formed on a substrate such as silicon, and a plurality of first bonding pads 41 (upper side) near the upper and lower sides of the surface. , Bonding pads 41-11, 41-12,..., And lower bonding pads 41-21, 41-22,.

  A relay chip 50, which is a relay member having a substantially rectangular plane, is fixed by an insulating adhesive 45 so as to fit inside the outer edge of the surface of the semiconductor chip 40. The relay chip 50 includes a thin substrate such as silicon or glass epoxy resin, and a plurality of bonding pads 51 (upper second bonding pads 51-11, 51-12,. .., Lower second bonding pads 51-21, 51-22,..., Left third bonding pads 51-31, 51-32,. -41, 51-42, ...) are arranged.

  A wiring pattern 52 made of a conductive film or the like is formed on the substrate of the relay chip 50, and a plurality of bonding pads 51 are connected to each other by the wiring pattern 52. For example, the upper half of the upper bonding pads 51-11, 51-12,... Are connected to the upper half of the left bonding pads 51-31, 51-32,. The right halves of 51-11, 51-12,... Are connected to the upper halves of the right bonding pads 51-41, 51-42,. ,... Are connected to the lower half of the left bonding pads 51-31, 51-32,..., And the lower bonding pads 51-21, 51-22,. The right half is connected to the lower half of the right bonding pads 51-41, 51-42,.

  A plurality of first bonding pads 41 on the semiconductor chip side are connected to a plurality of second bonding pads 51-11, 51-12,..., 51- on the relay chip side by a plurality of first wires 61. Are connected to the plurality of bonding pads 51-11, 51-12,..., 51-21, 51-22,. A plurality of third bonding pads 51-31, 51-32,..., 51-41, 51-42,. The plurality of bonding pads 33 are connected.

  For example, the left half of the bonding pads 41-11, 41-12,... On the upper side of the semiconductor chip 40 is connected to the bonding pads 33-11, 33- on the left side of the lead frame 30 via the wires 61 and the relay chip 50. The right half of the bonding pads 41-11, 41-12,... Connected to the upper half of the semiconductor chip 40 is connected to the lead frame 30 via the wire 61 and the relay chip 50. Are connected to the upper half of the right bonding pads 33-21, 33-22,. Similarly, the left half of the bonding pads 41-21, 41-22, ... on the lower side of the semiconductor chip 40 is the lower half of the bonding pads 33-11, 33-12, ... on the left side of the lead frame 30. The right half of the bonding pads 41-21, 41-22,... On the lower side of the semiconductor chip 40 is below the bonding pads 33-21, 33-22,. Connected in half.

  The die pad 31, the semiconductor chip 40, the relay chip 50, the wires 61 and 62, and the bonding pad 33 portion of the lead frame 32 are sealed with a resin member 70. The outer lead portion of the lead 32 protrudes from the resin member 70 and is bent downward substantially in an L shape.

  FIG. 4 is a diagram illustrating an example of a manufacturing method of the semiconductor device of FIG.

  The semiconductor device of FIG. 3 is manufactured by, for example, (1) a chip bonding process, (2) a mounting process, (3) a wire bonding process, and (4) a sealing process. Hereinafter, each manufacturing process will be described.

(1) Chip Bonding Process The semiconductor chip 40 is held by a die bonder, and the back surface of the semiconductor chip 40 is fixed to the surface of the die pad 31 of the lead frame 30 with an adhesive such as silver paste.

(2) Mounting process An insulating adhesive 45 is formed on the substantially central portion of the surface of the semiconductor chip 40 or on the back surface of the relay chip 50. As the adhesive material 45, for example, a low-stress paste material using an epoxy resin or the like, or a film material such as a thermoplastic resin or a thermosetting resin may be used.

  The relay chip 50 is held by the die bonder, and the back surface of the relay chip 50 is fixed by the adhesive 45 so as to be inside the outer edge of the front surface of the semiconductor chip 40.

  At the time of fixing, it is desirable to reduce the impact force received by the semiconductor chip 40 by adjusting the contact pressure and moving speed of the die bonder. Further, in order to buffer the impact force, an adhesive 45 having an impact buffer function may be used, or an impact buffer pad or the like may be separately provided between the semiconductor chip 40 and the relay chip 50.

(3) Wire Bonding Process Using a wire bonder, the bonding pad 41 of the semiconductor chip 40 and the bonding pad 51 of the relay chip 50 are connected by the wire 61, and the bonding pad 51 of the relay chip 50 and the bonding pad of the lead frame 30 are connected. 33 is connected by a wire 62.

(4) Sealing Step, etc. The lead frame 30 on which the semiconductor chip 40 and the relay chip 50 are mounted is set in, for example, a mold molding machine, and the semiconductor chip 40 is relayed by molding with a resin member 70 such as epoxy resin. The chip 50 and the wires 61 and 62 are sealed with resin.

  If the resin, burrs, unnecessary portions and the like of the lead frame 30 are removed and the outer lead portion of the lead 32 is bent into a desired shape, the manufacture of the semiconductor device of FIG. 1 is completed. Thereafter, the quality is verified by a tester as necessary.

  In the semiconductor device of FIG. 3, since the outer lead portion of the lead 32 and the semiconductor chip 40 are electrically connected via the relay chip 50 and the wires 61 and 62, signal input to the outer lead portion. If output is performed, a predetermined electrical operation is performed.

  This reference example has the following effects (a) to (g).

  (A) The relay chip 50 is stacked on the semiconductor chip 40, and the pad arrangement is changed to a substantially right angle direction so that the relay chip 50 can be connected to the bonding pad 33 on the lead frame 30 side. Therefore, for example, even if the conventional semiconductor chip 20B as shown in FIG. 7 is not formed, it can be mounted on the package as shown in FIG.

  (B) Since the relay chip 50 can be configured by only the bonding pad 51 and the wiring pattern 52, the cost required for redesign and verification of the operation, compared with the case where the conventional semiconductor chip 20B as shown in FIG. Development costs can be reduced.

  (C) Since the relay chip 50 is stacked on the semiconductor chip 40 without increasing the chip size by arranging the pads in accordance with the conventional semiconductor chip 20B as shown in FIG. The area required to place the is not increased.

  (D) Since the relay chip 50 is fixed so as to be inside the outer edge of the surface of the semiconductor chip 40, the relay chip 50 can be firmly fixed at a predetermined position. Therefore, the relay chip 50 is not displaced from the predetermined mounting position due to the force applied when the relay chip is mounted or wire bonding, and the relay chip mounting and wire bonding can be performed easily and accurately.

  (E) For example, when an adhesive having an impact buffering function is used as the adhesive 45, or an impact buffer pad or the like is separately provided between the semiconductor chip 40 and the relay chip 50, when the relay chip 50 is fixed, The impact force received by the semiconductor chip 40 can be reduced, and thereby the failure rate of the semiconductor chip 40 can be reduced.

  (F) The wiring pattern 52 of the relay chip 50 can be changed into various forms corresponding to the conversion direction of the pad arrangement. At this time, when the wiring state becomes complicated and inconveniences such as short-circuiting between the wirings occur, the wiring pattern 52 may have a multilayer wiring structure as shown in FIG. 5, for example.

  (G) FIG. 5 is a schematic enlarged sectional view showing an example of a multilayer wiring structure.

  The relay chip 50 includes a thin substrate 50a such as silicon or glass epoxy resin. On the substrate 50a, conductive films 50b for forming the wiring patterns 52 and interlayer insulating films 50c are alternately arranged and formed in a stacked state. The conductive film 50b is connected to the bonding pad 51 through a contact hole 50d or the like. By using such a laminated structure, a complicated wiring pattern 52 can be easily formed without causing a short circuit between the wirings.

  Next, the configuration, manufacturing method, effects, and the like of the first embodiment of the present invention will be described.

(Configuration etc.)
FIGS. 1A and 1B are schematic configuration diagrams of a semiconductor device in the form of a multi-chip package showing Example 1 of the present invention, and FIG. The figure and the figure (B) are the longitudinal cross-sectional views which abbreviate | omitted one part, and the same code | symbol is attached | subjected to the element which is common in the element in FIG. 3 which shows a reference example.

  In this multi-chip package semiconductor device, a plurality of (for example, two) semiconductor chips 40A-1 and 40A-2 having a substantially rectangular plane are formed on the surface of the die pad 31 of the lead frame 30 as shown in FIG. Further, one relay having a substantially rectangular plane is formed by an adhesive 45 similar to that of FIG. 3 so as to fit inside the outer edge of one region formed by the semiconductor chips 40A-1 and 40A-2. A relay chip 50F, which is a member, is fixed.

  Each of the semiconductor chips 40A-1 and 40A-2 is provided with a plurality of first bonding pads 41 in the vicinity of two opposing sides of the surface. The relay chip 50F corresponds to the plurality of bonding pads 41 of the semiconductor chips 40A-1 and 40A-2 and the bonding pad 33 of each lead 32, and a plurality of second chips in the vicinity of the two opposing sides of the surface. A third bonding pad 51 is provided. The plurality of bonding pads 51 are connected to each other by a wiring pattern 52F having a multilayer wiring structure as shown in FIG.

  The plurality of second bonding pads of the bonding pad 51 on the relay chip 50F side are connected to the plurality of first bonding pads 41 on the semiconductor chip 40A-1 and 40A-2 side by a plurality of first wires 61. Further, a plurality of third bonding pads other than the bonding pad 51 are connected to a plurality of bonding pads 33 (33-1, 33-2,... On the lead frame 30 side by a plurality of second wires 62. ··)It is connected to the.

  The semiconductor chips 40A-1 and 40A-2, the relay chip 50F, the wires 61 and 62, and the like are resin-sealed by the resin member 70 as in FIG. Other configurations and operations are substantially the same as those in FIG.

(Production method)
Similar to the manufacturing method of FIG. 3, in the chip bonding step, the back surfaces of the semiconductor chips 40A-1 and 40A-2 are fixed to the surface of the die pad 31. In the mounting process, the relay chip 50F is fixed with the adhesive 45 so as to be inside the outer edge of one region formed by the semiconductor chips 40A-1 and 40A-2. Next, in the wire bonding step, a plurality of first bonding pads 41 on the semiconductor chips 40A-1 and 40A-2 side are connected to a plurality of second bonding pads 51 on the relay chip 50F side by a first wire 61. A plurality of third bonding pads other than the bonding pad 51 are connected to the bonding pads 33 (33-1, 33-2,... On the lead frame 30 side by the second wires 62. ).

  Thereafter, in the sealing step, the semiconductor chips 40A-1 and 40A-2, the relay chip 50F, the wires 61 and 62, and the like are resin-sealed with the resin member 70. The manufacture of the semiconductor device of FIG.

(Effects etc.)
The first embodiment has the following effects (I) to (V).

  (I) The relay chip 50F is stacked on the semiconductor chips 40A-1 and 40A-2, and the pad arrangement direction is changed so that the relay chip 50F can be connected to the bonding pad 33 on the lead frame 30 side. . Therefore, a semiconductor device in the form of a multichip package can be manufactured without being restricted by the pad arrangement.

  (II) Since the relay chip 50F is composed only of the bonding pad 51 and the wiring pattern 52F having a multilayer wiring structure, the cost required for redesign and verification of operation is higher than when a semiconductor chip with a changed pad arrangement is created. Or, development costs can be reduced.

  (III) Since the relay chip 50F is fixed so as to fit inside the outer edge of one region formed by the semiconductor chips 40A-1 and 40A-2, the relay chip 50F can be firmly fixed at a predetermined position. . For this reason, the relay chip 50F is not displaced from the predetermined mounting position due to the force applied at the time of relay chip mounting or wire bonding, and the relay chip mounting and wire bonding can be performed easily and accurately. In particular, when the semiconductor chips 40A-1 and 40A-2 and the relay chip 50F are configured using a silicon substrate, wire bonding to them can be performed under substantially the same conditions, and bonding formed on the relay chip 50F. Wires 61 and 62 can be suitably bonded to the pad 51.

  (IV) For example, if an adhesive having an impact buffer function is used as the adhesive 45, or if an impact buffer pad or the like is separately provided between the semiconductor chips 40A-1, 40A-2 and the relay chip 50F, the relay chip When 50F is fixed, the impact force received by the semiconductor chips 40A-1 and 40A-2 can be reduced, thereby reducing the failure rate of the semiconductor chips 40A-1 and 40A-2.

  (V) Three or more semiconductor chips 40A-1 and 40A-2 may be provided. Further, the wiring pattern 52F of the relay chip 50F can be changed into various forms corresponding to the conversion direction of the pad arrangement.

(Configuration etc.)
2A and 2B are schematic configurations of a semiconductor device in the form of a multichip package showing a second embodiment of the present invention, and FIG. 2A is a plan view with a part omitted as viewed from the surface. FIG. 3B is a longitudinal sectional view with a part omitted, and elements common to those in FIGS. 3 and 1 showing the reference example and Example 1 are denoted by common reference numerals.

  In this multi-chip package semiconductor device, a plurality of (for example, two) semiconductor chips 40A-1 and 40A-2 similar to FIG. 1 are formed on the surface of the die pad 31 of the lead frame 30 as shown in FIG. Further, the relay chip 50G-1 is a relay member having a substantially rectangular plane by an adhesive 45 similar to that shown in FIG. 3 so as to fit inside the outer edges of the surfaces of the semiconductor chips 40A-1 and 40A-2. , 50G-2 are fixed to each other.

  Each relay chip 50G-1, 50G-2 fixed on each semiconductor chip 40A-1, 40A-2 corresponds to a plurality of first bonding pads 41 of the semiconductor chips 40A-1, 40A-2. A plurality of second and third bonding pads 51 are disposed in the vicinity of the two opposing sides of the surface. In addition, a plurality of fourth bonding pads 51 are also provided near the other side of each relay chip 51G-1, 51G-2 as necessary. The plurality of second, third, and fourth bonding pads 51 are connected to each other by wiring patterns 52G-1 and 52G-2 having a multilayer wiring structure as shown in FIG.

  The plurality of second bonding pads of the bonding pads 51 on the relay chips 50G-1 and 50G-2 side are connected to the plurality of first wires 61 on the semiconductor chips 40A-1 and 40A-2 side by the plurality of first wires 61. Further, a plurality of third bonding pads other than the bonding pad 51 are connected to a plurality of bonding pads 33 (33-1 on the lead frame 30 side) by a plurality of second wires 62. , 33-2,... When connection between the relay chip 50G-1 and the relay chip 50G-2 is necessary, the fourth bonding pad 51 on the relay chip 50G-1 side and the fourth bonding pad on the relay chip 50G-2 side 51 may be connected by a wire 63.

  These semiconductor chips 40A-1, 40A-2, relay chips 50G-1, 50G-2, wires 61, 62, 63, and the like are resin-sealed by a resin member 70 as in FIGS. Yes. Other configurations and operations are substantially the same as those in FIGS.

(Production method)
3 and 1, the back surfaces of the semiconductor chips 40A-1 and 40A-2 are fixed to the surface of the die pad 31 in the chip bonding step. In the mounting step, the relay chips 50G-1 and 50G-2 are fixed with the adhesive 45 so as to be inside the outer edges of the surfaces of the semiconductor chips 40A-1 and 40A-2.

  Next, in the wire bonding step, a plurality of first bonding pads 41 on the semiconductor chips 40A-1 and 40A-2 side are bonded to the bonding pads 51 on the relay chips 50G-1 and 50G-2 side by the first wires 61. Are connected to the plurality of second bonding pads, and the other plurality of third bonding pads of the bonding pad 51 are connected to the bonding pads 33 (33-1, 33 on the lead frame 30 side) by the second wires 62. -2, ...). When the connection between the relay chip 50G-1 and the relay chip 50G-2 is necessary, the fourth bonding pad 51 on the relay chip 50G-1 side and the fourth bonding pad 51 on the relay chip 50G-2 side Are connected by a wire 63.

  Thereafter, in the sealing step, the semiconductor chips 40A-1 and 40A-2, the relay chips 50G-1, 50G-2, the wires 61, 62, 63, and the like are resin-sealed with the resin member 70. If the process similar to that in FIG. 1 is performed, the manufacture of the semiconductor device in FIG. 2 is completed.

(Effects etc.)
In the second embodiment, there are the effects (I) to (V) of the first embodiment and the following effects (VI).

  (VI) Compared with the first embodiment, the relay chip 50F in FIG. 1 is divided into the relay chip 50G-1 and the relay chip 50G-2 to reduce the relay chip size, so that the disconnection and the like are reduced and the yield is improved. The cost can be reduced.

  The present invention is not limited to the reference example and the first and second embodiments, and various modifications are possible. As a third embodiment which is this modification, for example, there are the following (i) and (ii).

  (I) Although the example using the die pad 31 of the lead frame 30 has been described as the substrate for mounting the semiconductor chip, other substrates such as a wiring substrate, a semiconductor substrate, and a glass epoxy substrate may be used.

  (ii) The illustrated pad arrangement and the wiring pattern of the relay chip are merely examples, and can be changed to various forms according to the conversion direction of the pad arrangement. Moreover, a manufacturing method and a manufacturing material can be changed arbitrarily.

  In the above reference examples and examples, the SOP type package has been described. However, by changing the lead shape of the outer lead portion of the lead frame 30, other package shapes such as QFP can be used. In addition to the resin-encapsulated package, other packages such as a hollow package may be used.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram of the semiconductor device which shows Example 1 of this invention. It is a schematic block diagram of the semiconductor device which shows Example 2 of this invention. It is a schematic block diagram of the semiconductor device which shows the reference example of this invention. It is a figure which shows an example of the manufacturing method of FIG. It is a general | schematic expanded sectional view which shows an example of a multilayer wiring structure. It is a schematic block diagram of the conventional semiconductor device. It is a schematic block diagram of the conventional semiconductor device. It is a schematic block diagram of the conventional semiconductor device.

Explanation of symbols

30 Lead frame 31 Die pad 32 Lead 33, 41, 51 Bonding pad 40, 40A-1, 40A-4 Semiconductor chip 45 Adhesive 50, 50F, 50G-1, 50G-2 Relay chip 52, 52F, 52G-1, 52G -2 wiring pattern 61, 62, 63 wire

Claims (4)

A substrate for mounting a semiconductor chip;
A plurality of leads disposed around the substrate at a predetermined distance from the substrate;
A plurality of semiconductor chips mounted on the substrate and using a silicon substrate on which a plurality of first bonding pads are arranged;
A plurality of second bonding pads, a third bonding pad, and a wiring for electrically connecting the second bonding pad and the third bonding pad, and exposing the first bonding pad A relay member erected on the plurality of semiconductor chips,
A plurality of first wires that electrically connect the first bonding pad of each of the semiconductor chips and the second bonding pad of the relay member;
A plurality of second wires that electrically connect the lead and the third bonding pad of the relay member;
The relay member is disposed so as to be located inside an outer edge of one region formed by the plurality of semiconductor chips,
2. A semiconductor device according to claim 1, wherein the relay member is a relay chip including a silicon substrate on which the second bonding pad, the third bonding pad, and the wiring are formed. A substrate for mounting a semiconductor chip;
A plurality of leads disposed around the substrate at a predetermined distance from the substrate;
A plurality of semiconductor chips mounted on the substrate and using a silicon substrate on which a plurality of first bonding pads are arranged;
A second bonding pad; a third bonding pad; and a plurality of wirings that electrically connect the second bonding pad and the third bonding pad. A plurality of relay members respectively formed on each of the semiconductor chips so as to expose the bonding pads;
A plurality of first wires that electrically connect the first bonding pads of the semiconductor chips and the second bonding pads of the relay members;
A plurality of second wires that electrically connect the leads and the third bonding pads of the relay members;
Each of the relay members is smaller than each of the semiconductor chips, and is disposed so as to fit inside the outer edge of the upper surface of each of the semiconductor chips.
Wherein each relay member, the second bonding pad and the third bonding pad and configured relay chip from the silicon substrate in which wiring and is formed is found using,
Further, each of the relay members is provided with a plurality of fourth bonding pads for connection between intermediate members electrically connected to the second and third bonding pads by the wiring. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the wiring of the relay chip has a multilayer wiring structure in which interlayer insulating films and conductive films are alternately arranged. 3. The semiconductor device according to claim 1, wherein the semiconductor chip mounting substrate is a lead frame die pad.

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