JP2003060126A - Manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a mounting area and the manufacturing cost by modularizing a semiconductor chip in a batch-molding method. SOLUTION: A BGA semiconductor device 1 has a module structure, in which two semiconductor chips 3 are mounted on a printed wiring board 2 with a bonding material. This semiconductor device 1, is formed in a batch- molding method, in which a plurality of device regions are resin-molded so as to be covered in block. In the printed wiring board 2, a plurality of bonding electrodes 2a are formed on the peripheral parts of the semiconductor chips 3, respectively, and outer circumferential wiring patterns 2b are formed on outer circumferential parts of these bonding electrodes 2a, respectively. The outer circumferential wiring patterns 2b are wired, so as to cross each other at right angles, and bonding electrodes 2e1 -2e12 among the bonding electrodes 2a, to which common signals such as address signals are inputted, are connected to them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for miniaturizing a semiconductor device, and more particularly to a technique effectively applied to modularization of a semiconductor device formed by collective molding.

[0002]

2. Description of the Related Art According to a study by the present inventor, personal computers, workstations, etc.
A so-called motherboard is provided. This motherboard is a printed wiring board on which the basic components of a computer are mounted, and includes a microcomputer, a semiconductor memory used as a main memory, and a basic input / output system (BIOS).
ROM (Read Only) that stores the system
A semiconductor memory such as a memory) and various electronic components such as an expansion slot are mounted.

As a semiconductor memory of the main memory device, for example, a DRAM (Dynamic Random) is used.
m Access Memory) and the like are used.

In general, a plurality of semiconductor memories of this main memory device are mounted in order to cope with an increase in the capacity of the memory, and in order to meet the demands for downsizing, a large number of pins, etc., a CSP is used. (Chip Size Package)
In addition, small packages such as LGA (Land Grid Array) are being used.

As an example in which this type of memory has been described in detail, September 10, 1996, published by Nikkei BP, Nikkei Byte (ed.), "Latest PC Technology System '9"
7 ”P79 to P82, and this document describes the configuration of a memory system used in a personal computer or the like.

[0006]

However, the present inventor has found that the mounting technique for a plurality of semiconductor devices such as the semiconductor memory as described above has the following problems.

That is, when mounting a plurality of semiconductor memories on a motherboard, a certain clearance must be secured in each memory, and the mounting area of the motherboard increases as the number of mounted memories increases. However, there is a problem in that it becomes difficult to reduce the size of the motherboard itself and the manufacturing cost increases.

Further, in a package such as CSP or LGA, since external terminals are provided on the back surface (mounting surface side) of the package, it becomes difficult to route the wiring pattern, and the mother board becomes a multilayer wiring, resulting in cost reduction. There is a problem that it invites up.

An object of the present invention is to provide a method of manufacturing a semiconductor device, which can modularize semiconductor chips by a collective molding method and can significantly reduce the mounting area and the manufacturing cost.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the method of manufacturing a semiconductor device according to the present invention has a common bonding common electrode having a plurality of device regions to which a common signal is input, a common wiring pattern for commonly connecting the bonding common electrodes, and a common wiring pattern. A step of preparing a printed wiring board having a bonding electrode to which an independent signal other than a signal is formed, a step of mounting a semiconductor chip in a device region, a surface electrode of the semiconductor chip and a printed wiring board corresponding thereto Step of connecting the bonding common electrode and the bonding electrode with a connecting member, and a step of collectively covering a plurality of device regions on the printed wiring board with a molding resin to seal the semiconductor chip with a resin and form a collective sealing portion. And the print layout for each device area along the dicing line. Singulation by dividing the substrate and the block molding portion, and a step of forming individual sealed portion.

A method of manufacturing a semiconductor device according to the present invention is
A bonding common electrode having a plurality of device regions to which an address signal is input, a common wiring pattern for commonly connecting the bonding common electrodes, and a bonding electrode to which an independent signal other than the address signal is input are formed. A step of preparing a printed wiring board, a step of mounting a semiconductor chip in a device region, and a step of connecting a surface electrode of the semiconductor chip and a bonding electrode of a printed wiring board corresponding to the surface electrode and a bonding common electrode by a connecting member. And cover a plurality of device areas on the printed wiring board with molding resin at once.
The process of resin-sealing the semiconductor chip and forming the collective sealing part, and dividing the printed wiring board and the collective sealing part into individual device areas along the dicing line into individual pieces, And a step of forming.

Further, the semiconductor device manufacturing method of the present invention has a plurality of device regions, a bonding common electrode formed in the device regions to which an address signal is input, and an independent signal other than the address signal are input. And a bonding electrode is formed in the device region, and a common wiring pattern for commonly connecting the bonding common electrodes is prepared in the peripheral portion of the dicing line. The step of mounting, the step of connecting the surface electrode of the semiconductor chip and the corresponding bonding electrode of the printed wiring board, and the bonding common electrode by a connecting member, and a plurality of device regions in the printed wiring board are collectively formed by molding resin. And seal the semiconductor chip with resin. And a step of forming a collective sealing portion, and a step of dividing the printed wiring board and the collective sealing portion into individual pieces along the dicing line for individual device regions to form individual sealing portions. It is a thing.

As described above, when a semiconductor device having a module structure is formed by dividing a plurality of device regions into a series, a bonding common electrode to which a common signal is input is connected on the printed wiring board. The wiring density of a motherboard on which the semiconductor device is mounted can be reduced, and the semiconductor device itself can be miniaturized by the collective molding method.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an external perspective view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an explanatory view of a printed wiring board used in the semiconductor device of FIG. 1, and FIG. 3 is a semiconductor device of FIG. FIG. 4 is an explanatory view of a multi-cavity substrate used in the manufacture of FIG. 4, FIG. 4 is a wiring explanatory diagram of an outer peripheral wiring pattern in the multi-cavity substrate of FIG. 3, and FIGS. 10 and 10 are flowcharts of manufacturing steps in the semiconductor device of FIG. 1, and FIG. 11 is an explanatory diagram showing an example of cutting out a device region according to one embodiment of the present invention.

In the present embodiment, the semiconductor device 1 is
It is a semiconductor memory such as a DRAM mounted on a motherboard of a personal computer or the like. Semiconductor device 1
Is a BGA (Bal) which is one of surface mount type packages.
l Grid Array) and is formed by the MAP method.

As shown in FIGS. 1 and 2, the semiconductor device 1 is provided with a printed wiring board 2 made of, for example, glass epoxy resin. Here, FIG. 2 is an explanatory view showing the semiconductor device 1 in which a package is not formed. Further, the printed wiring board 2 may be other than the printed board, and may be configured by using a tape substrate such as polyimide.

Two semiconductor chips 3 are mounted on the main surface of the printed wiring board 2 via an adhesive such as an insulating resin. Therefore, the semiconductor device 1 has a memory module configuration in which the two semiconductor chips 3 are provided.

On the back surface of the printed wiring board 2, connection electrodes arranged in an array corresponding to the two semiconductor chips 3 and wiring patterns are formed. On the main surface of the printed wiring board 2 (mounting surface of the semiconductor chip 3), a plurality of bonding electrodes 2a are formed in the vicinity of the peripheral portion of the semiconductor chip 3, and in the vicinity of the outer peripheral portion of these bonding electrodes 2a, A plurality of outer peripheral wiring patterns (common wiring patterns) 2b are formed respectively.

The bonding electrode 2a and the connecting electrode are
Wiring pattern 2 formed on both sides of printed wiring board 2
c, and through holes 2d, etc., for electrical connection.

The outer peripheral wiring pattern 2b is wired in the long side direction and the short side direction of the printed wiring board 2, respectively. These outer peripheral wiring patterns 2b, for example, of the bonding electrodes 2a, bonding electrodes (bonding common electrode) 2e ₁ ~2e ₁₂ common signals such as address signals (common signal) is input are connected.

Further, the outer peripheral wiring pattern 2 of different signals
At a portion where b intersects, one wiring pattern is arranged in a lower layer as shown by a dotted line in FIG. 2 so that it is not electrically short-circuited.

Therefore, the bonding electrode 2e ₁ corresponding to one semiconductor chip 3 and the bonding electrode 2e ₁ corresponding to the other semiconductor chip 3 are the outer peripheral wiring pattern 2
This means that they are commonly connected via b.

Solder bumps 4 made of spherical solder are formed on the connecting electrodes on the back surface of the printed wiring board 2. On the main surface of the semiconductor chip 3, a plurality of electrodes (surface electrodes) 3a are formed near the outer peripheral portion of the semiconductor chip 3, respectively. Predetermined bonding electrodes 2a are connected to these electrodes 3a via bonding wires (connection members) 5, respectively.

The semiconductor chip 3, the periphery of the bonding electrode 2a of the printed wiring board 2 and the bonding wire 5 are sealed with a sealing resin 6 to form a package.

Further, when the semiconductor device 1 is mounted on a printed circuit board on which electronic parts such as a mother board are mounted, the solder bumps 4 are superposed on electrodes such as lands formed on the printed circuit board. It is mounted and electrically connected by performing reflow.

Next, the semiconductor device 1 according to the present embodiment
1, 2, and 3 are explanatory views of the multi-cavity substrate 7, connection explanatory diagrams of the outer peripheral wiring pattern 2b in the multi-cavity substrate 7 of FIG. 4, and the manufacturing steps of FIGS. Will be described with reference to the explanatory diagram of FIG.

5 to 9 are drawings in which a part is omitted. In these FIGS. 5 to 9, the outer peripheral wiring pattern 2 is shown.
b, the wiring pattern 2c, the through hole 2d, etc. are not shown.

First, the multi-cavity substrate 7 and the semiconductor chip 3 mounted on the multi-cavity substrate 7 are prepared (step S101). As shown in FIG. 3, a plurality of device regions 7a arranged in a matrix and dicing lines 7b separating the device regions 7a are formed on the multi-piece substrate 7, and the plurality of device regions 7 are formed.
A batch molding is performed in which a resin is molded so as to collectively cover a.

Further, the semiconductor device 1 is obtained by dicing so that the two device regions in the collective molding portion 8 formed by this collective molding are continuous. The dicing line 7b includes a part of the device area 7a, the multi-piece substrate 7 and the device area 7.
This is a region that is separated from the portion a.

Further, the peripheral wiring pattern 2b (FIG. 2) described above is formed near the peripheral portion of the device region 7a.

Here, the connection structure of the outer peripheral wiring pattern 2b will be described with reference to FIG. In this FIG. 4 shows only the connection structure of four device areas 7a ₁ formed in ～7A ₄ perimeter wiring pattern 2b shown by circles of multi-chip substrate 7 in FIG. 3, the bonding electrodes 2
a, through hole 2d, and wiring 2f to the external electrode
Are not shown.

The outer peripheral wiring pattern 2b is configured many long side direction of the chip substrate 7, and the short side direction is formed by 12, respectively the outer peripheral wiring pattern 2b ₁ ~2b _12. These outer peripheral wiring pattern 2b ₁ ~2b _12, bonding electrodes 2e ₁ ~2e ₁₂ provided in the device region 7a ₁ ~7a ₄ are respectively connected in common.

For example, the bonding electrodes 2e ₁ provided in the device regions 7a _{1 to} 7a ₄ are the outer peripheral wiring patterns 2b in the long side direction and the short side direction of the multi-piece substrate 7.
All are commonly connected by ₁ . Similarly, the bonding in the device region 7a ₁ ~7a ₄ electrodes 2
e ₁₂ are all commonly connected via the outer peripheral wiring pattern 2b ₁₂ .

As described above, the bonding electrodes 2e _{1 to} 2e ₁₂ formed on the multi-piece substrate 7 are connected in common by the outer peripheral wiring patterns 2b _{1 to} 2b ₁₂ .

In the device area 7a, the above-mentioned bonding electrode 2a, outer peripheral wiring pattern 2b, wiring pattern 2c, through hole 2d, wiring 2f to the external electrode,
Also, the connection electrodes and the like are respectively formed, and after dicing and dividing into individual pieces, the printed wiring board 2 (FIG. 2) described above is obtained.

Thereafter, an adhesive material is applied to each semiconductor chip mounting surface of the multi-piece substrate 7 and, as shown in FIG.
The semiconductor chips 3 are mounted and bonded and fixed (step S102).

Then, as shown in FIG. 6, the semiconductor chip 3
The electrode 3a and the bonding electrode 2a formed on the multi-piece substrate 7 are joined by the bonding wires 5 and electrically connected (step S103).

After this wire bonding, as shown in FIG. 7, the semiconductor chip 3 and the bonding wire 5 are sealed with a sealing resin 6 by performing a batch molding using a transfer molding mold (step S104). Then, the mold resin is cured to form the collective mold section (collective sealing section) 8. As the mold resin, for example, an epoxy thermosetting resin or the like is used.

Thereafter, as shown in FIG. 8, the solder bumps 4 are formed on the connection electrodes formed on the back surface of the multi-piece substrate 7 (step S105).

For the solder bumps 4, for example, a semiconductor chip mounting surface of the multi-cavity substrate 7 faces downward, and a ball mounting jig holding a plurality of solder bumps 4 by vacuum suction is arranged above the solder bumps 4, and a multi-cavity soldering is performed. It is formed by mounting on the connection electrodes on each device region 7a from above the substrate 7.

After the collective mold portion 8 is formed, as shown in FIG. 9, the collective mold portion 8 is divided into individual pieces by dicing using a blade B which is a cutting blade for dicing ( Step S106).

In this case, the dicing cuts the package according to the customer's request. This package is
The device area 7a is a single device, the double module in which the two device areas 7a are connected, the four module in which the four device areas 7a are connected in a square shape, or the four vice areas 7a are connected in a rectangular shape 4 It can have various shapes such as a continuous module.

These cutout examples are shown as cutout example A to cutout example E in FIG. 11 (from the left side to the right side in FIG. 11).
Show. The cutout example A is a case of a single device, and individual device regions 7a are cut out to form one single device. Further, the cutout example B is a case of a double module in which two device regions 7a are connected, and is formed by dicing in the long side direction of the multi-piece substrate 7 in a state where the two device regions 7a are connected.

The cutout example C has four device areas 7a.
Is a case of a quadruple module connected in a square shape, and dicing is performed in a state where two device regions 7a are connected in the long side direction and the short side direction of the multi-piece substrate 7 respectively.

The cut-out example D is a case of a quadruple module in which four vice regions 7a are connected in a rectangular shape, and four device regions 7 in the short side direction of the multi-piece substrate 7 are formed.
The dicing is performed in the state where a is continuous.

The cut-out example E is a case of a quad module in which four device regions 7a are connected in a rectangular shape as described above, and four vice regions 7a in the long side direction of the multi-piece substrate 7 are connected. Dicing in the state.

Here, since the semiconductor device 1 (FIG. 1) is a double module in which two device regions 7a are continuous, dicing according to the cutout example B is performed. At this time, as a measure against the warp of the package, as shown in FIG. 12, the sealing resin 6 between the continuous device regions 7a may be half-cut to form the groove M.

Then, in the process of step S106, the package is formed by finishing the dicing, and the semiconductor device 1 shown in FIG. 1 is completed (step S107).

Further, by stocking the collective molding portion 8 in a state where it is formed and dicing it into an arbitrary module according to a customer's request, it is possible to greatly shorten the time until product shipment.

As a result, in the present embodiment, the semiconductor device 1 such as a memory module can be formed only by dicing the collective molding portion 8 into a shape according to the request, so that the size of the semiconductor device 1 can be reduced. Can be made possible.

Also, the bonding electrodes 2e _{1 to} 2e ₁₂ to which a common signal such as an address signal is input to the semiconductor device 1.
As a result, the printed wiring board such as a mother board on which the semiconductor device 1 is mounted can be miniaturized, and the electronic device such as a personal computer can be reduced in cost and miniaturized.

Further, by forming the semiconductor device 1 by the collective molding method, a semiconductor device having a module structure can be manufactured at low cost.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications are possible without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above embodiment, solder bumps are formed as connecting electrodes of the printed wiring board,
Although the electrodes of the semiconductor chip and the bonding electrodes of the printed wiring board are connected via bonding wires, as shown in FIG. 13, lands L are provided as connecting electrodes instead of solder bumps or the like. A semiconductor device 1a or a semiconductor device 1b configured to connect electrodes of a semiconductor chip and bonding electrodes of a printed wiring board via metal bumps KB such as gold bumps instead of bonding wires as shown in FIG. It may be.

Further, the semiconductor device according to the above-described embodiment has a stacked structure in which, for example, two (or more) semiconductor chips are stacked, so that higher density can be realized.

[0059]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) Since the bonding common electrodes to which the common signal is input are connected by the common wiring pattern of the printed wiring board, it is possible to reduce the number of wirings such as a mother board on which the semiconductor device is mounted.

(2) By forming the semiconductor device by the collective molding method, the semiconductor device itself having a module structure can be downsized and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is an external perspective view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a printed wiring board used in the semiconductor device of FIG.

FIG. 3 is an explanatory diagram of a multi-cavity substrate used in manufacturing the semiconductor device of FIG.

4 is a wiring explanatory diagram of an outer peripheral wiring pattern in the multi-cavity substrate of FIG. 3;

FIG. 5 is an explanatory diagram of a manufacturing process in the semiconductor device of FIG.

FIG. 6 is an explanatory diagram of the manufacturing process of the semiconductor device, following FIG. 5;

FIG. 7 is an explanatory diagram of the manufacturing process of the semiconductor device, following FIG. 6;

FIG. 8 is an explanatory diagram of the manufacturing process of the semiconductor device, following FIG. 7;

FIG. 9 is an explanatory diagram of the manufacturing process of the semiconductor device, following FIG. 8;

10 is a flowchart of a manufacturing process in the semiconductor device of FIG.

FIG. 11 is an explanatory diagram showing an example of cutting out a device area according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

FIG. 13 is a sectional view showing an example of a semiconductor device according to another embodiment of the present invention.

FIG. 14 is a sectional view showing another example of a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

1~1b semiconductor device 2 printed circuit board 2a bonding electrodes 2b periphery wiring pattern (common wiring pattern) 2b ₁ ~2b ₁₂ outer peripheral wiring pattern (common wiring pattern) 2c wiring pattern 2d through hole 2e ₁ ~2e ₁₂ bonding electrodes (bonding common Electrode) 2f Wiring 3 Semiconductor chip 3a Electrode (front surface electrode) 4 Solder bump 5 Bonding wire (connecting member) 6 Sealing resin 7 Multi-cavity substrate 7a Device regions 7a _{1 to} 7a ₄ Device region 7b Dicing line 8 Batch molding part

Claims (3)

[Claims] 1. A method of manufacturing a resin-encapsulated semiconductor device, comprising: a bonding common electrode having a plurality of device regions, to which a common signal is input; and a common wiring for commonly connecting the bonding common electrode. A step of preparing a printed wiring board on which a pattern and a bonding electrode to which an independent signal other than the common signal is input are formed; a step of mounting a semiconductor chip in the device region; and a surface electrode of the semiconductor chip and this Corresponding to the step of connecting the bonding common electrode of the printed wiring board and the bonding electrode with a connecting member, and collectively covering a plurality of device regions on the printed wiring board with a mold resin to seal the semiconductor chip with a resin. Together with the process of forming a collective sealing part, it is optional along the dicing line The method of manufacturing a semiconductor device, characterized in that by dividing the printed circuit board and the block molding portion for each of the device region singulated, and a step of forming individual sealed portion. 2. A method of manufacturing a resin-encapsulated semiconductor device, comprising a bonding common electrode having a plurality of device regions, to which an address signal is input, and a common wiring for commonly connecting the bonding common electrode. A step of preparing a printed wiring board on which a pattern and a bonding electrode to which an independent signal other than the address signal is input are formed; a step of mounting a semiconductor chip in the device region; A step of connecting the bonding electrodes of the printed wiring board and the bonding common electrodes corresponding to the above with a connecting member, and collectively covering a plurality of device regions on the printed wiring board with a mold resin to seal the semiconductor chip with a resin. Together with the process of forming the collective sealing part and the dicing line. Said printed wiring board and said to divide the block molding unit singulation method of manufacturing a semiconductor device characterized by a step of forming individual sealed portion each any of the device region Te. 3. A method of manufacturing a resin-encapsulated semiconductor device, comprising: a bonding common electrode having a plurality of device regions, to which an address signal is input, and bonding to which an independent signal other than the address signal is input. A step of preparing a printed wiring board in which electrodes and electrodes are respectively formed in the device region, and a common wiring pattern for commonly connecting the bonding common electrodes is formed in the peripheral portion of the dicing line; and a semiconductor chip in the device region. Mounting a surface electrode of the semiconductor chip and a bonding electrode corresponding to the surface electrode of the semiconductor chip, and a bonding common electrode by a connecting member, and molding a plurality of device regions in the printed wiring board. Cover with the resin all at once A step of forming an encapsulation part together with an oil encapsulation, and dividing the printed wiring board and the encapsulation part into individual pieces along the dicing line into individual device areas, and individually encapsulating the parts. And a step of forming a portion.