JP2005294604A - Submount and its manufacturing method - Google Patents

Submount and its manufacturing method Download PDF

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Publication number
JP2005294604A
JP2005294604A JP2004108640A JP2004108640A JP2005294604A JP 2005294604 A JP2005294604 A JP 2005294604A JP 2004108640 A JP2004108640 A JP 2004108640A JP 2004108640 A JP2004108640 A JP 2004108640A JP 2005294604 A JP2005294604 A JP 2005294604A
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solder
metallized layer
substrate
layer
submount
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JP4825403B2 (en
Inventor
Naoki Matsushima
直樹 松嶋
Kazuhiro Hirose
一弘 廣瀬
Masatoshi Seki
正俊 関
Hideaki Takemori
英昭 竹盛
Toshiaki Koizumi
俊晃 小泉
Takeshi Fujinaga
猛 藤永
Shohei Hata
昌平 秦
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Hitachi Ltd
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Hitachi Ltd
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Priority to PCT/JP2005/003278 priority patent/WO2005098931A1/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2081—Compound repelling a metal, e.g. solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process

Abstract

<P>PROBLEM TO BE SOLVED: To provide a submount which can control wet spread of Sn-Zn based solder formed on the outermost layer without arranging conventional solder resist composed of resin, Pt, etc. <P>SOLUTION: An Au metallized layer is formed to a circuit board composed of SiC, Al<SB>2</SB>O<SB>3</SB>, AlN, etc., Sn-Zn based solder is vapor-deposited on the upper layer of the Au metallized layer, and alloy whose principal component is Au and Sn which function as resist of the Sn-Zn based solder is formed on periphery of the Sn-Zn based solder. For the other way, sputtering is used instead of depositing, and alloy whose principal component is Au and Sn functioning as resist of the Sn-Zn based solder is formed on periphery of the Sn-Zn based solder. At this time, Zn just below the Sn-Zn based solder is made at most 38 wt.% to sum with Au just below the Sn-Zn based solder. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、回路基板の一種であるサブマウントとその製造方法に関する。   The present invention relates to a submount that is a type of circuit board and a method of manufacturing the same.

回路基板の一種にサブマウントと呼ばれる基板があり、主な用途としては、高い放熱性が要求される光ピックアップや光モジュールといった光関係製品におけるレーザダイオードの搭載がある。   One type of circuit board is a substrate called a submount, and its main application is mounting a laser diode in an optical product such as an optical pickup or an optical module that requires high heat dissipation.

このサブマウント上に電子部品を搭載する方法としては、はんだによる接合が最も一般的であり、はんだ材料にはAｕ-ＳｎやPb-Ｓｎが知られている。また、Pb-Ｓｎはんだに代わるPbフリーはんだ材料の一つとしては、Ｓｎ−Ｚｎ系はんだがあることが知られている。   As a method for mounting an electronic component on this submount, joining by solder is the most common, and Au—Sn and Pb—Sn are known as solder materials. As one of Pb-free solder materials replacing Pb—Sn solder, it is known that there is Sn—Zn solder.

特許文献１には、金めっきの側面をソルダーレジストで囲み、金めっき上にＳｎ−Ｚｎ系はんだをボールで供給することが記載されている。   Patent Document 1 describes that a side surface of gold plating is surrounded by a solder resist, and Sn—Zn-based solder is supplied by balls on the gold plating.

特開２００１−１５６２０７号公報JP 2001-156207 A

仮に、特許文献１のメタライズ層とはんだの構造を採用しようとすると、はんだのぬれ広がりを制御するために、Ａｕの上に樹脂やＰｔのソルダーレジストを形成するか、Ａｕを除去してＰｔを露出させる必要がある。   If the metallized layer and solder structure of Patent Document 1 are to be adopted, in order to control the wetting spread of the solder, a resin or Pt solder resist is formed on Au, or Au is removed to remove Pt. Need to be exposed.

そのため、はんだのぬれ広がりを制御するための製造プロセスが別途必要であった。   Therefore, a separate manufacturing process for controlling the wetting spread of the solder is required.

本願に含まれる一部の発明の目的は、簡単な製造プロセスで搭載したＳｎ−Ｚｎ系はんだのリフロー時におけるぬれ広がりを制御できるサブマウントと、その製造方法を提供することにある。   An object of some of the inventions included in the present application is to provide a submount capable of controlling the wetting spread during reflow of a Sn—Zn-based solder mounted by a simple manufacturing process, and a manufacturing method thereof.

また、従来のリフロー工程ではんだと基板とを固定するようにした場合、はんだとメライズ間の接合強度が弱かった。   Further, when the solder and the substrate are fixed in the conventional reflow process, the bonding strength between the solder and merise is weak.

つまり、本願に含まれる一部の発明の目的は、Ｓｎ−Ｚｎ系はんだをメタライズ上に搭載した基板のメタライズとはんだとの界面の接合強度を向上させることにある。   That is, an object of some inventions included in the present application is to improve the bonding strength of the interface between the metallization and the solder of the substrate on which the Sn—Zn solder is mounted on the metallization.

本願は、上記課題を解決するる手段を複数備えているが、代表的なものは次の通りである。   The present application includes a plurality of means for solving the above-mentioned problems, but typical ones are as follows.

＜代表例１＞
代表例１は、基板と、基板上に形成されたメタライズ層と、該メタライズ層上に形成されたＳｎ−Ｚｎ系はんだとを備え、前記メタライズ層のＳｎ−Ｚｎ系はんだ直下の領域に隣接した外側領域の表面にAｕ−Ｚｎ系合金を備えたサブマウントである。 <Representative example 1>
The representative example 1 includes a substrate, a metallized layer formed on the substrate, and a Sn—Zn solder formed on the metallized layer, and is adjacent to a region directly below the Sn—Zn solder of the metallized layer. The submount includes an Au—Zn alloy on the surface of the outer region.

Aｕ−Ｚｎ系合金は、融点が非常に高くはんだ溶融時に溶解することはなく、またはんだが濡れ広がることがないという性質を備えている。   The Au-Zn alloy has a property that it has a very high melting point and does not melt when the solder is melted, or does not spread wet.

そこで、この性質を利用し、Ｓｎ−Ｚｎ系はんだ直下の領域に隣接した領域にAｕ−Ｚｎ系合金を露出した状態で存在させることにより、はんだ溶融時のはんだの過剰な濡れ広がりを防止するはんだダム、つまり、広義のソルダレジスト（はんだをぬれ広がりにくくするもの）として機能させることができるようになる。   Therefore, by utilizing this property, the Au—Zn alloy is exposed in a region adjacent to the region directly under the Sn—Zn solder, thereby preventing excessive wetting and spreading of the solder at the time of melting the solder. It becomes possible to function as a dam, that is, a solder resist in a broad sense (which makes it difficult for the solder to spread).

＜代表例１の変形例＞
代表例１の変形例は、メタライズ層のＳｎ−Ｚｎ系はんだ直下の領域もAｕ−Ｚｎ系合金を備えているサブマウントである。 <Modification of representative example 1>
A modification of the representative example 1 is a submount in which the region immediately below the Sn—Zn-based solder of the metallized layer is also provided with an Au—Zn-based alloy.

この場合、リフロー時に基板上のメタライズ層のＡｕとＳｎ−Ｚｎ系はんだのＺｎとで反応する量がほとんどないので、リフロー中の溶融特性の変動が少ない。また、そもそも、メタライズ層のＳｎ−Ｚｎ系はんだ直下の領域が蒸着又はスパッタによるAｕ−Ｚｎ系合金で構成されているので、リフローにより構成される接合構造よりも接合強度も高い。   In this case, since there is almost no amount of reaction between Au in the metallized layer on the substrate and Zn in the Sn—Zn-based solder during reflow, there is little variation in melting characteristics during reflow. In the first place, since the region immediately below the Sn—Zn-based solder of the metallized layer is composed of an Au—Zn-based alloy by vapor deposition or sputtering, the bonding strength is higher than the bonding structure configured by reflow.

ペーストやペレットによりはんだを供給した場合、リフロー時に形成されるＡｕ−Ｚｎ化合物の影響ではんだ濡れ阻害が発生したり、Ａｕ−Ｚｎ化合物がＡｕ−Ｓｎ化合物などの他部材と接合が不充分であったりすることで、基板とはんだの接合強度が低い場合があった。   When solder is supplied as a paste or pellet, solder wetting inhibition occurs due to the influence of the Au—Zn compound formed during reflow, or the Au—Zn compound is insufficiently bonded to other members such as an Au—Sn compound. In some cases, the bonding strength between the substrate and the solder is low.

しかし、代表例１の変形例のように、蒸着やスパッタによりＡｎ−Ｚｎを成膜すると、分子に与えるエネルギーがリフローよりも高いため、分子間の接合強度が高くすることができ、せん断強度を高くできている。   However, when an An-Zn film is formed by vapor deposition or sputtering as in the modified example of the representative example 1, the energy given to the molecules is higher than the reflow, so that the bonding strength between the molecules can be increased and the shear strength can be increased. It is high.

＜代表例２＞
代表例２は、基板上にAｕを含むメタライズ層を形成する工程と、メタライズ層のうちのＳｎ及びＺｎが成膜された領域におけるＡｕとＺｎの化合物におけるＺｎの組成比がγ相以上の組成比となるように、該Aｕの上にＳｎ及びＺｎを蒸着又はスパッタで成膜する工程と、を備えたサブマウントの製造方法である。 <Representative example 2>
The representative example 2 is a composition in which the composition ratio of Zn in the compound of Au and Zn in the region where Sn and Zn are formed in the metallized layer is higher than the γ phase in the step of forming a metallized layer containing Au on the substrate. And a step of forming a film of Sn and Zn on the Au by vapor deposition or sputtering so as to achieve a ratio.

＜代表例３＞
代表例３は、基板上にAｕを含むメタライズ層を形成する工程と、成膜されるＳｎ−Ｚｎ系はんだのＺｎとＳｎ−Ｚｎ系はんだを成膜する領域におけるメタライズ層のＡｕとの和に対する該Ｚｎの組成比が３８重量％以下となる量のＺｎを含ませたＳｎ−Ｚｎ系はんだを蒸着又はスパッタで成膜する工程と、を備えたサブマウントの製造方法である。 <Representative example 3>
The representative example 3 corresponds to the step of forming a metallized layer containing Au on the substrate and the sum of Zn of the Sn—Zn-based solder to be formed and Au of the metalized layer in the region where the Sn—Zn-based solder is formed. And a step of depositing Sn—Zn-based solder containing Zn in an amount such that the composition ratio of Zn is 38 wt% or less by vapor deposition or sputtering.

代表例２及び３に共通のことであるが、Ｓｎ−Ｚｎ系はんだに含まれるＺｎは活性が高く、蒸着又はスパッタで成膜することでＺｎに非常に高いエネルギーが加わると、メタライズのAｕと反応して接合強度の高いAｕ−Ｚｎ系合金が形成される。これは上記手法にて成膜するＳｎ−Ｚｎ系薄膜はんだに固有の現象で、はんだペーストやペレットを形成しただけでは発生しないものである。   As is common to the representative examples 2 and 3, Zn contained in the Sn—Zn-based solder has high activity, and when a very high energy is applied to Zn by vapor deposition or sputtering, metallization Au and By reacting, an Au—Zn alloy having high bonding strength is formed. This is a phenomenon unique to Sn—Zn-based thin film solders formed by the above method, and does not occur only by forming solder paste or pellets.

また、Ｓｎ−Ｚｎ系はんだ中にＺｎを残すことができるので、リフロー時に基板のメタライズ層を構成するＡｕとの反応による融点の変動を抑制できる。   In addition, since Zn can be left in the Sn—Zn-based solder, fluctuations in the melting point due to reaction with Au constituting the metallized layer of the substrate can be suppressed during reflow.

また、Ｓｎ−Ｚｎ系はんだパターンからメタライズ層のＡｕをはみ出させるようにして、代表例２及び３を実施すれば、図５の結果や図４の状態図から、はみ出したＡｕにＡｕ−Ｚｎ系化合物が形成され、代表例１の効果を得ることができることがわかる。   Further, if the representative examples 2 and 3 are carried out so that Au of the metallized layer protrudes from the Sn—Zn solder pattern, the Au—Zn alloy is extracted from the protruding Au from the results of FIG. 5 and the state diagram of FIG. It turns out that a compound is formed and the effect of the representative example 1 can be acquired.

従って、従来よりも少ないプロセスで広義のソルダレジストを製造できる。   Therefore, a solder resist in a broad sense can be manufactured with fewer processes than before.

＜代表例４＞
代表例４は、基板と、基板上に形成されたメタライズと、該メタライズ上に形成されたＳｎ−Ｚｎ系はんだとを有し、該メタライズ層上にＳｎ−Ｚｎ系はんだを蒸着することにより生じたAｕ−Ｚｎ系合金により該基板にＳｎ−Ｚｎ系はんだが固定されているサブマウントである。 <Representative example 4>
The representative example 4 has a substrate, a metallization formed on the substrate, and a Sn—Zn solder formed on the metallization, and is produced by depositing a Sn—Zn solder on the metallization layer. In addition, this is a submount in which Sn—Zn solder is fixed to the substrate by an Au—Zn alloy.

代表例４は、リフロー時に基板上のメタライズ層のＡｕとＳｎ−Ｚｎ系はんだのＺｎとで反応する量がほとんどないので、リフロー中の融点の変動が少ない。また、そもそも、メタライズ層のＳｎ−Ｚｎ系はんだ直下の領域が蒸着又はスパッタによるAｕ−Ｚｎ系合金で構成されているので、リフローにより構成される接合構造よりも接合強度も高い。   In the representative example 4, there is almost no amount of reaction between Au of the metallized layer on the substrate and Zn of the Sn—Zn-based solder at the time of reflow, so that the melting point fluctuation during reflow is small. In the first place, since the region immediately below the Sn—Zn-based solder of the metallized layer is composed of an Au—Zn-based alloy by vapor deposition or sputtering, the bonding strength is higher than the bonding structure configured by reflow.

Ｓｎ−Ｚｎ系はんだのぬれ性のわるさ及びリフローによって生成されたＡｕ−Ｓｎ系化合物とＡｕ−Ｚｎ系化合物の影響で、リフローによるＳｎ−Ｚｎ系はんだの基板への接合は接合強度が低かった。しかし、代表例１の変形例のように、蒸着やスパッタによりＡｎ−Ｚｎを成膜すると、分子に与えるエネルギーがリフローよりも高いため、分子間の接合強度が高くすることができ、せん断強度を高くできている。 また、Ｓｎ−Ｚｎ系はんだ中にＺｎを残すことができるので、リフロー時に基板のメタライズ層を構成するＡｕとの反応による融点の変動を抑制できる。   Due to the wettability of Sn—Zn solder and the influence of Au—Sn compound and Au—Zn compound produced by reflow, the bonding strength of Sn—Zn solder to the substrate by reflow was low. . However, when an An-Zn film is formed by vapor deposition or sputtering as in the modified example of the representative example 1, the energy given to the molecules is higher than the reflow, so that the bonding strength between the molecules can be increased and the shear strength can be increased. It is high. In addition, since Zn can be left in the Sn—Zn-based solder, fluctuations in the melting point due to reaction with Au constituting the metallized layer of the substrate can be suppressed during reflow.

本発明によれば、サブマウントに搭載したＳｎ−Ｚｎ系はんだの濡れ広がりを制御する構造を実現できる。   According to the present invention, it is possible to realize a structure that controls the wetting and spreading of the Sn—Zn-based solder mounted on the submount.

以下、本発明を実施する複数の形態を説明する。   Hereinafter, a plurality of modes for carrying out the present invention will be described.

実施例１を図１の製造工程図を用いて説明する。   Example 1 will be described with reference to the manufacturing process diagram of FIG.

図１(a)〜(e)は断面図、(a')〜(e')は上面図を表す。   1A to 1E are sectional views, and FIGS. 1A to 1E are top views.

まず、基板１として、ＳｉＣ製基板を用い、基板１の表面上にメタライズ層２を成膜した(a)(a')。層構成は基板１側からTi層２１、Pt層２２、Aｕ層２３とし、蒸着により積層した。最上層のAｕの膜厚は、この後に成膜するはんだパターンのＺｎ量を考慮して0.05mmとした。   First, a SiC substrate was used as the substrate 1, and a metallized layer 2 was formed on the surface of the substrate 1 (a) (a '). The layer structure was a Ti layer 21, a Pt layer 22, and an Au layer 23 from the substrate 1 side and laminated by vapor deposition. The film thickness of the uppermost Au layer was set to 0.05 mm in consideration of the Zn amount of the solder pattern to be formed later.

次に、メタライズ層パターン２００をイオンミリングを用いて形成する(b)(b')。   Next, the metallized layer pattern 200 is formed by ion milling (b) (b ′).

次に、メタライズ層パターン２００の上層にＳｎ−Ｚｎはんだパターン３００をリフトオフ法により形成した。まず、はんだパターンを配置しない部分にレジストパターン５を形成する(c)(c')。レジストパターン５の存在しない部分は、Ｓｎ−Ｚｎはんだパターン３００が形成されることになるが、このとき、Ａｕメタライズ層がＳｎ−Ｚｎはんだパターン３００よりも大きく、かつ、その外周領域がはみ出して露出する形状となるようにレジストパターン５を形成した。   Next, an Sn—Zn solder pattern 300 was formed on the metallized layer pattern 200 by a lift-off method. First, a resist pattern 5 is formed in a portion where a solder pattern is not disposed (c) (c ′). In the portion where the resist pattern 5 does not exist, the Sn—Zn solder pattern 300 is formed. At this time, the Au metallized layer is larger than the Sn—Zn solder pattern 300, and its outer peripheral region protrudes and is exposed. A resist pattern 5 was formed so as to have a shape to be formed.

次に、Ｓｎ−Ｚｎはんだパターン３００を成膜する。本実施例では、はんだ組成としてＳｎ-9wt%Ｚｎを適用し、膜厚３mmで加熱蒸着により形成した。   Next, a Sn—Zn solder pattern 300 is formed. In this example, Sn-9 wt% Zn was applied as the solder composition, and the film was formed by heat evaporation with a film thickness of 3 mm.

この成膜構成ではんだ蒸着した後、サブマウントはＳｎ−Ｚｎはんだパターン３００のパターン端部から２０μｍ離れた位置までの外周領域と、レジストパターン５の端部近傍直下のAｕメタライズが存在する領域に、Aｕ−Ｚｎ合金４０１が形成されていた。これは、活性なＺｎが、はんだパターン直下のAｕのみならずパターン端部外周のレジストパターン端部近傍のAｕメタライズと反応することで形成されたものである (d)(d')。また、その上層のはんだ３０１は、AｕとＺｎとの反応により蒸着時よりもＺｎ量の少ない組成比となっていた。この層構成の場合、はんだ直下に存在するAｕメタライズ層２０３のＺｎ量は、AｕとＳｎ−Ｚｎはんだ３に含まれるＺｎ量との和に対して６７wt%であった。   After solder deposition in this film formation configuration, the submount is located in the outer peripheral area from the pattern edge of the Sn—Zn solder pattern 300 to a position 20 μm away, and in the area where Au metallization immediately below the edge of the resist pattern 5 exists. An Au—Zn alloy 401 was formed. This is formed by reacting active Zn not only with Au just below the solder pattern but also with Au metallization in the vicinity of the resist pattern end on the outer periphery of the pattern end (d) (d ′). Moreover, the solder 301 of the upper layer had a composition ratio with a smaller amount of Zn than that during vapor deposition due to the reaction between Au and Zn. In the case of this layer configuration, the amount of Zn in the Au metallized layer 203 existing directly under the solder was 67 wt% with respect to the sum of Au and the amount of Zn contained in the Sn—Zn solder 3.

最後に、レジストパターン５をリフトオフ法で除去することで、所望の箇所にはんだパターン３０１を形成し、そのはんだパターン３０１の直下及びその外周にAｕ−Ｚｎ合金４０１を形成した電子回路が完成させた(e)(e')。   Finally, the resist pattern 5 is removed by a lift-off method, whereby a solder pattern 301 is formed at a desired location, and an electronic circuit in which an Au—Zn alloy 401 is formed directly under and around the solder pattern 301 is completed. (e) (e ').

次に、メタライズ層パターン２００におけるＳｎ−Ｚｎはんだパターン３００を形成した領域に含まれるＺｎと、Ｓｎ−Ｚｎはんだに含まれるＺｎとの組成比とAｕ−Ｚｎ合金４０１がどのくらいＳｎ−Ｚｎはんだパターン３００から離れた領域まで伸びているか（Ｓｎ−Ｚｎはんだパターン３００からの長さ）を実験した。その結果を図５に示す。   Next, how much the composition ratio of Zn contained in the region where the Sn—Zn solder pattern 300 is formed in the metallized layer pattern 200 and Zn contained in the Sn—Zn solder and how much the Au—Zn alloy 401 is Sn—Zn solder pattern 300. It was experimented whether it extended to the area | region away from (length from the Sn-Zn solder pattern 300). The result is shown in FIG.

実験データの記録項目は、メタライズ層であるＡｕの膜厚（μｍ）、Ｓｎ−Ｚｎはんだに占めるＺｎの組成比（重量％）、Ｓｎ−Ｚｎ系はんだの直下の領域に形成したＡｕとＳｎ−Ｚｎはんだに含まれるＺｎの和におけるＳｎ−Ｚｎはんだに含まれるＡｕとＺｎの組成比（重量％）、はみ出す長さ（μｍ）とし、６つのデータを取り、そのデータからグラフを作成した。   The recording items of the experimental data are the film thickness (μm) of Au as the metallized layer, the composition ratio (% by weight) of Zn in the Sn—Zn solder, Au and Sn— formed in the region immediately below the Sn—Zn solder. The composition ratio (wt%) of Au and Zn contained in the Sn—Zn solder in the sum of Zn contained in the Zn solder and the protruding length (μm) were taken, and six data were taken and a graph was created from the data.

このグラフにより、Ｚｎが３８重量％以上の場合に、Ｓｎ−Ｚｎ系はんだ直下の領域から外周に向けてＡｕ−Ｚｎ合金が形成されはじめ、はんだダムとして機能し、濡れ広がり防止の効果が生じている。また、Ａｕが３８重量％以上含まれ５８重量％未満含まれている場合、Ｓｎ−Ｚｎはんだ直下の領域から外周にむけて５μｍ以下の距離までの領域で形成され、Ｚｎが５８重量％以上含ま６２重量％以上含まれる場合、５μｍより大きく１０μｍ以下の距離までの領域に形成されるようになり、Ｚｎが６２重量％以上６７重量％以上含まれる場合、１０μｍより大きく２０μｍ以下の距離までの領域に形成されるようになり、Ｚｎが６７重量％以下の場合には、反応が安定し、２０μｍの距離までの領域に形成されるようになることがわかった。   According to this graph, when Zn is 38% by weight or more, an Au—Zn alloy starts to be formed from the region directly under the Sn—Zn-based solder toward the outer periphery, functions as a solder dam, and has the effect of preventing wetting and spreading. Yes. Further, when Au is contained in an amount of 38% by weight or more and less than 58% by weight, it is formed in a region up to a distance of 5 μm or less from the region directly under the Sn—Zn solder to the outer periphery, and Zn is contained by 58% by weight or more. When it is contained 62% by weight or more, it is formed in a region up to a distance of 5 μm or more and 10 μm or less. It was found that when Zn was 67% by weight or less, the reaction was stable and it was formed in a region up to a distance of 20 μm.

つまり、メタライズ層におけるＳｎ−Ｚｎはんだを形成した領域のＡｕと蒸着やスパッタにより成膜したＳｎ−Ｚｎはんだに含まれるＺｎとの和に対するそのＺｎの組成比が３８重量％以上であれば、メタライズ層におけるＳｎ−Ｚｎはんだを形成した領域のＡｕと反応しきれない量のＺｎが存在することなり、所定の融点（Ｓｎ−９wtＺｎであれば１９９℃）を保持でき、さらに、メタライズ層におけるＳｎ−Ｚｎはんだを形成した領域の外側にソルダレジストとして機能するＡｕ−Ｚｎ合金を形成できる。   That is, if the composition ratio of Zn to the sum of Au in the region where the Sn—Zn solder is formed in the metallization layer and Zn contained in the Sn—Zn solder formed by vapor deposition or sputtering is 38 wt% or more, the metallization is performed. In the layer, there is an amount of Zn that does not react with Au in the region where the Sn—Zn solder is formed, and a predetermined melting point (199 ° C. if Sn-9 wt Zn) can be maintained. An Au—Zn alloy functioning as a solder resist can be formed outside the region where the Zn solder is formed.

このことを、AｕとＺｎの２元系状態図から検討すると、Ｓｎ−Ｚｎはんだ直下の領域に形成されている合金はγ、γ２あるいはγ３、もしくはこれらの固溶体、又はこれらよりもＺｎの組成比が高ければよいことを意味していることが分かる。   Examining this from the binary phase diagram of Au and Zn, the alloy formed in the region directly under the Sn—Zn solder is γ, γ2 or γ3, or a solid solution thereof, or a composition ratio of Zn rather than these. It means that it means that it is better if is high.

本実施例では、成膜時のＳｎ−Ｚｎはんだの組成として、Ｓｎ−９wt%Ｚｎを適用したが、もちろんこれ以外でも構わない。例えば、成膜時のはんだをＺｎ過剰にし、下地Aｕメタライズ層とＺｎが反応してAｕとＺｎを主成分とする合金が形成された後にＳｎ−９wt%Ｚｎ組成となるように設定しても構わない。さらに、Ｓｎ−Ｚｎ−Ｂｉ等のＳｎとＺｎを主成分とする多元系はんだであっても構わない。   In this embodiment, Sn-9 wt% Zn is applied as the composition of the Sn—Zn solder at the time of film formation. For example, even if the solder during film formation is made to be Zn-excess and the base Au metallized layer reacts with Zn to form an alloy containing Au and Zn as main components, the Sn-9 wt% Zn composition is set. I do not care. Furthermore, it may be a multi-component solder mainly composed of Sn and Zn such as Sn—Zn—Bi.

なお、本実施例では、放熱性を重視してＳｉＣ製基板を用いたが、Ａｌ２Ｏ３製基板又はＡｌＮ製基板であっても構わない。   In this embodiment, the SiC substrate is used with emphasis on heat dissipation, but an Al2O3 substrate or an AlN substrate may be used.

なお、蒸着の代わりにスパッタでもよいが、本実施例では、蒸着を用いた。また、メタライズ層２００のAｕメタライズ層２０３よりも下の部分は、基板とはんだとの接続強度を確保すること、あるいはこれに加えて、搭載する電子回路素子と基板間の熱伝導性やメタライズの電気伝導性を確保することができれば上記以外の部材・層構成でも構わない。メタライズ層のパターンニング方法についてもメタライズの材料が対応可能であればウェットエッチング等他の方法でも構わない。   Although sputtering may be used instead of vapor deposition, vapor deposition is used in this embodiment. Further, the portion of the metallized layer 200 below the Au metallized layer 203 is to secure the connection strength between the substrate and the solder, or in addition to this, the thermal conductivity between the electronic circuit element to be mounted and the substrate and the metallized layer Any other member / layer structure may be used as long as electrical conductivity can be ensured. As for the patterning method of the metallized layer, other methods such as wet etching may be used as long as the metallized material can be used.

また、はんだの組成比は、Ｓｎ-9wt%Ｚｎ以外のものでもよく、またＳｎ−Ｚｎ系の多元系のはんだでも構わない。さらに、成膜方法に関しては、蒸着以外の、例えばスパッタ方式でも構わない。   The composition ratio of the solder may be other than Sn-9 wt% Zn, or may be Sn-Zn based multi-element solder. Further, regarding the film forming method, for example, a sputtering method other than vapor deposition may be used.

本実施例は、次の発明が含まれている。   The present embodiment includes the following inventions.

＜発明例１＞
発明例１は、基板と、基板上に形成されたメタライズ層と、該メタライズ層上に形成されたＳｎ−Ｚｎ系はんだとを備え、前記メタライズ層のＳｎ−Ｚｎ系はんだ直下の領域に隣接した外側領域の表面にAｕ−Ｚｎ系合金を備えているサブマウントである。 <Invention Example 1>
Invention Example 1 includes a substrate, a metallized layer formed on the substrate, and a Sn—Zn solder formed on the metallized layer, and is adjacent to a region directly below the Sn—Zn solder of the metallized layer. The submount includes an Au—Zn alloy on the surface of the outer region.

Aｕ−Ｚｎ系合金は、融点が非常に高くはんだ溶融時に溶解することはなく、またはんだが濡れ広がることがないという性質を備えている。   The Au-Zn alloy has a property that it has a very high melting point and does not melt when the solder is melted, or does not spread wet.

そこで、この性質を利用し、Ｓｎ−Ｚｎ系はんだ直下の領域に隣接した領域にAｕ−Ｚｎ系合金を露出した状態で存在させることにより、はんだ溶融時のはんだの過剰な濡れ広がりを防止するはんだダム、つまり、広義のソルダレジスト（はんだをぬれ広がりにくくするもの）として機能させることができるようになる。   Therefore, by utilizing this property, the Au—Zn alloy is exposed in a region adjacent to the region directly under the Sn—Zn solder, thereby preventing excessive wetting and spreading of the solder at the time of melting the solder. It becomes possible to function as a dam, that is, a solder resist in a broad sense (which makes it difficult for the solder to spread).

＜発明例１の変形例＞
発明例１の変形例は、メタライズ層のＳｎ−Ｚｎ系はんだ直下の領域もAｕ−Ｚｎ系合金を備えているサブマウントである。 <Modification of Invention Example 1>
A modification of Invention Example 1 is a submount in which the region immediately below the Sn—Zn-based solder of the metallized layer is also provided with an Au—Zn-based alloy.

この場合、リフロー時に基板上のメタライズ層のＡｕとＳｎ−Ｚｎ系はんだのＺｎとで反応する量がほとんどないので、リフロー中の融点の変動が少ない。また、そもそも、メタライズ層のＳｎ−Ｚｎ系はんだ直下の領域が蒸着又はスパッタによるAｕ−Ｚｎ系合金で構成されているので、リフローにより構成される接合構造よりも接合強度も高い。   In this case, since there is almost no amount of reaction between Au of the metallized layer on the substrate and Zn of the Sn—Zn-based solder during reflow, there is little variation in the melting point during reflow. In the first place, since the region immediately below the Sn—Zn-based solder of the metallized layer is composed of an Au—Zn-based alloy by vapor deposition or sputtering, the bonding strength is higher than the bonding structure configured by reflow.

Ｓｎ−Ｚｎ系はんだのぬれ性のわるさ及びリフローによって生成されたＡｕ−Ｓｎ系化合物とＡｕ−Ｚｎ系化合物の影響で、リフローによるＳｎ−Ｚｎ系はんだの基板への接合は接合強度が低かった。   Due to the wettability of Sn—Zn solder and the influence of Au—Sn compound and Au—Zn compound produced by reflow, the bonding strength of Sn—Zn solder to the substrate by reflow was low. .

ペーストやペレットによりはんだを供給した場合、リフロー時に形成されるＡｕ−Ｚｎ化合物の影響ではんだ濡れ阻害が発生したり、Ａｕ−Ｚｎ化合物がＡｕ−Ｓｎ化合物などの他部材と接合が不充分であったりすることで、基板とはんだの接合強度が低い場合があった。   When solder is supplied as a paste or pellet, solder wetting inhibition occurs due to the influence of the Au—Zn compound formed during reflow, or the Au—Zn compound is insufficiently bonded to other members such as an Au—Sn compound. In some cases, the bonding strength between the substrate and the solder is low.

しかし、発明例１の変形例のように、蒸着やスパッタによりＡｎ−Ｚｎを成膜すると、分子に与えるエネルギーがリフローよりも高いため、分子間の接合強度が高くすることができ、せん断強度を高くできている。   However, as in the modification of Invention Example 1, when an An-Zn film is formed by vapor deposition or sputtering, the energy given to the molecules is higher than the reflow, so that the bonding strength between the molecules can be increased and the shear strength can be increased. It is high.

＜発明例２＞
発明例２は、基板上にAｕを含むメタライズ層を形成する工程と、メタライズ層のうちのＳｎ及びＺｎが成膜された領域におけるＡｕとＺｎの化合物におけるＺｎの組成比がγ相以上の組成比となるように、該Aｕの上にＳｎ及びＺｎを蒸着又はスパッタで成膜する工程と、を備えたサブマウントの製造方法である。 <Invention Example 2>
Invention Example 2 is a composition in which the composition ratio of Zn in the Au and Zn compound in the region where Sn and Zn are formed in the metallized layer is higher than the γ phase in the step of forming the metallized layer containing Au on the substrate And a step of forming a film of Sn and Zn on the Au by vapor deposition or sputtering so as to achieve a ratio.

＜発明例３＞
発明例３は、基板上にAｕを含むメタライズ層を形成する工程と、成膜されるＳｎ−Ｚｎ系はんだのＺｎとＳｎ−Ｚｎ系はんだを成膜する領域におけるメタライズ層のＡｕとの和に対する該Ｚｎの組成比が３８重量％以下となる量のＺｎを含ませたＳｎ−Ｚｎ系はんだを蒸着又はスパッタで成膜する工程と、を備えたサブマウントの製造方法である。 <Invention Example 3>
Invention Example 3 corresponds to the step of forming a metallized layer containing Au on the substrate and the sum of Zn of the Sn—Zn-based solder to be formed and Au of the metallized layer in the region where the Sn—Zn-based solder is formed. And a step of depositing Sn—Zn-based solder containing Zn in an amount such that the composition ratio of Zn is 38 wt% or less by vapor deposition or sputtering.

発明例２及び３に共通のことであるが、Ｓｎ−Ｚｎ系はんだに含まれるＺｎは活性が高く、蒸着又はスパッタで成膜することでＺｎに非常に高いエネルギーが加わると、メタライズのAｕと反応して接合強度の高いAｕ−Ｚｎ系合金が形成される。これは上記手法にて成膜するＳｎ−Ｚｎ系薄膜はんだに固有の現象で、はんだペーストやペレットを形成しただけでは発生しないものである。   As is common to Invention Examples 2 and 3, Zn contained in the Sn—Zn-based solder has high activity, and when a very high energy is applied to Zn by vapor deposition or sputtering, metallization Au and By reacting, an Au—Zn alloy having high bonding strength is formed. This is a phenomenon unique to Sn—Zn-based thin film solders formed by the above method, and does not occur only by forming solder paste or pellets.

また、Ｓｎ−Ｚｎ系はんだ中にＺｎを残すことができるので、リフロー時に基板のメタライズ層を構成するＡｕとの反応による融点の変動を抑制できる。   In addition, since Zn can be left in the Sn—Zn-based solder, fluctuations in the melting point due to reaction with Au constituting the metallized layer of the substrate can be suppressed during reflow.

また、Ｓｎ−Ｚｎ系はんだパターンからメタライズ層のＡｕをはみ出させるようにして、発明例２及び３を実施すれば、図５の結果や図４の状態図から、はみ出したＡｕにＡｕ−Ｚｎ系化合物が形成され、発明例１の効果を得ることができることがわかる。   Further, when the invention examples 2 and 3 are carried out so that Au of the metallized layer protrudes from the Sn—Zn based solder pattern, the Au—Zn based on the protruding Au from the result of FIG. 5 and the state diagram of FIG. It turns out that a compound is formed and the effect of invention example 1 can be acquired.

従って、従来よりも少ないプロセスで広義のソルダレジストを製造できる。   Therefore, a solder resist in a broad sense can be manufactured with fewer processes than before.

＜発明例４＞
発明例４は、基板と、基板上に形成されたメタライズと、該メタライズ上に形成されたＳｎ−Ｚｎ系はんだとを有し、該メタライズ層上にＳｎ−Ｚｎ系はんだを蒸着することにより生じたAｕ−Ｚｎ系合金により該基板にＳｎ−Ｚｎ系はんだが固定されているサブマウントである。 <Invention Example 4>
Invention Example 4 has a substrate, a metallization formed on the substrate, and a Sn—Zn solder formed on the metallization, and is produced by depositing the Sn—Zn solder on the metallization layer. In addition, this is a submount in which Sn—Zn solder is fixed to the substrate by an Au—Zn alloy.

発明例４は、リフロー時に基板上のメタライズ層のＡｕとＳｎ−Ｚｎ系はんだのＺｎとで反応する量がほとんどないので、リフロー中の融点の変動が少ない。また、そもそも、メタライズ層のＳｎ−Ｚｎ系はんだ直下の領域が蒸着又はスパッタによるAｕ−Ｚｎ系合金で構成されているので、リフローにより構成される接合構造よりも接合強度も高い。   In Invention Example 4, there is almost no amount of reaction between Au in the metallized layer on the substrate and Zn in the Sn—Zn-based solder during reflow, and therefore, there is little variation in melting point during reflow. In the first place, since the region immediately below the Sn—Zn-based solder of the metallized layer is composed of an Au—Zn-based alloy by vapor deposition or sputtering, the bonding strength is higher than the bonding structure configured by reflow.

Ｓｎ−Ｚｎ系はんだのぬれ性のわるさ及びリフローによって生成されたＡｕ−Ｓｎ系化合物とＡｕ−Ｚｎ系化合物の影響で、リフローによるＳｎ−Ｚｎ系はんだの基板への接合は接合強度が低かった。しかし、発明例１の変形例のように、蒸着やスパッタによりＡｎ−Ｚｎを成膜すると、分子に与えるエネルギーがリフローよりも高いため、分子間の接合強度が高くすることができ、せん断強度を高くできている。 また、Ｓｎ−Ｚｎ系はんだ中にＺｎを残すことができるので、リフロー時に基板のメタライズ層を構成するＡｕとの反応による融点の変動を抑制できる。   Due to the wettability of Sn—Zn solder and the influence of Au—Sn compound and Au—Zn compound produced by reflow, the bonding strength of Sn—Zn solder to the substrate by reflow was low. . However, as in the modification of Invention Example 1, when an An-Zn film is formed by vapor deposition or sputtering, the energy given to the molecules is higher than the reflow, so that the bonding strength between the molecules can be increased and the shear strength can be increased. It is high. In addition, since Zn can be left in the Sn—Zn-based solder, fluctuations in the melting point due to reaction with Au constituting the metallized layer of the substrate can be suppressed during reflow.

次に、実施例２について、図２の製造工程図を用いて説明する。   Next, Example 2 will be described using the manufacturing process diagram of FIG.

図２(a)は、実施例２の方法に従い形成した電子部品の断面図である。   FIG. 2A is a cross-sectional view of an electronic component formed according to the method of the second embodiment.

図１と大きく異なるのは、Aｕワイヤを設置するためのAｕメタライズを最上層とするボンディングパッド６が具備されている点である。   A significant difference from FIG. 1 is that a bonding pad 6 having an Au metallization as an uppermost layer for installing an Au wire is provided.

パッド６はメタライズ層パターン２００と同一工程で形成しており、図に示されるように両者はメタライズが途切れることなく接続されている。これは、パッド６が、基板１に搭載される電子部品に電流等を印加する目的を持っているためである。   The pad 6 is formed in the same process as that of the metallized layer pattern 200, and the two are connected without interruption of the metallization as shown in the figure. This is because the pad 6 has a purpose of applying a current or the like to the electronic component mounted on the substrate 1.

なお、パッド６は、Aｕワイヤ設置用パッド以外の、例えば別の電子回路素子をはんだ搭載するためのメタライズであっても構わない。   The pad 6 may be a metallization for mounting, for example, another electronic circuit element other than the Au wire installation pad.

この電子部品に、半導体レーザ等の電子回路素子７を配置してはんだの融点以上の温度に加熱すると、はんだパターン３０１は溶融し電子回路素子側のメタライズ７０１とが拡散し合い電子回路素子７が接合される(b)。このとき、はんだパターン外周にAｕとＺｎを主成分とする合金４０１が形成されていることにより、図２のように濡れ広がらず、ボンディングパッド６にはんだが及ぶことはない。一方、従来技術による電子回路で図３と同じ構造を形成し、電子回路素子７を接合すると、溶融したはんだ８は基板側のメタライズ７０２に濡れ広がりパッド６にまではんだが流出する可能性が高い。パッド６とはんだパターン直下のメタライズとの間にはんだが濡れない部材を用いてパターンを形成すれば、濡れ広がりは防げるが、１層分の薄膜形成工程が加わることになり、電子部品の組立コストの上昇を招く。すなわち、本発明は、組立コストの上昇を招くことなしに、はんだの過剰な濡れ広がりによる不良を抑止することができる。   When the electronic circuit element 7 such as a semiconductor laser is disposed on the electronic component and heated to a temperature equal to or higher than the melting point of the solder, the solder pattern 301 is melted and diffused with the metallized 701 on the electronic circuit element side. Bonded (b). At this time, since the alloy 401 mainly composed of Au and Zn is formed on the outer periphery of the solder pattern, the alloy does not spread as shown in FIG. 2, and the solder does not reach the bonding pad 6. On the other hand, when the same structure as that of FIG. 3 is formed by the electronic circuit according to the prior art and the electronic circuit element 7 is joined, the molten solder 8 wets the metallization 702 on the substrate side and the solder is likely to flow out to the pad 6. . If a pattern is formed using a member that does not wet the solder between the pad 6 and the metallization directly under the solder pattern, wetting spread can be prevented, but a thin film forming process for one layer is added, and the assembly cost of the electronic component is increased. Invite the rise. That is, the present invention can suppress defects due to excessive wetting and spreading of solder without causing an increase in assembly cost.

実施例１の製造工程図である。2 is a manufacturing process diagram of Example 1. FIG. 実施例２の製造工程図である。6 is a production process diagram of Example 2. FIG. 従来技術による電子部品を示す模式図である。It is a schematic diagram which shows the electronic component by a prior art. AｕとＺｎの二元系平衡状態図である。It is a binary system equilibrium state diagram of Au and Zn. ＳｎとＺｎを含むはんだからの距離とＺｎの含有比率の関係を示す試験データである。It is test data which shows the relationship between the distance from the solder containing Sn and Zn, and the content rate of Zn.

符号の説明Explanation of symbols

１ 基板
２ メタライズ層
５ レジストパターン
６ Aｕワイヤ設置用ボンディングパッド
７ 電子回路素子（半導体レーザ）
８ はんだ
２１ Ti層
２２ Pt層
２３ Aｕ層
２００ メタライズ層パターン
２０１ Ti層パターン
２０２ Pt層パターン
２０３ Aｕ層パターン
３０１ ＳｎとＺｎを主成分とするはんだパターン
４００、４０１ AｕとＺｎを主成分とする合金パターン
７０１、７０２ メタライズ DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Metallization layer 5 Resist pattern 6 Bonding pad for Au wire installation 7 Electronic circuit element (semiconductor laser)
8 Solder 21 Ti layer 22 Pt layer 23 Au layer 200 Metallized layer pattern 201 Ti layer pattern 202 Pt layer pattern 203 Au layer pattern 301 Solder pattern 400 containing Sn and Zn as main components, alloy containing 401 Au and Zn as main components Pattern 701, 702 Metallization

Claims (9)

基板と、基板上に形成されたメタライズ層と、該メタライズ層上に形成されたＳｎ−Ｚｎ系はんだとを備え、
前記メタライズ層のうちＳｎ−Ｚｎ系はんだ直下の領域に隣接した領域は、その表面にAｕ−Ｚｎ系合金を備えているサブマウント。 A substrate, a metallized layer formed on the substrate, and a Sn-Zn based solder formed on the metallized layer,
In the metallized layer, a region adjacent to a region directly below the Sn—Zn solder is a submount having an Au—Zn alloy on its surface. 請求項１において、
前記Ｓｎ−Ｚｎ系はんだは蒸着又はスパッタにより形成されたはんだであり、
前記メタライズ層のうち前記Ｓｎ−Ｚｎ系はんだの直下領域が前記蒸着又はスパッタにより形成されたAｕ−Ｚｎ系合金で構成されていることを特徴とするサブマウント。 In claim 1,
The Sn—Zn solder is a solder formed by vapor deposition or sputtering,
A submount, wherein a region immediately below the Sn—Zn solder in the metallized layer is made of an Au—Zn alloy formed by vapor deposition or sputtering. 請求項１において、
前記Ｓｎ−Ｚｎ系はんだは蒸着又はスパッタにより形成されたものであることを特徴とするサブマウント。 In claim 1,
The submount, wherein the Sn-Zn solder is formed by vapor deposition or sputtering. 請求項２又は３において、
成膜されるＳｎ−Ｚｎ系はんだ中のＺｎと、Ｓｎ−Ｚｎ系はんだを成膜する領域におけるメタライズ層のＡｕとの和に対する該Ｚｎの組成比が３８重量％以上であることを特徴とするサブマウント。 In claim 2 or 3,
The composition ratio of Zn with respect to the sum of Zn in the Sn—Zn-based solder to be deposited and Au of the metallized layer in the region where the Sn—Zn-based solder is deposited is 38 wt% or more. Submount. 基板上にAｕを含むメタライズ層を形成する工程と、
成膜されるＳｎ−Ｚｎ系はんだのＺｎとＳｎ−Ｚｎ系はんだを成膜する領域におけるメタライズ層のＡｕとの和に対する該Ｚｎの組成比が３８重量％以上となる量のＺｎを含ませたＳｎ−Ｚｎ系はんだを蒸着又はスパッタで成膜する工程と、を備えたサブマウントの製造方法。 Forming a metallized layer containing Au on the substrate;
Zn was included in such an amount that the composition ratio of Zn to the sum of Zn of the Sn—Zn-based solder to be deposited and Au of the metallized layer in the region where the Sn—Zn-based solder was deposited was 38 wt% or more. And a step of forming a film of Sn—Zn solder by vapor deposition or sputtering. 基板上にAｕを含むメタライズ層を形成する工程と、
メタライズ層のうちのＳｎ及びＺｎが成膜された領域におけるＡｕとＺｎの化合物におけるＺｎの組成比がγ相以下の組成比となるように、該Aｕの上にＳｎ及びＺｎを蒸着又はスパッタで成膜する工程と、を備えたサブマウントの製造方法。 Forming a metallized layer containing Au on the substrate;
The Sn and Zn are deposited or sputtered on the Au so that the composition ratio of Zn in the compound of Au and Zn in the metallized layer where Sn and Zn are deposited is equal to or less than the γ phase. And a film forming method. 請求項５又は６において、
マスクを用いてレジストパターンを形成し、
前記Ｚｎ及びＳｎを成膜し、
該レジストパターンを除去することによりはんだパターンを形成することを特徴とするサブマウントの製造方法。 In claim 5 or 6,
Use a mask to form a resist pattern,
Depositing Zn and Sn;
A method of manufacturing a submount, comprising forming a solder pattern by removing the resist pattern. 請求項５又は６において、
前記ＺｎとＳｎを、ＳｎにＺｎ粒子を含有させた状態で成膜するか、Ｓｎ層とＺｎ層もしくはＳｎとＺｎの混合物層とを積層した積層体として成膜することを特徴とするサブマウントの製造方法。 In claim 5 or 6,
The submount characterized in that the Zn and Sn are formed in a state where Zn particles are contained in Sn, or are formed as a laminated body in which a Sn layer and a Zn layer or a mixture layer of Sn and Zn are laminated. Manufacturing method. 基板と、基板上に形成されたメタライズと、該メタライズ上に形成されたＳｎ−Ｚｎ系はんだとを有し、
該メタライズ層上にＳｎ−Ｚｎ系はんだを蒸着することにより生じたAｕ−Ｚｎ系合金により該基板にＳｎ−Ｚｎ系はんだが固定されていることを特徴とするサブマウント。
A substrate, a metallization formed on the substrate, and a Sn-Zn solder formed on the metallization,
A submount characterized in that an Sn-Zn-based solder is fixed to the substrate by an Au-Zn-based alloy produced by depositing an Sn-Zn-based solder on the metallized layer.
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