JP2005286161A - 形状修復方法及び装置、並びにそれらを用いた半導体デバイス製造方法 - Google Patents

形状修復方法及び装置、並びにそれらを用いた半導体デバイス製造方法 Download PDF

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Publication number
JP2005286161A
JP2005286161A JP2004099127A JP2004099127A JP2005286161A JP 2005286161 A JP2005286161 A JP 2005286161A JP 2004099127 A JP2004099127 A JP 2004099127A JP 2004099127 A JP2004099127 A JP 2004099127A JP 2005286161 A JP2005286161 A JP 2005286161A
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Japan
Prior art keywords
shape
pattern
incomplete
inspection
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2004099127A
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English (en)
Japanese (ja)
Other versions
JP2005286161A5 (enExample
Inventor
Toru Satake
徹 佐竹
Shinji Nomichi
伸治 野路
Masaki Hatakeyama
雅規 畠山
Kenji Watanabe
賢治 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ebara Corp
Original Assignee
Ebara Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ebara Corp filed Critical Ebara Corp
Priority to JP2004099127A priority Critical patent/JP2005286161A/ja
Priority to US11/091,704 priority patent/US7220604B2/en
Publication of JP2005286161A publication Critical patent/JP2005286161A/ja
Priority to US11/783,793 priority patent/US20070192057A1/en
Publication of JP2005286161A5 publication Critical patent/JP2005286161A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/305—Contactless testing using electron beams
    • G01R31/307—Contactless testing using electron beams of integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2004099127A 2004-03-30 2004-03-30 形状修復方法及び装置、並びにそれらを用いた半導体デバイス製造方法 Withdrawn JP2005286161A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004099127A JP2005286161A (ja) 2004-03-30 2004-03-30 形状修復方法及び装置、並びにそれらを用いた半導体デバイス製造方法
US11/091,704 US7220604B2 (en) 2004-03-30 2005-03-29 Method and apparatus for repairing shape, and method for manufacturing semiconductor device using those
US11/783,793 US20070192057A1 (en) 2004-03-30 2007-04-12 Method and apparatus for repairing shape, and method for manufacturing semiconductor device using those

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004099127A JP2005286161A (ja) 2004-03-30 2004-03-30 形状修復方法及び装置、並びにそれらを用いた半導体デバイス製造方法

Publications (2)

Publication Number Publication Date
JP2005286161A true JP2005286161A (ja) 2005-10-13
JP2005286161A5 JP2005286161A5 (enExample) 2007-04-19

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JP2004099127A Withdrawn JP2005286161A (ja) 2004-03-30 2004-03-30 形状修復方法及び装置、並びにそれらを用いた半導体デバイス製造方法

Country Status (2)

Country Link
US (2) US7220604B2 (enExample)
JP (1) JP2005286161A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1777936A1 (en) 2005-09-30 2007-04-25 Brother Kogyo Kabushiki Kaisha Multi function peripheral
KR101923339B1 (ko) * 2010-01-26 2018-11-28 램 리써치 코포레이션 웨이퍼의 처리 방법

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US20050255611A1 (en) * 2004-05-14 2005-11-17 Patterson Oliver D Defect identification system and method for repairing killer defects in semiconductor devices
US7961032B1 (en) * 2009-11-30 2011-06-14 International Business Machines Corporation Method of and structure for recovering gain in a bipolar transistor
US20140064596A1 (en) * 2012-08-29 2014-03-06 Micron Technology, Inc. Descriptor guided fast marching method for analyzing images and systems using the same
US10199283B1 (en) 2015-02-03 2019-02-05 Pdf Solutions, Inc. Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage
US9799575B2 (en) 2015-12-16 2017-10-24 Pdf Solutions, Inc. Integrated circuit containing DOEs of NCEM-enabled fill cells
US10593604B1 (en) 2015-12-16 2020-03-17 Pdf Solutions, Inc. Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
US10978438B1 (en) 2015-12-16 2021-04-13 Pdf Solutions, Inc. IC with test structures and E-beam pads embedded within a contiguous standard cell area
US9929063B1 (en) 2016-04-04 2018-03-27 Pdf Solutions, Inc. Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
US9905553B1 (en) 2016-04-04 2018-02-27 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
US9627370B1 (en) 2016-04-04 2017-04-18 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells
US9748153B1 (en) 2017-03-29 2017-08-29 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
US9773774B1 (en) 2017-03-30 2017-09-26 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
US9786649B1 (en) 2017-06-27 2017-10-10 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
US9865583B1 (en) 2017-06-28 2018-01-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells
US10096530B1 (en) 2017-06-28 2018-10-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
CN112233993B (zh) * 2020-09-24 2022-10-21 上海华力集成电路制造有限公司 检测晶圆通孔缺陷的方法及装置

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US3876879A (en) * 1973-11-09 1975-04-08 Calspan Corp Method and apparatus for determining surface characteristics incorporating a scanning electron microscope
US4108751A (en) * 1977-06-06 1978-08-22 King William J Ion beam implantation-sputtering
US4560435A (en) * 1984-10-01 1985-12-24 International Business Machines Corporation Composite back-etch/lift-off stencil for proximity effect minimization
US4906326A (en) * 1988-03-25 1990-03-06 Canon Kabushiki Kaisha Mask repair system
US5412210A (en) * 1990-10-12 1995-05-02 Hitachi, Ltd. Scanning electron microscope and method for production of semiconductor device by using the same
JP3464320B2 (ja) * 1995-08-02 2003-11-10 株式会社荏原製作所 高速原子線を用いた加工方法及び加工装置
US5754678A (en) * 1996-01-17 1998-05-19 Photon Dynamics, Inc. Substrate inspection apparatus and method
JPH11307604A (ja) * 1998-04-17 1999-11-05 Toshiba Corp プロセスモニタ方法及びプロセス装置
US6670602B1 (en) * 1998-06-03 2003-12-30 Nikon Corporation Scanning device and scanning method
DE10103061B4 (de) * 2001-01-24 2010-04-08 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Inspektion der Tiefe einer Öffnung in einer dielektrischen Materialschicht
JP2002303586A (ja) * 2001-04-03 2002-10-18 Hitachi Ltd 欠陥検査方法及び欠陥検査装置
JP3698075B2 (ja) * 2001-06-20 2005-09-21 株式会社日立製作所 半導体基板の検査方法およびその装置
US7236847B2 (en) * 2002-01-16 2007-06-26 Kla-Tencor Technologies Corp. Systems and methods for closed loop defect reduction
US6645781B1 (en) * 2002-04-29 2003-11-11 Texas Instruments Incorporated Method to determine a complete etch in integrated devices
US20040040658A1 (en) * 2002-08-29 2004-03-04 Tatehito Usui Semiconductor fabricating apparatus and method and apparatus for determining state of semiconductor fabricating process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1777936A1 (en) 2005-09-30 2007-04-25 Brother Kogyo Kabushiki Kaisha Multi function peripheral
KR101923339B1 (ko) * 2010-01-26 2018-11-28 램 리써치 코포레이션 웨이퍼의 처리 방법

Also Published As

Publication number Publication date
US7220604B2 (en) 2007-05-22
US20070192057A1 (en) 2007-08-16
US20050224457A1 (en) 2005-10-13

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