JP2005276981A - Method of manufacturing module with built-in circuit component - Google Patents

Method of manufacturing module with built-in circuit component Download PDF

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JP2005276981A
JP2005276981A JP2004086243A JP2004086243A JP2005276981A JP 2005276981 A JP2005276981 A JP 2005276981A JP 2004086243 A JP2004086243 A JP 2004086243A JP 2004086243 A JP2004086243 A JP 2004086243A JP 2005276981 A JP2005276981 A JP 2005276981A
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metal layer
circuit component
manufacturing
plating
component built
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Hiroyuki Ishitomi
裕之 石富
Masaaki Katsumata
雅昭 勝又
Eiji Kawamoto
英司 川本
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a module with built-in circuit components which can easily accomplish a shielding effect good enough for reduction in size, height, and weight of an electronic apparatus which is responsive to higher frequency by improving the shielding property of the module with built-in circuit components. <P>SOLUTION: In manufacturing the module with built-in circuit components, a plate member 20 formed with through-holes 21 and a releasing film 25 mounted with circuit components 24 are laminated to form an electric insulation substrate 26. The electric insulation substrate 26 is cut into single circuit boards. Then, on the front surface and cut faces of an insulating resin of each single circuit board 31 divided by cutting, a first metal layer 28 is formed by electroless copper plating, a second metal layer 29 is formed by electrolytic copper plating, and a third metal layer 30 for preventing the oxidation of copper is formed by metal plating. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、各種電子機器、通信機器等に用いられる回路部品内蔵モジュールの製造方法に関するものである。   The present invention relates to a method for manufacturing a circuit component built-in module used in various electronic devices, communication devices, and the like.

従来の電気シールドを有する回路部品内蔵モジュールの製造方法を図１５に示す。このシールドめっき形成方法では、まず図１５（ａ）に示すように集合回路基板１は、いずれかの層にグランドパターン２を有している。集合回路基板１の単一基板毎にＩＣ、チップ抵抗、チップコンデンサなどの回路部品３を所定の位置に搭載し、ダイボンド、ワイヤボンド、リフローなどの手段で集合回路基板１に実装する。次いで、図１５（ｂ）に示すように集合回路基板１の上面全体に無機フィラーと熱硬化性樹脂とを含む混合物からなる絶縁樹脂を充填し、集合回路基板１の上に均一な厚さの絶縁体４を形成して実装部品を封止する。   FIG. 15 shows a conventional method of manufacturing a circuit component built-in module having an electric shield. In this shield plating forming method, first, as shown in FIG. 15A, the collective circuit board 1 has a ground pattern 2 in any layer. A circuit component 3 such as an IC, a chip resistor, and a chip capacitor is mounted at a predetermined position for each single substrate of the collective circuit board 1 and mounted on the collective circuit board 1 by means such as die bonding, wire bonding, and reflow. Next, as shown in FIG. 15B, the entire upper surface of the collective circuit board 1 is filled with an insulating resin made of a mixture containing an inorganic filler and a thermosetting resin, and a uniform thickness is formed on the collective circuit board 1. An insulator 4 is formed to seal the mounted component.

その後、図１５（ｃ）に示すように、ダイシングラインに沿って絶縁体４の上から格子状に切り込みを入れ、集合回路基板１の下半部を残した状態でハーフダイシングを行う。このハーフダイシングによって絶縁体４は単一回路基板毎に溝５が形成されると共に、集合回路基板１の上半部にも切り込みが入るため、グランドパターン２の一端部も集合回路基板１から露出することになる。   Thereafter, as shown in FIG. 15C, half dicing is performed in a state in which a cut is made in a lattice shape from above the insulator 4 along the dicing line and the lower half of the collective circuit board 1 is left. By this half dicing, the insulator 4 is formed with a groove 5 for each single circuit board, and the upper half of the collective circuit board 1 is also cut, so that one end of the ground pattern 2 is also exposed from the collective circuit board 1. Will do.

そして、図１５（ｄ）に示すように、ハーフダイシングが終了した絶縁体４の表面に、ニッケルめっき層６をグランドパターン２と導通させるように形成することで電子部品パッケージの電磁波シールドを行い、単一回路基板に分割して、図１５（ｅ）のような回路部品内蔵モジュールを形成する。   And as shown in FIG.15 (d), the electromagnetic wave shielding of an electronic component package is performed by forming the nickel plating layer 6 in conduction with the ground pattern 2 on the surface of the insulator 4 after the half dicing is completed, Dividing into single circuit boards, a circuit component built-in module as shown in FIG.

なお、この出願の発明に関する先行技術文献情報としては、例えば、特許文献１が知られている。
特開平１１−１６３５８３号公報 As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.
Japanese Patent Laid-Open No. 11-163583

しかしながら、電磁波シールドめっきの被膜方法として、単一基板毎に溝を形成して、グランドパターンを露出してからめっきを行っているが、溝の幅が狭いためにめっき液の侵入が困難で溝部分の均一なるめっき被膜形成は難しく、めっき被膜形成不完全による製品不良が多いという問題点を有していた。   However, as a coating method for electromagnetic wave shielding plating, a groove is formed on each single substrate and plating is performed after exposing the ground pattern. However, since the groove width is narrow, it is difficult to infiltrate the plating solution. It was difficult to form a uniform plating film on the part, and there were many problems of defective products due to incomplete plating film formation.

本発明は上記従来の課題を解決するもので、回路部品内蔵モジュールのシールド性向上に対応し、電子機器の小型化、低背化、軽量化、高周波化に十分なシールド効果を容易に実現する回路部品内蔵モジュールの製造方法を提供することを目的とするものである。   SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and easily realizes a shielding effect sufficient for miniaturization, low profile, light weight, and high frequency of an electronic device, corresponding to improvement in shielding performance of a circuit component built-in module. An object of the present invention is to provide a method for manufacturing a circuit component built-in module.

上記目的を達成するために本発明は、無機フィラーと未硬化状態の熱硬化性樹脂とを含む混合物からなる板状体に貫通孔を形成し、前記貫通孔に熱硬化性の導電性物質を充填した板状体と、表面に配線パターンと回路部品を実装した離型フィルムとを、位置合わせしながら重ねて加圧することにより基板を形成し、次に前記基板から離型フィルムを剥離し、その後前記基板と別の未硬化状態の板状体とをそれぞれ位置合わせしながら重ねて集合回路基板を形成し、次に金属層を形成する面の離型フィルムを剥離し、その後前記集合回路基板を単一基板毎に切断し、次に切断により分割した回路基板の絶縁樹脂表面および切断面に無電解銅めっき層にて第１の金属層、電解銅めっきで第２の金属層、銅の酸化を防止するために金属めっきにて第３の金属層をそれぞれ形成し、その後離型フィルムを集合回路基板から剥離することを特徴とし、電子機器の小型化、低背化、軽量で電磁波シールド性に優れた回路部品内蔵モジュールを構成することができる。   In order to achieve the above object, the present invention forms a through hole in a plate-like body made of a mixture containing an inorganic filler and an uncured thermosetting resin, and a thermosetting conductive substance is formed in the through hole. Forming the substrate by overlapping and pressing the filled plate-like body and the release film having the wiring pattern and the circuit component mounted on the surface while aligning, then peeling the release film from the substrate, Thereafter, the substrate and another uncured plate-like body are aligned and overlapped to form a collective circuit board, and then the release film on the surface on which the metal layer is to be formed is peeled off, and then the collective circuit board Is cut into single substrates, and then the insulating resin surface and the cut surface of the circuit board divided by cutting are electroless copper plated on the first metal layer, electrolytic copper plated on the second metal layer, copper Metal plating is used to prevent oxidation. Each of the metal layers is formed, and then the release film is peeled off from the collective circuit board, and a circuit component built-in module that is small in size, low in profile, lightweight, and excellent in electromagnetic shielding properties Can do.

以上のように本発明は、集合回路基板を個片に分割した後に導体層を形成することにより、回路部品内蔵モジュールのシールド性を向上させることができ、低背化、軽量化、高周波化に十分なシールド効果を有する回路部品内蔵モジュールを提供することができる。   As described above, the present invention can improve the shielding performance of the module with a built-in circuit component by forming the conductor layer after dividing the collective circuit board into pieces, thereby reducing the height, weight and frequency. A circuit component built-in module having a sufficient shielding effect can be provided.

（実施の形態１）
以下、実施の形態１を用いて、本発明の特に請求項１〜７に記載の発明について、図面を参照しながら説明する。 (Embodiment 1)
Hereinafter, the invention described in the first to seventh aspects of the present invention will be described using the first embodiment with reference to the drawings.

図１は、本発明の実施の形態１の回路部品内蔵モジュールの製造方法を示したものである。   FIG. 1 shows a method of manufacturing a circuit component built-in module according to Embodiment 1 of the present invention.

まず、図１に示すように、無機フィラーと未硬化状態の熱硬化性樹脂とを混合してペースト状混練物とし、このペースト状混練物を一定厚みに成型することによって板状体２０を形成する。その後板状体２０の可撓性を維持しながら粘着性を除去することにより、その後の処理を容易にするので、板状体２０の熱処理を行う。また、溶剤によって熱硬化性樹脂を溶解させた混合物では、熱処理をすることによって、溶剤の一部を除去することができる。   First, as shown in FIG. 1, an inorganic filler and an uncured thermosetting resin are mixed to form a paste-like kneaded material, and the plate-like body 20 is formed by molding the paste-like kneaded material to a certain thickness. To do. Thereafter, by removing the adhesiveness while maintaining the flexibility of the plate-like body 20, the subsequent processing is facilitated, so that the plate-like body 20 is heat-treated. In addition, in a mixture in which a thermosetting resin is dissolved with a solvent, a part of the solvent can be removed by heat treatment.

次に、図２に示すように、板状体２０の所望の位置に貫通孔２１を形成する。貫通孔２１は、たとえば、レーザ、ドリルまたは金型による加工で形成する。特にレーザ加工は、微細なピッチで貫通孔２１を形成することができ、削り屑が発生しないため好ましい。また炭酸ガスレーザやエキシマレーザを用いると加工が容易である。なお、貫通孔２１は、ペースト状混練物を成型して板状体２０を形成する際に、同時に形成することができる。   Next, as shown in FIG. 2, a through hole 21 is formed at a desired position of the plate-like body 20. The through-hole 21 is formed by processing with a laser, a drill, or a metal mold | die, for example. In particular, laser processing is preferable because the through holes 21 can be formed at a fine pitch and no shavings are generated. Further, when a carbon dioxide laser or excimer laser is used, processing is easy. The through-hole 21 can be formed at the same time when the paste-like kneaded product is formed to form the plate-like body 20.

その後、図３に示すように、貫通孔２１に導電性樹脂組成物２２を充填する。   Thereafter, as shown in FIG. 3, the conductive resin composition 22 is filled in the through holes 21.

一方、図１〜図３の工程と平行して、図４に示すように、離型フィルム２５上に配線パターン２３を形成し、配線パターン２３に回路部品２４を実装する。離型フィルム２５は、たとえば、銅箔、アルミ箔、ＰＰＳなどのフィルムを用いることができる。配線パターン２３は、たとえば、離型フィルム２５に銅箔を接着した後フォトリソ工程およびエッチング工程を行うことによって形成でき、エッチング法または打ち抜き法で形成された金属板のリードフレームを用いてもよい。   On the other hand, in parallel with the steps of FIGS. 1 to 3, as shown in FIG. 4, the wiring pattern 23 is formed on the release film 25, and the circuit component 24 is mounted on the wiring pattern 23. For the release film 25, for example, a film of copper foil, aluminum foil, PPS, or the like can be used. The wiring pattern 23 can be formed by, for example, performing a photolithography process and an etching process after bonding a copper foil to the release film 25, and a metal plate lead frame formed by an etching method or a punching method may be used.

また、図１〜図４の工程と平行して、図５に示すように、別の離型フィルム２５上に配線パターン２３を図４と同様に形成する。   Further, in parallel with the steps of FIGS. 1 to 4, as shown in FIG. 5, a wiring pattern 23 is formed on another release film 25 in the same manner as in FIG.

次に、図３、図４、図５の工程で形成したものを、図６に示すように、それぞれを位置合わせして重ね合わせる。そしてこの板を加圧、加熱することによって、板状体２０および導電性樹脂組成物２２中の熱硬化性樹脂を硬化させる。加熱は、板状体２０および導電性樹脂組成物２２中の熱硬化性樹脂が硬化する温度以上の温度（１５０℃〜２６０℃）、圧力は１０〜２００ｋｇ／ｃｍ2で行う。 Next, those formed in the steps of FIGS. 3, 4, and 5 are aligned and overlapped as shown in FIG. And the thermosetting resin in the plate-shaped body 20 and the conductive resin composition 22 is hardened by pressurizing and heating this board. The heating is performed at a temperature (150 ° C. to 260 ° C.) that is equal to or higher than the temperature at which the thermosetting resin in the plate-like body 20 and the conductive resin composition 22 is cured, and the pressure is 10 to 200 kg / cm 2 .

硬化後、図７に示すように、板状体２０は電気絶縁性基板２６となり、導電性樹脂組成物２２はインナービア２７となる。これによって、配線パターン２３、回路部品２４と電気絶縁性基板２６が機械的に強固に接着する。また、インナービア２７によって、表裏の配線パターン２３が電気的に接続され、回路部品モジュールの機械的強度がより向上する。   After the curing, as shown in FIG. 7, the plate-like body 20 becomes an electrically insulating substrate 26, and the conductive resin composition 22 becomes an inner via 27. As a result, the wiring pattern 23, the circuit component 24, and the electrically insulating substrate 26 are mechanically firmly bonded. Also, the inner via 27 connects the front and back wiring patterns 23 electrically, and the mechanical strength of the circuit component module is further improved.

その後、図８に示すように、両面の離型フィルム２５を剥離する。   Thereafter, as shown in FIG. 8, the release films 25 on both sides are peeled off.

次に、図９に示すように、図８で形成された電気絶縁性基板２６に、図１〜図７の工程と同様に形成した、少なくとも一つ以上のグランドパターン２３を有する離型フィルム２５と貫通孔２１に導電性樹脂組成物２２が充填された板状体２０を位置合わせして重ねて、図１０に示すように加圧、加熱することによって、未硬化の板状体２０および導電性樹脂組成物２２中の熱硬化性樹脂を硬化させる。   Next, as shown in FIG. 9, a release film 25 having at least one or more ground patterns 23 formed on the electrically insulating substrate 26 formed in FIG. 8 in the same manner as in the steps of FIGS. The plate-like body 20 filled with the conductive resin composition 22 in the through-hole 21 is aligned and overlapped, and pressurized and heated as shown in FIG. The thermosetting resin in the curable resin composition 22 is cured.

その後、図１１に示すように、めっきが必要な面の離型フィルム２５を剥離し、図１２に示すように、ダイシングラインにて、単一回路基板３１毎に分割する。このダイシングによって、配線パターン２３の一端部も露出することになる。   Thereafter, as shown in FIG. 11, the release film 25 on the surface that needs to be plated is peeled off, and as shown in FIG. By this dicing, one end of the wiring pattern 23 is also exposed.

その後、図１２のような分割された単一回路基板３１を、無電解銅めっきの前処理としてまずアミノカルボン酸塩等の活性剤で表面の脱脂、コンディショニングを行い、過硫酸ナトリウム、硫酸混合液で表面を軽くエッチングし、硫酸でデスミアを行う。前処理後パラジウムを単一回路基板３１の表面に付与させ、無電解銅めっき液で銅めっきを行い、約１μｍの厚さの第１の金属層２８を形成する。   Thereafter, the surface of the divided single circuit board 31 as shown in FIG. 12 is first degreased and conditioned with an activator such as aminocarboxylate as a pretreatment for electroless copper plating, and sodium persulfate, sulfuric acid mixed solution Lightly etch the surface with, and desmear with sulfuric acid. After the pretreatment, palladium is applied to the surface of the single circuit board 31, and copper plating is performed with an electroless copper plating solution to form a first metal layer 28 having a thickness of about 1 μm.

ここで、無電解銅めっきだけではめっき被膜の緻密さ、被膜物性が劣るため、第２、第３の金属層２９，３０を形成する。以下、その方法について説明する。   Here, since only the electroless copper plating is inferior in the density and physical properties of the plating film, the second and third metal layers 29 and 30 are formed. The method will be described below.

第１の金属層２８を形成後、ジエタノールアミン、硫酸混合液で表面を脱脂し、硫酸で表面を活性化する。その後硫酸銅めっき液で電解銅めっきを行い、約１〜５μｍの厚さで第２の金属層２９を形成する。   After forming the first metal layer 28, the surface is degreased with a mixture of diethanolamine and sulfuric acid, and the surface is activated with sulfuric acid. Thereafter, electrolytic copper plating is performed with a copper sulfate plating solution to form a second metal layer 29 having a thickness of about 1 to 5 μm.

次に、ジエタノールアミン、硫酸混合液で表面を脱脂し、過硫酸ナトリウム、硫酸混合液で電解銅めっき被膜上の酸化膜を軽くエッチングして除去した後、硫酸で酸活性する。その後銅の酸化防止層からなる電解錫めっきを行い、約１〜６μｍの厚さの電解錫めっき被膜からなる第３の金属層３０を形成する。このようにして、図１３に示すような電磁波シールド層が得られる。   Next, the surface is degreased with a mixture of diethanolamine and sulfuric acid, the oxide film on the electrolytic copper plating film is lightly etched and removed with a mixture of sodium persulfate and sulfuric acid, and then acid-activated with sulfuric acid. Thereafter, electrolytic tin plating made of a copper antioxidant layer is performed to form a third metal layer 30 made of an electrolytic tin plating film having a thickness of about 1 to 6 μm. In this way, an electromagnetic wave shielding layer as shown in FIG. 13 is obtained.

ここで第３の金属層３０を形成した後、１００℃、１時間の熱処理を行うと、単一回路基板３１とめっき被膜との密着性はさらに向上する。さらに、第１、第２の金属層２８，２９のめっき被膜形成後に、それぞれ１００℃、１時間の熱処理を行うと、単一回路基板３１の表面とめっき被膜との密着性はよりいっそう向上する。   Here, after the third metal layer 30 is formed, if heat treatment is performed at 100 ° C. for 1 hour, the adhesion between the single circuit board 31 and the plating film is further improved. Furthermore, if a heat treatment is performed at 100 ° C. for 1 hour after forming the plated films on the first and second metal layers 28 and 29, the adhesion between the surface of the single circuit board 31 and the plated film is further improved. .

なお、電解錫めっきを行うとき、錫めっき浴を周波数１５〜６０Ｈｚの振動攪拌をすることにより錫めっき浴の流動性が良くなり、めっき析出速度が向上し、めっき時間の短縮化が図れると共に、単一回路基板３１の側面部へのめっきカバーリング性が著しく向上し、より電磁波シールド性効果が向上する。   When electrolytic tin plating is performed, the tin plating bath is vibrated and stirred at a frequency of 15 to 60 Hz to improve the fluidity of the tin plating bath, the plating deposition rate is improved, and the plating time can be shortened. The plating covering property to the side surface portion of the single circuit board 31 is remarkably improved, and the electromagnetic wave shielding effect is further improved.

また、錫めっき被膜よりなる第３の金属層３０を形成した単一回路基板３１を、ピーク温度２３０〜３００℃のはんだリフロー炉に通すことにより、錫めっき被膜が溶融し、より緻密な被膜となり耐候性が一段と向上する。   Moreover, by passing the single circuit board 31 on which the third metal layer 30 made of a tin plating film is passed through a solder reflow furnace having a peak temperature of 230 to 300 ° C., the tin plating film is melted and becomes a denser film. The weather resistance is further improved.

なお、第３の金属層３０の形成方法として、スルファミン酸ニッケルめっき液により１〜２μｍの電解ニッケルめっき被膜を形成してもよく、また、次亜リン酸ナトリウムを還元剤とする無電解Ｎｉ−Ｐ（ニッケル−リン）浴でＮｉ−Ｐめっき被膜を形成してもよい。特に、塩水噴霧試験など環境試験においては純ニッケル被膜より、リンを含有することで著しく耐環境特性は向上する。特にＰが６％〜１０％含有することで、Ｎｉ−Ｐ被膜の耐環境性は著しく向上する。   As a method for forming the third metal layer 30, an electrolytic nickel plating film having a thickness of 1 to 2 μm may be formed with a nickel sulfamate plating solution, and electroless Ni— using sodium hypophosphite as a reducing agent. The Ni—P plating film may be formed with a P (nickel-phosphorus) bath. In particular, in an environmental test such as a salt spray test, environmental resistance characteristics are remarkably improved by containing phosphorus rather than a pure nickel coating. In particular, when P is contained in an amount of 6% to 10%, the environmental resistance of the Ni-P coating is remarkably improved.

また、第３の金属層３０の他の形成方法として、３価クロムあるいは６価クロムめっき液により１〜６μｍの電解クロムめっき被膜を形成しても、同等の電磁波シールド層を得ることができる。   Further, as another method for forming the third metal layer 30, even when an electrolytic chromium plating film of 1 to 6 μm is formed with a trivalent chromium or hexavalent chromium plating solution, an equivalent electromagnetic wave shielding layer can be obtained.

金属層を形成後、図１４に示すように、離型フィルム２５を剥離することで回路部品内蔵モジュールが形成される。   After the metal layer is formed, the circuit component built-in module is formed by peeling the release film 25 as shown in FIG.

なお、本実施の形態では、貫通孔２１に充填する導電性物質として導電性樹脂組成物２２を用いたが、熱硬化性の導電性物質であれば何でもよい。   In the present embodiment, the conductive resin composition 22 is used as the conductive material that fills the through hole 21. However, any thermosetting conductive material may be used.

なお、離型フィルム２５の剥離方法は、たとえば、エッチング法によるキャリアを溶解させてもよい。   In addition, the peeling method of the release film 25 may dissolve the carrier by an etching method, for example.

以上のように、本実施の形態では、基板切断し、個片に分割した後に金属層を形成するので、切断された単一回路基板３１の表面および側面に確実に電磁波シールド層が形成されることになり、その結果外部の電界ノイズ、磁界ノイズから電子部品をシールドすることができ、これにより、電子部品パッケージ内部から発生する電界ノイズ、磁界ノイズを外部に放出することがないため、他の周辺の電子部品、電子機器に電波障害を与えることもない。   As described above, in this embodiment, since the metal layer is formed after the substrate is cut and divided into pieces, an electromagnetic wave shielding layer is reliably formed on the surface and side surfaces of the cut single circuit substrate 31. As a result, the electronic component can be shielded from the external electric field noise and magnetic field noise, and thus the electric field noise and magnetic field noise generated from the inside of the electronic component package are not emitted to the outside. It does not cause radio interference to surrounding electronic components and electronic equipment.

本発明は、絶縁体との密着性、耐環境性、電磁波シールド効果に優れた電磁波シールド被膜を有し、各種電子機器、通信機器等に用いられる回路部品内蔵モジュール及びそのシールド被膜形成技術として有用である。   The present invention has an electromagnetic shielding film excellent in adhesion to an insulator, environmental resistance, and electromagnetic shielding effect, and is useful as a circuit component built-in module used in various electronic devices, communication devices, etc. It is.

本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 本発明の実施の形態１における回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of manufacturing method of circuit component built-in module according to Embodiment 1 of the present invention 従来の回路部品内蔵モジュールの製造方法の製造工程図Manufacturing process diagram of a conventional method for manufacturing a circuit component built-in module

符号の説明Explanation of symbols

２０ 板状体
２１ 貫通孔
２２ 導電性樹脂組成物
２３ 配線パターン
２４ 回路部品
２５ 離型フィルム
２６ 電気絶縁性基板
２７ インナービア
２８ 第１の金属層
２９ 第２の金属層
３０ 第３の金属層
３１ 単一回路基板 DESCRIPTION OF SYMBOLS 20 Plate-like body 21 Through-hole 22 Conductive resin composition 23 Wiring pattern 24 Circuit component 25 Release film 26 Electrical insulation board | substrate 27 Inner via | veer 28 1st metal layer 29 2nd metal layer 30 3rd metal layer 31 Single circuit board

Claims (7)

無機フィラーと未硬化状態の熱硬化性樹脂とを含む混合物からなる板状体に貫通孔を形成し、前記貫通孔に熱硬化性の導電性物質を充填した板状体と、表面に配線パターンと回路部品を実装した離型フィルムとを、位置合わせしながら重ねて加圧することにより基板を形成し、次に前記基板から離型フィルムを剥離し、その後前記基板と別の未硬化状態の板状体とをそれぞれ位置合わせしながら重ねて集合回路基板を形成し、次に金属層を形成する面の離型フィルムを剥離し、その後前記集合回路基板を単一基板毎に切断し、次に切断により分割した回路基板の絶縁樹脂表面および切断面に無電解銅めっき層にて第１の金属層、電解銅めっきで第２の金属層、銅の酸化を防止するために金属めっきにて第３の金属層をそれぞれ形成し、その後離型フィルムを集合回路基板から剥離する回路部品内蔵モジュールの製造方法。 A through-hole is formed in a plate-like body made of a mixture containing an inorganic filler and an uncured thermosetting resin, and the through-hole is filled with a thermosetting conductive material, and a wiring pattern is formed on the surface. And a release film on which circuit components are mounted are stacked and pressed while being aligned, and then a substrate is formed. Next, the release film is peeled off from the substrate, and then another uncured plate from the substrate. And forming the collective circuit board by aligning the respective bodies, respectively, then peeling the release film on the surface on which the metal layer is to be formed, and then cutting the collective circuit board into single substrates, A first metal layer with an electroless copper plating layer on the insulating resin surface and cut surface of the circuit board divided by cutting, a second metal layer with electrolytic copper plating, and a metal plating to prevent copper oxidation. 3 metal layers respectively, then Method for producing a circuit component built-in module of peeling the mold film from a set circuit board. 第３の金属層を錫めっきにて形成する請求項１に記載の回路部品内蔵モジュールの製造方法。 The method for manufacturing a circuit component built-in module according to claim 1, wherein the third metal layer is formed by tin plating. 錫めっき時に１５〜６０Ｈｚの周波数で振動撹拌を行う請求項２に記載の回路部品内蔵モジュールの製造方法。 The method of manufacturing a circuit component built-in module according to claim 2, wherein vibration agitation is performed at a frequency of 15 to 60 Hz during tin plating. 錫めっき後、２３０〜３００℃の温度ではんだリフローを行う請求項２に記載の回路部品内蔵モジュールの製造方法。 The method for manufacturing a circuit component built-in module according to claim 2, wherein the solder reflow is performed at a temperature of 230 to 300 ° C. after the tin plating. 第３の金属層をニッケルめっきにて形成する請求項１に記載の回路部品内蔵モジュールの製造方法。 The manufacturing method of the circuit component built-in module according to claim 1, wherein the third metal layer is formed by nickel plating. ニッケルめっきにて形成する第３の金属層はリンを６〜１０％含有する請求項５に記載の回路部品内蔵モジュールの製造方法。 The method for manufacturing a circuit component built-in module according to claim 5, wherein the third metal layer formed by nickel plating contains 6 to 10% of phosphorus. 第３の金属層をクロムめっきにて形成する請求項１に記載の回路部品内蔵モジュールの製造方法。 The method for manufacturing a circuit component built-in module according to claim 1, wherein the third metal layer is formed by chromium plating.
JP2004086243A 2004-03-24 2004-03-24 Method of manufacturing module with built-in circuit component Pending JP2005276981A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008155957A1 (en) * 2007-06-19 2008-12-24 Murata Manufacturing Co., Ltd. Method for manufacturing substrate with built-in component and substrate with built-in component
JP2011155213A (en) * 2010-01-28 2011-08-11 Tdk Corp Method for manufacturing circuit module
US10468353B2 (en) 2016-09-07 2019-11-05 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008155957A1 (en) * 2007-06-19 2008-12-24 Murata Manufacturing Co., Ltd. Method for manufacturing substrate with built-in component and substrate with built-in component
JP2011155213A (en) * 2010-01-28 2011-08-11 Tdk Corp Method for manufacturing circuit module
US10468353B2 (en) 2016-09-07 2019-11-05 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same
US10629544B2 (en) 2016-09-07 2020-04-21 Samsung Electronics Co., Ltd. Semiconductor packages

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