JP2005269512A - Pll circuit, and tuner and receiver equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of improving the phase jitter property of a tuner for the circuit to be mounted on, regardless of the modulation systems of received signals of the tuner. <P>SOLUTION: The PLL circuit has a VCO 4 for outputting an oscillation signal of a frequency according to a control voltage, a phase comparator 2a, and a loop filter 3a for smoothing the output signal of the phase comparator 2a and generating the control voltage. The phase comparator 2a has a phase comparison circuit 7 for generating a signal corresponding to the phase difference between a reference signal of a predetermined frequency inputted to an input terminal 1 and a signal based on the oscillation signal, and a charge pump circuit 8 which outputs a charge pump current whose current value changes to the loop filter 3a, on the basis of a signal outputted from the comparison circuit 7. The cut-off frequency of the loop filter 3a changes according to the charge pump current. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a PLL circuit.

  FIG. 9 shows a circuit block diagram of a general PLL circuit used in a tuner for a television receiver. The PLL circuit of FIG. 9 includes an input terminal 1, a phase comparator 2, a loop filter 3, and a voltage controlled oscillator (hereinafter also referred to as VCO) 4.

  The phase comparator 2 generates a phase difference signal corresponding to the phase difference between the reference signal having a predetermined frequency input to the input terminal 1 and the oscillation signal of the VCO 4. The loop filter 3 smoothes the phase difference signal output from the phase comparator 2 and outputs it to the VCO 4. The VCO 4 outputs an oscillation signal having a frequency corresponding to the signal output from the loop filter 3.

  The phase jitter characteristic of a signal (for example, an intermediate frequency signal) output from a television receiver tuner greatly depends on the loop filter bandwidth of the PLL circuit used in the television receiver tuner.

  FIG. 10 shows the phase jitter characteristics of a tuner for a television receiver. A phase jitter characteristic curve 5 in FIG. 10 shows a phase jitter characteristic curve when the loop filter band of the PLL circuit used in the tuner for the television receiver is wide. A phase jitter characteristic curve 6 in FIG. 3 shows a phase jitter characteristic curve when a loop filter band of a PLL circuit used in a tuner for a television receiver is narrow. Further, the output signal frequency of the PLL circuit is adjusted so that f in FIG. 10 becomes the center frequency of the carrier signal of the tuner for the television receiver.

  As can be seen from FIG. 10, when the loop filter band of the PLL circuit used in the tuner for the television receiver is widened, the phase jitter near the center frequency f is improved, but in the frequency region far from the center frequency f, the phase is reversed. Jitter deteriorates and the noise floor increases as a whole.

For this reason, the signal output unit of a television receiver tuner usually narrows the loop filter band of the PLL circuit to reduce the noise floor. However, when the television receiver tuner receives an OFDM modulation reception signal, carrier signals are present at intervals of about 1 kHz in the reception band. Therefore, the loop filter of the PLL circuit used in the television receiver tuner It is necessary to make the phase jitter near 1 kHz offset good by taking a wide band.
JP-A-9-93125 (first page)

  By the way, the transmission method of CATV terrestrial digital broadcast retransmission in Japan is suitable for cable television, the “pass-through method” in which the terrestrial digital broadcast modulation method (OFDM modulation method) is transmitted as it is via the cable. There are two types of "transmodulation methods" that are converted into QAM modulation methods and transmitted. In order to cope with this, as a tuner for receiving CATV terrestrial digital broadcast retransmission, a tuner (tuner suitable for the pass-through method) having good phase jitter characteristics near the center frequency of the carrier signal, and the center of the carrier signal Two types of tuners (tuners suitable for the transmodulation system) that have good phase jitter characteristics in the frequency domain away from the frequency are necessary and troublesome.

  The PLL synthesizer circuit disclosed in Patent Document 1 suppresses fluctuations in the lock time and noise characteristics by adjusting the charge pump current. However, since the loop filter band is fixed, the phase jitter characteristics are also improved. It was fixed.

  In view of the above problems, the present invention provides a PLL circuit capable of improving the phase jitter characteristics of the tuner regardless of the modulation method of the received signal of the tuner mounted thereon, and a tuner and a receiving apparatus including the PLL circuit. The purpose is to do.

  In order to achieve the above object, a PLL circuit according to the present invention includes a voltage controlled oscillator that outputs an oscillation signal having a frequency corresponding to a voltage applied to a voltage control terminal, a reference signal having a predetermined frequency input from the outside, A phase comparator that generates a phase difference signal corresponding to a phase difference from a signal based on an oscillation signal; and a loop filter that smoothes the phase difference signal output from the phase comparator and outputs the signal to the voltage control terminal. The filter band of the loop filter is made variable.

  In such a PLL circuit, since the filter band of the loop filter is variable, for example, when the received signal of the tuner to be mounted is an OFDM modulation system, the filter band of the loop filter is widened, and the received signal of the tuner is mounted. When the signal is QAM modulation, the filter band of the loop filter is narrowed so that the phase jitter characteristics of the tuner can be obtained regardless of whether the received signal of the tuner mounted is OFDM modulation or QAM modulation. Can be improved. Note that the filter band of the loop filter when the received signal of the tuner to be mounted is a QAM modulation system is 1/6 of the filter band of the loop filter when the received signal of the tuner to be mounted is an OFDM modulation system. The following is desirable. By setting the filter band of the loop filter for the received signal of the tuner thus mounted for each modulation method, the phase jitter characteristic of the tuner is improved regardless of the modulation method of the received signal of the tuner. be able to.

  Further, the phase comparator generates a signal corresponding to a phase difference between a reference signal having a predetermined frequency input from the outside and a signal based on the oscillation signal so that a filter band of the loop filter is variable. And a charge pump circuit that outputs a charge pump current based on a signal output from the phase comparison circuit and has a variable current value of the charge pump current, wherein the loop filter is used as the charge pump current. Accordingly, a filter whose cutoff frequency is variable may be used.

  The loop filter includes a switch and a plurality of resistors connected to the switch so that a filter band of the loop filter is variable, a circuit in which impedance is switched by selection of the switch, a variable resistor, and a variable capacitor And a switch and a plurality of capacitors connected to the switch, and at least one of the circuits whose impedance is switched by the selection of the switch may be provided.

  The loop filter includes a first filter unit, a second filter unit having a narrower filter band than the first filter unit, and the first filter unit or the second filter unit so that a filter band of the loop filter is variable. You may make it provide the switch which selects any one of a filter part.

  Further, the loop filter includes a first filter unit, a second filter unit whose filter band is narrower than the first filter unit, and an input signal of the loop filter so that the filter band of the loop filter is variable. A switch for selecting one of the band-limited output by the first filter unit and the second filter unit and output from the loop filter, or the band-limited output by only the first filter unit and output from the loop filter; You may make it provide.

  Further, a tuner according to the present invention is configured to include any of the PLL circuits described above, and a receiving device according to the present invention is configured to include the tuner.

  Since the tuner according to the present invention includes any of the above PLL circuits, the phase jitter characteristics can be improved regardless of the modulation method of the received signal. In addition, since the receiving apparatus according to the present invention includes the tuner, reception characteristics (for example, BER (bit error rate)) can be improved regardless of the modulation method of the received signal.

  According to the present invention, it is possible to realize a PLL circuit capable of improving the phase jitter characteristic of the tuner regardless of the modulation method of the received signal of the tuner mounted, and a tuner and a receiving apparatus including the PLL circuit.

  An embodiment of the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described. The configuration of the PLL circuit according to the first embodiment of the present invention is shown in FIG. 1, the same parts as those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The PLL circuit of FIG. 1 has a configuration in which the phase comparator 2 and the loop filter 3 of the PLL circuit of FIG. 9 are replaced with a phase comparator 2a and a loop filter 3a, respectively.

  The phase comparator 2 a includes a phase comparison circuit 7 and a charge pump circuit 8. A frequency dividing circuit (not shown) divides the oscillation frequency of the VCO 4 into N equal parts. The phase comparison circuit 7 outputs a positive signal when the phase of the output signal of the frequency divider circuit is delayed from the phase of the reference signal of a predetermined frequency input to the input terminal 1, and outputs the positive signal of the frequency divider circuit. When the phase is ahead of the phase of the reference signal having a predetermined frequency input to the input terminal 1, a negative signal is output. The charge pump circuit 8 outputs a positive charge pump current when the output of the phase comparison circuit 7 is positive, and outputs a negative charge pump current when the output of the phase comparison circuit 7 is negative. This charge pump current becomes a phase difference signal of the phase comparator 2a. The phase comparator 2a has several kinds of set values for the charge pump current, and selects a set value for the charge pump current value by inputting a control signal from the outside of the phase comparator 2a. The control signal includes information on set values such as the oscillation frequency, charge pump current, and step frequency of the VCO 4. By changing the set value of the charge pump current that is one of the information included in the control signal according to the modulation method of the received signal, the charge output from the charge pump circuit 8 according to the modulation method of the received signal The value of the pump current can be changed. Similarly, by changing the set value of the step frequency, which is one of the information included in the control signal, according to the modulation method of the received signal, it is output from the charge pump circuit 8 according to the modulation method of the received signal. The charge pump current value to be changed can be changed.

The loop filter 3a is an active filter including capacitors C1 to C3, resistors R1 and R2, a transistor Q1, and a terminal T1. A fixed voltage is applied to the terminal T1. The base current of the transistor Q1 is adjusted by the phase comparator 2a. If the base current of the transistor Q1 increases, the collector current passing through the transistor Q1 from the terminal T1 also increases, and the voltage drop due to the resistor R2 increases. The applied voltage will be lower. The cut-off frequency of the loop filter 3a can be expressed by the following equation (1). Incidentally, (1) f _c in the formula represents the cutoff frequency of the loop filter 3a, K _v represents the control sensitivity [rad / VS] of VCO 4, I _cp charge pump current output from the charge pump circuit 8 [A], ω _n represents each natural frequency [rad / S], ε represents a damping factor, C ₂ represents a constant, and N represents a total frequency division number.

  As can be seen from the above equation (1), the cut-off frequency of the loop filter 3 a is proportional to the charge pump current output from the charge pump circuit 8. Therefore, by changing the charge pump current, the loop filter band of the PLL circuit can be changed, and the phase jitter characteristic of the tuner to be mounted can be set to a desired characteristic. For example, when the received signal of the tuner to be mounted is the OFDM modulation system, the filter band of the loop filter 3a is widened, and when the received signal of the tuner to be mounted is the QAM modulation system, the filter band of the loop filter 3a. By narrowing, the phase jitter characteristic of the tuner can be improved regardless of whether the received signal of the tuner mounted is the OFDM modulation system or the QAM modulation system. Note that the charge pump current output from the charge pump circuit 8 when the received signal of the mounted tuner is the QAM modulation system is the same as the charge pump current output from the charge pump circuit 8 when the received signal of the mounted tuner is the OFDM modulation system. It is desirable to set it to 1/6 or less of the output charge pump current.

  Next, second to fourth embodiments of the present invention will be described. In the second to fourth embodiments of the present invention, an active filter is used as the loop filter of the PLL circuit. The configuration of the PLL circuit according to the second embodiment of the present invention is shown in FIG. 2A, the configuration of the PLL circuit according to the third embodiment of the present invention is shown in FIG. 2B, and the fourth embodiment of the present invention is shown. The configuration of the PLL circuit according to the embodiment is shown in FIG. 2, the same parts as those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

The PLL circuit of FIG. 2A has a configuration in which the loop filter 3 of the PLL circuit of FIG. 9 is replaced with a loop filter 3b. The loop filter 3b includes a switch 9, resistors R3 and R4, an operational amplifier 10, and a capacitor C4. The resistance R ₃ of the resistor R3, the resistance value R ₄ of the resistors R4, when a capacitance value of the capacitor C4 and C _4, the offset frequency of the loop filter 3b in a case where the switch 9 selects the resistor R3 Becomes 1 / (2π · C ₄ · R ₃ ), and when the switch 9 selects the resistor R4, the offset frequency of the loop filter 3b becomes 1 / (2π · C ₄ · R ₄ ). Therefore, the offset frequency can be switched by switching the switch 9, and the filter band of the loop filter 3b is variable.

The PLL circuit in FIG. 2B has a configuration in which the loop filter 3 of the PLL circuit in FIG. 9 is replaced with a loop filter 3c. The loop filter 3c includes a variable resistor R5, an operational amplifier 10, and a capacitor C5. When the resistance value of the variable resistor R5 is R ₅ and the capacitance value of the capacitor C5 is C ₅ , the offset frequency of the loop filter 3c is 1 / (2π · C ₅ · R ₅ ). Therefore, by changing the resistance value R ₅ of the variable resistor R5, can switch the offset frequency, the filter band of the loop filter 3c is varied.

The PLL circuit in FIG. 2C has a configuration in which the loop filter 3 of the PLL circuit in FIG. 9 is replaced with a loop filter 3d. The loop filter 3d includes a resistor R6, an operational amplifier 10, and a variable capacitor C6. If the resistance value of the resistor R6 is R ₆ and the capacitance value of the variable capacitor C6 is C ₆ , the offset frequency of the loop filter 3d is 1 / (2π · C ₆ · R ₆ ). Therefore, by changing the capacitance value C ₆ of the variable capacitance C6, can switch the offset frequency, the filter band of the loop filter 3d is varied.

  Next, fifth to seventh embodiments of the present invention will be described. In the fifth to seventh embodiments of the present invention, a lag filter is used as the loop filter of the PLL circuit. The configuration of the PLL circuit according to the fifth embodiment of the present invention is shown in FIG. 3A, the configuration of the PLL circuit according to the sixth embodiment of the present invention is shown in FIG. 3B, and the seventh embodiment of the present invention is implemented. The configuration of the PLL circuit according to the embodiment is shown in FIG. In FIG. 3, the same parts as those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

The PLL circuit in FIG. 3A has a configuration in which the loop filter 3 of the PLL circuit in FIG. 9 is replaced with a loop filter 3e. The loop filter 3e includes a switch 11, resistors R7 and R8, and a capacitor C7. The resistance value R ₇ of the resistor R7, the resistance value R ₈ of the resistor R8, the capacitance value of the capacitance C7 When C _7, the offset frequency of the loop filter 3e if the switch 11 selects the resistor R7 Becomes 1 / (2π · C ₇ · R ₇ ), and when the switch 11 selects the resistor R ₈ , the offset frequency of the loop filter 3 e becomes 1 / (2π · C ₇ · R ₈ ). Therefore, the offset frequency can be switched by switching the switch 11, and the filter band of the loop filter 3e is variable.

The PLL circuit in FIG. 3B has a configuration in which the loop filter 3 of the PLL circuit in FIG. 9 is replaced with a loop filter 3f. The loop filter 3f includes a variable resistor R9 and a capacitor C8. Variable resistor R9 R ₉ the resistance value of the electrostatic capacitance value of the capacitor C8 When C _8, the offset frequency of the loop filter 3f becomes _{1 / (2π · C 8 ·} R 9). Therefore, by changing the resistance value R ₉ of the variable resistor R9, can switch the offset frequency, the filter band of the loop filter 3f is varied. .

The PLL circuit in FIG. 3C has a configuration in which the loop filter 3 of the PLL circuit in FIG. 9 is replaced with a loop filter 3g. The loop filter 3g includes a resistor R10 and a variable capacitor C9. When the resistance value of the resistor R10 is R ₁₀ and the capacitance value of the variable capacitor C9 is C ₉ , the offset frequency of the loop filter 3g is 1 / (2π · C ₉ · R ₁₀ ). Therefore, by changing the capacitance value C ₉ of the variable capacitance C9, can switch the offset frequency, the filter band of the loop filter 3g is varied.

  Next, eighth to tenth embodiments of the present invention will be described. In the eighth to tenth embodiments of the present invention, a lag lead filter is used as the loop filter of the PLL circuit. FIG. 4A shows the configuration of the PLL circuit according to the eighth embodiment of the present invention, and FIG. 4B shows the configuration of the PLL circuit according to the ninth embodiment of the present invention. The configuration of the PLL circuit according to the embodiment is shown in FIG. 4, the same parts as those in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

The PLL circuit of FIG. 4A has a configuration in which the loop filter 3 of the PLL circuit of FIG. 9 is replaced with a loop filter 3h. The loop filter 3h includes a switch 12, resistors R11, R12 and R13, and a capacitor C10. The resistance value R ₁₁ of the resistor R11, the resistance value R ₁₂ of the resistor R12, R ₁₃ the resistance value of the resistor R13, the capacitance values of the capacitance C10 When C _10, switch 12 selects the resistor R11 In this case, the offset frequency of the loop filter 3h is 1 / {2π · C ₁₀ · (R ₁₁ + R ₁₃ )}, and when the switch 12 selects the resistor R12, the offset frequency of the loop filter 3e is 1 / { 2π · C ₁₀ · (R ₁₂ + R ₁₃ )}. Therefore, the offset frequency can be switched by switching the switch 12, and the filter band of the loop filter 3h is variable.

The PLL circuit in FIG. 4B has a configuration in which the loop filter 3 of the PLL circuit in FIG. 9 is replaced with a loop filter 3i. The loop filter 3i includes variable resistors R14 and R15 and a capacitor C11. The resistance value R ₁₄ of the variable resistor R14, the resistance value R ₁₅ of the variable resistor R15, the capacitance value of the capacitor C11 when the C _11, the offset frequency of the loop filter 3i is _{1 / {2π · C 11 ·} (R ₁₄ + R ₁₅ )}. Thus, by changing at least one of the resistance R ₉ of the resistance value R ₉ and the variable resistor R9 of the variable resistor R9, can switch the offset frequency, the filter band of the loop filter 3i is varied. Note that either one of the variable resistors R14 and R15 may be replaced with a resistor having a fixed resistance value.

The PLL circuit in FIG. 4C has a configuration in which the loop filter 3 of the PLL circuit in FIG. 9 is replaced with a loop filter 3j. The loop filter 3j includes resistors R16 and R17 and a variable capacitor C12. The resistance value R ₁₆ of the resistor R16, the resistance value R ₁₇ of the resistor R17, when the capacitance value of the variable capacitance C12 and C _12, the offset frequency of the loop filter 3j is _{1 / {2π · C 12 ·} (R 16 + R ₁₇ )}. Therefore, by changing the capacitance value C ₁₂ of the variable capacitance C12, can switch the offset frequency, the filter band of the loop filter 3j is varied.

  The variable capacitor may be configured using a variable capacitance diode. For example, the loop filter 3g in FIG. 3C is as shown in FIG. 5 when a variable capacitance diode is used. In FIG. 5, the same parts as those in FIG. A series circuit of the capacitor C13 and the variable capacitance diode D1 provided in the loop filter of FIG. 5 corresponds to the variable capacitor C9 provided in the loop filter 3g in FIG. The capacitance value of the variable capacitance diode D1 varies according to the voltage applied to the connection node between the capacitance C13 and the variable capacitance diode D1.

  In the second embodiment, the fifth embodiment, and the sixth embodiment, the resistor is selected by the switch. However, a plurality of capacitors having different capacitance values are provided, and the switch selects the capacitor instead of the resistor. I do not care.

  Further, the loop filter 3 of the PLL circuit of FIG. 9 is a multi-stage filter in which at least two of the loop filters 3b to 3g are combined (for example, a two-stage filter in which the loop filter 3b and the loop filter 3h shown in FIG. 6 are combined). ), The PLL circuit according to the present invention can be realized.

  Next, eleventh to twelfth embodiments of the present invention will be described. In the eleventh to twelfth embodiments of the present invention, a filter having two filter units is used as a loop filter of a PLL circuit. FIG. 7A shows the configuration of the PLL circuit according to the eleventh embodiment of the present invention, and FIG. 7B shows the configuration of the PLL circuit according to the twelfth embodiment of the present invention. 7 that are the same as those in FIG. 9 are given the same reference numerals, and detailed descriptions thereof are omitted.

The PLL circuit of FIG. 7A has a configuration in which the loop filter 3 of the PLL circuit of FIG. 9 is replaced with a loop filter 3k. The loop filter 3k includes a switch 13, a lag filter including a resistor R18 and a capacitor C14, and a lag filter including a resistor R19 and a capacitor C15. The resistance value R ₁₈ of the resistor R18, the capacitance value C ₁₄ of the capacitor C14, and the resistance value of the resistor R19 R _19, the capacitance values of the capacitance C15 and C _15, the switch 13 the resistor R18 and capacitor C14 Is selected, the offset frequency of the loop filter 3k is 1 / (2π · C ₁₄ · R ₁₈ ), and the switch 13 selects the lag filter consisting of the resistor R19 and the capacitor C15. The offset frequency of the loop filter 3k is 1 / (2π · C ₁₅ · R ₁₉ ). Therefore, the offset frequency can be switched by switching the switch 13, and the filter band of the loop filter 3k is variable.

The PLL circuit of FIG. 7B has a configuration in which the loop filter 3 of the PLL circuit of FIG. 9 is replaced with a loop filter 3l. The loop filter 31 includes a lag filter composed of a resistor R20 and a capacitor C16, a switch 14, and a lag filter composed of a resistor R21 and a capacitor C17. The lag filter including the resistor R21 and the capacitor C17 is a filter having a narrower filter band than the lag filter including the resistor R20 and the capacitor C16. R ₂₀ the resistance value of the resistor R20, the capacitance value C ₁₆ of the capacitor C16, and the resistance value of the resistor R21 R _21, the capacitance values of the capacitance C17 and C _17, the switch 14 the resistor R21 and capacitor C17 When the input terminal of the lag filter consisting of is selected, the input signal of the loop filter 3l is band-limited by the lag filter consisting of the resistor R20 and the capacitor C16 and the lag filter consisting of the resistor R21 and the capacitor C17. Therefore, the offset frequency of the loop filter 3l becomes 1 / (2π · C ₁₇ · R ₂₁ ), the filter band becomes narrower, and the switch 14 selects the output terminal of the lag filter composed of the resistor R21 and the capacitor C17. In this case, the input signal of the loop filter 3l is banded only by the lag filter including the resistor R20 and the capacitor C16. Since being limited output from the loop filter 3l, the offset frequency of the loop filter 3l filter bandwidth is wider becomes _{1 / (2π · C 16 ·} R 20). Therefore, the offset frequency can be switched by switching the switch 14, and the filter band of the loop filter 3l is variable.

  In the second to twelfth embodiments, it is possible to change the loop filter band of the PLL circuit to make the phase jitter characteristic of the tuner on which the PLL circuit is mounted a desired characteristic. For example, when the received signal of the tuner to be mounted is the OFDM modulation system, the filter band of the loop filter is widened, and when the received signal of the tuner to be mounted is the QAM modulation system, the filter band of the loop filter is narrowed. This makes it possible to improve the phase jitter characteristics of the tuner regardless of whether the received signal of the mounted tuner is of the OFDM modulation scheme or the QAM modulation scheme. Note that the filter band of the loop filter when the received signal of the tuner to be mounted is the QAM modulation system is 1/6 or less of the filter band of the loop filter when the received signal of the tuner to be mounted is the OFDM modulation system. It is desirable to do.

  Next, the receiving apparatus according to the present invention will be described. An example of the configuration of the receiving apparatus according to the present invention is shown in FIG. The receiving apparatus in FIG. 8 is a receiving apparatus that receives CATV terrestrial digital broadcast retransmission, and includes an RF input terminal 15, an RF amplifier 16, an RF attenuator 17, a mixer 18, a crystal oscillator 19, A PLL circuit 20, a variable gain amplifier 21, a mixer 22, a local oscillator 23, and a demodulation unit 24 are provided.

  An RF signal for CATV terrestrial digital broadcast retransmission is input to the RF input terminal 15 via a cable (not shown).

  The RF signal input to the RF input terminal 15 is amplified by the RF amplifier 16, level-adjusted by the RF attenuator 17, and sent to the mixer 18.

  The RF signal output from the RF attenuator 17 is mixed with the oscillation signal output from the PLL circuit 20 by the mixer 18, converted into a first intermediate frequency signal, level-adjusted by the variable gain amplifier 21, and then to the mixer 22. Sent out. Note that the gain of the RF attenuator 17 and the variable gain amplifier 21 changes according to the AGC control voltage supplied from the demodulator 24. The PLL circuit 20 has the same configuration as the PLL circuit shown in FIG. 1 and receives a reference signal output from the crystal oscillator 19.

  The first intermediate frequency signal output from the variable gain amplifier 21 is mixed with the local oscillation signal output from the local oscillator 23 by the mixer 22, converted into a second intermediate frequency signal, and sent to the demodulator 24. The demodulator 24 demodulates the second intermediate frequency signal and generates an AGC control voltage based on the second intermediate frequency signal.

  8 includes a PLL circuit having the same configuration as the PLL circuit shown in FIG. 1, the RF input terminal 15, the RF amplifier 16, the RF attenuator 17, the mixer 18, the crystal oscillator 19, and the like. The phase jitter characteristics of the tuner unit constituted by the PLL circuit 20, the variable gain amplifier 21, the mixer 22, and the local oscillator 23 can be improved regardless of the modulation method of the RF signal. As a result, reception characteristics (for example, BER (bit error rate)) can be improved regardless of the modulation method of the RF signal.

  In the above-described embodiment, the case where the reception signal of the tuner equipped with the PLL circuit is the OFDM modulation system and the case of the QAM modulation system has been described. However, the reception signal of another modulation system may be used.

  In the PLL circuit according to the present invention, a frequency divider may be provided between the voltage controlled oscillator and the phase comparator.

These are figures which show the structure of the PLL circuit which concerns on 1st embodiment of this invention. These are figures which show the structure of the PLL circuit which concerns on 2nd-4th embodiment of this invention. These are figures which show the structure of the PLL circuit which concerns on 5th-7th embodiment of this invention. These are figures which show the structure of the PLL circuit which concerns on 8th-10th embodiment of this invention. These are figures which show one structural example of the loop filter using a variable capacitance diode. These are figures which show the example of 1 structure of a multistage filter. These are figures which show the structure of the PLL circuit which concerns on 11th-12th embodiment of this invention. These are figures which show the example of 1 structure of the receiver which concerns on this invention. These are circuit block diagrams of a general PLL circuit. FIG. 4 is a diagram showing phase jitter characteristics of a tuner for a television receiver.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input terminal 2 Phase comparator 3, 3a-3l Loop filter 4 Voltage controlled oscillator (VCO)
7 phase comparison circuit 8 charge pump circuit 9, 11-14 switch 10 operational amplifier 20 PLL circuit

Claims (7)

A voltage-controlled oscillator that outputs an oscillation signal having a frequency corresponding to a voltage applied to the voltage control terminal, and a phase difference signal corresponding to a phase difference between a reference signal having a predetermined frequency input from the outside and a signal based on the oscillation signal In a PLL circuit comprising: a phase comparator that generates a signal; and a loop filter that smoothes a phase difference signal output from the phase comparator and outputs the signal to the voltage control terminal.
A PLL circuit characterized in that a filter band of the loop filter is variable. The phase comparator generates a signal corresponding to a phase difference between a reference signal having a predetermined frequency input from the outside and a signal based on the oscillation signal, and based on a signal output from the phase comparator A charge pump circuit that outputs a charge pump current and varies a current value of the charge pump current,
The PLL circuit according to claim 1, wherein the loop filter is a filter whose cutoff frequency varies according to the charge pump current.   The loop filter includes a switch and a plurality of resistors connected to the switch, and a circuit in which impedance is switched by selection of the switch, a variable resistor, a variable capacitor, and a plurality of capacitors connected to the switch and the switch. The PLL circuit according to claim 1, further comprising at least one of circuits that are provided and whose impedance is switched by selection of the switch.   The loop filter includes a first filter unit, a second filter unit having a narrower filter band than the first filter unit, and a switch for selecting either the first filter unit or the second filter unit. Item 2. The PLL circuit according to Item 1.   The loop filter includes a first filter unit, a second filter unit having a narrower filter band than the first filter unit, and an input signal of the loop filter is band-limited by the first filter unit and the second filter unit. The PLL circuit according to claim 1, further comprising: a switch that selects one of the output from the loop filter and the output from the loop filter after being band-limited only by the first filter unit.   A tuner comprising the PLL circuit according to claim 1.   A receiving apparatus comprising the tuner according to claim 6.

Images