JP3461905B2 - Digital transmission signal receiving circuit - Google Patents

Digital transmission signal receiving circuit

Info

Publication number
JP3461905B2
JP3461905B2 JP07756594A JP7756594A JP3461905B2 JP 3461905 B2 JP3461905 B2 JP 3461905B2 JP 07756594 A JP07756594 A JP 07756594A JP 7756594 A JP7756594 A JP 7756594A JP 3461905 B2 JP3461905 B2 JP 3461905B2
Authority
JP
Japan
Prior art keywords
signal
intermediate frequency
capacitor
digital transmission
means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07756594A
Other languages
Japanese (ja)
Other versions
JPH07288483A (en
Inventor
秀起 大戸
敏正 安達
裕司 小野
隆輔 泉
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP07756594A priority Critical patent/JP3461905B2/en
Publication of JPH07288483A publication Critical patent/JPH07288483A/en
Application granted granted Critical
Publication of JP3461905B2 publication Critical patent/JP3461905B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit for demodulating a digital transmission signal, and more particularly to a digital transmission signal receiving circuit that is resistant to external vibration.

[0002]

2. Description of the Related Art Conventionally, when receiving a satellite broadcast (hereinafter referred to as BS broadcast) signal, a satellite broadcast signal having a frequency of 12 GHz is converted to a BS intermediate frequency signal having a frequency of 1.2 GHz by a parabolic antenna and a BS converter arranged outdoors. It is converted to a first intermediate frequency signal) and supplied to the BS tuner of the indoor unit. The BS tuner is built in, for example, a television receiver, converts the first intermediate frequency signal into a second intermediate frequency signal, and performs FM demodulation to extract a baseband video signal and a PCM audio digital signal. ing. As described above, in the conventional general BS broadcasting, the video signal is transmitted in analog and the audio signal is transmitted in digital.

However, in recent years, with the improvement of image data compression technology, television broadcasting systems for digitally transmitting video signals have been developed in various countries. FIG. 5 shows a receiving circuit for receiving such a conventional digitally modulated transmission signal, and particularly shows a configuration of a frequency conversion section.

The example of FIG. 5 shows a receiving circuit in a television receiver, and reference numeral 71 is an input terminal to which a first intermediate frequency signal a3 obtained by converting a satellite broadcast signal from a BS converter into a band of 950 to 1450 MHz is introduced. Is.
The first intermediate frequency signal a3 guided to the input terminal 71
Is amplified by an amplifier 72, level-adjusted by a volume 73, further amplified by an amplifier 74, and supplied to one input terminal of a mixer 75 as a first intermediate frequency signal b3.

The variable local oscillator 81 oscillates an arbitrary local oscillation signal c3 based on the channel selection data, amplifies the local oscillation signal c3 by an amplifier 82, and outputs the local oscillation signal d3 to the other side of the mixer 75. Is supplied to the input terminal of.

The mixer 75 has a first intermediate frequency signal b.
3 is combined with the local oscillation signal d3 to obtain 140
It is converted into the second intermediate frequency signal e3 centered on MHz and supplied to the amplifier 76. The amplifier 76 amplifies the second intermediate frequency signal e3 from the mixer 75 and supplies it to the filter 77. The filter 77 has a second output that is the output of the amplifier 76.
It removes unnecessary signals from the intermediate frequency signal f3 and supplies the second intermediate frequency signal g3 to the amplifier 78.

The amplifier 78 amplifies the second intermediate frequency signal g3 from the filter 77 and guides the second intermediate frequency signal h3 to the output terminal 79. The second intermediate frequency signal h3 guided to the output terminal 79 is demodulated into a digital signal by a phase detection circuit (not shown), and various digital processing such as deinterleaving is performed by a decoder to generate a digital video signal and a digital audio signal. To be converted.

According to such a conventional receiving circuit, the variable local oscillator 81 oscillates a local oscillation signal which changes according to a desired channel, and the mixer 75 is supplied via the amplifier 82.
Is supplied as a local oscillation signal d3 to the other input terminal of
This mixer 75 synthesizes with the first intermediate frequency signal b3,
The second intermediate frequency signal e3 centered at 140 MHz is converted.

Here, the variable frequency range of the variable local oscillator 81 requires 1090 MHz to 1590 MHz,
The variable local oscillator 81 is composed of a voltage controlled oscillator using a variable capacitance diode and a phase locked loop circuit (hereinafter referred to as a PLL circuit).

FIG. 6 is a block diagram showing such a variable local oscillator 81. In FIG. 6, reference numeral 91 is a reference oscillator, which oscillates a reference frequency signal a4 (hereinafter referred to as a reference signal) and supplies the reference signal a4 to the frequency divider 92.
The frequency divider 92 divides the frequency by 1 /
R is set, the reference signal a4 is divided by 1 / R, and the divided signal b4 is supplied to the phase comparator 93.

A 1 / N frequency-divided signal f4 is guided to the other input terminal of the phase comparator 93 by a frequency divider 96 described later. The phase comparator 93 compares the phase of the 1 / R frequency-divided signal b4 from the frequency divider 92 and the 1 / N frequency-divided signal f4 from the frequency divider 96 to obtain the frequency-divided signal b4 and the frequency-divided signal f4.
An error signal c4 showing the difference in frequency between and is created and supplied to the loop filter 94.

The loop filter 94 constitutes an integrating circuit, integrates the error signal c4 from the phase comparator 93,
The control voltage d4 as the result of this integration is supplied to the voltage controlled oscillator 9
Supply to 5.

The voltage controlled oscillator 95 includes a loop filter 9
The oscillating frequency is controlled based on the control voltage d4 from 4 to supply the oscillating signal e4 (c3 in FIG. 5) to the frequency divider 96, and at the same time as the oscillating signal c3, the amplifier 8 in FIG.
Supply to 2. The frequency divider 96 divides the oscillation signal e4 into 1 /
The frequency is divided into N and the divided signal f4 is supplied to the phase comparator 93.

As a result, the voltage-controlled oscillator 95 is repeatedly operated so that the frequency of the oscillation signal e4 becomes close to the N / R frequency of the reference signal a4, and the voltage-controlled oscillator 95.
Controls the frequency of the oscillation signal e4 in accordance with the frequency division ratio 1 / N of the frequency divider 96.

Recently, an integrated circuit is used as the PLL circuit. That is, the above-mentioned reference oscillator 91, frequency divider 92, phase comparator 93, frequency divider 96,
Also, a charge pump (not shown) and the like provided on the output side of the phase comparator 93 are configured on an integrated circuit, and the frequency divider 96 is configured by a swallow counter type programmable counter. The phase comparator 93 operates so that the comparison frequency is 250 kHz, and the loop filter 9
In No. 4, the bandwidth is set to about 10 kHz to reduce the phase noise.

On the other hand, the loop filter 94 includes a plurality of capacitors, and these capacitors are laminated chip capacitors or laminated film capacitors in terms of temperature stability, long-term reliability, size, and the like.

In such a laminated type capacitor, when vibration is applied from the outside, a piezoelectric effect occurs and an equivalent capacitance is changed to generate noise. That is, since the multilayer capacitor has a structure in which electrodes and dielectrics are alternately stacked, the multilayer capacitor causes a capacitance change due to a piezoelectric effect due to vibration.

Here, in the case of a television receiver for receiving an analog television broadcast, noise appears as an extremely fine spot on the screen even if the equivalent capacitance of the loop filter capacitor changes, and is therefore practically used. Although there is no problem in the above, in the television receiver which receives the digital transmission signal shown in FIG. 5, since the digital data obtained by compressing the image data is frequency-converted, the multilayer type capacitor used for the loop filter is vibrated from the outside. When the equivalent capacitance changes in addition, the digital data is interrupted during the vibration period to cause a breakdown, resulting in a problem that the screen quality is significantly deteriorated.

In the case of a television receiver for receiving analog broadcasting, such noise is generated by the loop filter 9
Although it is possible to slow the response of the PLL so as not to make a loop response to the vibration frequency by narrowing the bandwidth of 4, the phase noise is important in the original performance in the transmission of digital data. Therefore, the loop filter 9
When the bandwidth of 4 is narrowed, the loop effect against random noise disappears and the phase noise performance cannot be satisfied,
This leads to deterioration of quality.

[0020]

In the conventional receiving circuit described above, when vibration is applied from the outside to the laminated type capacitor used for the loop filter, a piezoelectric effect occurs,
There is a problem in that equivalent capacitance changes, noise is generated, digital data is interrupted during the vibration period, and breakage occurs, resulting in a significant deterioration in screen quality.

It is an object of the present invention to eliminate the above problems and provide a digital transmission signal receiving circuit capable of reducing the occurrence of noise even when vibration is externally applied to a loop filter capacitor.

[0022]

SUMMARY OF THE INVENTION The present invention is a digital transmission signal receiving circuit having a frequency conversion circuit for mixing an input digital transmission signal and a local oscillation signal and converting the mixture into an intermediate frequency signal. means for generating an oscillating signal, a phase locked loop for controlling the oscillation frequency of the voltage controlled oscillator to the voltage controlled oscillator comprises a loop filter in said phase locked loop, the capacitor used in the loop filter This is a digital transmission signal receiving circuit characterized in that a non-laminated capacitor is used in part .

[0023]

As described above, according to the structure of the present invention, since the non-laminated capacitor in which the piezoelectric effect rarely occurs is used for the capacitor of the loop filter, even if vibration is applied from the outside,
The change in capacitance can be suppressed, and the occurrence of noise can be reduced.

[0024]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a circuit diagram of a variable local oscillator used in a digital transmission signal receiving circuit of the present invention, and FIG. 2 is a block diagram showing a case where the digital transmission signal receiving circuit is applied to a satellite broadcast receiving device.

First, the entire satellite broadcast receiving apparatus will be described with reference to FIG. In FIG. 2, reference numeral 170 is a BS antenna that performs reflection convergence of a satellite broadcast signal, and the satellite broadcast signal reflected and converged by this BS antenna 170 is a BS antenna.
BS of 950 to 1450 MHz by converter 171
It is converted to an intermediate frequency signal (first intermediate frequency signal) a2. The first intermediate frequency signal a2 is amplified by the amplifier 172, the level is adjusted by the volume 173, further amplified by the amplifier 174, and supplied to one input terminal of the mixer 175 as the first intermediate frequency signal b2.

The variable local oscillator 181 oscillates an arbitrary local oscillation signal c2 based on the channel selection data, amplifies the local oscillation signal c2 by the amplifier 182, and outputs the local oscillation signal d2 to the other side of the mixer 175. Supply to the input terminal of.

The mixer 175 synthesizes the first intermediate frequency signal b2 and the local oscillation signal d2 to obtain 14
The second intermediate frequency signal e2 centered at 0 MHz is converted and supplied to the amplifier 176. The amplifier 176 is the mixer 1
The second intermediate frequency signal e2 from 75 is amplified and supplied to the filter 177. The filter 177 removes unnecessary signals from the second intermediate frequency signal f2 that is the output of the amplifier 176, and supplies the second intermediate frequency signal g2 to the amplifier 178.

The amplifier 178 is the second output from the filter 177.
The second intermediate frequency signal h2 is obtained by amplifying the intermediate frequency signal g2.
To the phase detection circuit 179. The phase detection circuit 179 is
Demodulates the second intermediate frequency signal h2 from the amplifier 178,
The digital demodulated signal i2 is supplied to the decoder 180. The decoder 180 performs various digital processes such as deinterleaving on the supplied digital demodulated signal i2 and outputs a digital video signal j2 and a digital audio signal k2 to output terminals 183.
Leads to 184.

In the satellite broadcast receiving apparatus of the present invention as described above, the variable local oscillator 181 and the mixer 175 constitute a frequency conversion circuit and outputs the second intermediate frequency signal e2 centered at 140 MHz.

Next, the variable local oscillator 181 which is an essential part of the present invention will be described with reference to FIG. In FIG.
The variable local oscillator 181 is roughly classified into an integrated circuit 14 for the phase locked loop (hereinafter referred to as PLL / IC14),
It comprises a loop filter 30 and a voltage controlled oscillator 40, and further comprises an integration circuit 60 for lock detection.

In FIG. 1, reference numeral 10 is a power supply line for supplying a DC voltage V1, and the power supply line 10 is connected to a loop filter 30, a voltage controlled oscillator 40, and an integrating circuit 60, and each circuit has a power supply voltage. Is supplied with a DC voltage V1.

On the other hand, the PLL IC 14 has a reference oscillator and a 1 / R divider for dividing the reference frequency signal from the reference oscillator into 1 / R, and further the voltage controlled oscillator 40.
A 1 / N frequency divider that divides the local oscillation signal from 1 to N by 1 / N, and a phase comparator that compares the phases of both signals from the 1 / R frequency divider and the 1 / N frequency divider. It has a charge pump connected to the phase comparator.

The 1 / N frequency divider uses a pulse swallow type, and is composed of a 1/64 and 1/65 prescaler, a programmable counter, and a swallow counter. Terminals Clock, DATA, and LE to which a clock pulse a1, a data signal b1, and a load pulse c1 for setting the frequency division ratio 1 / N are supplied are provided.

The PLL IC 14 is supplied with an input terminal fin to which a local oscillation signal from the voltage controlled oscillator 40 is supplied.
An output terminal fout for outputting a phase comparison signal, a power supply terminal Vcc1 for supplying a power supply voltage for a logic circuit, and a power supply terminal Vcc2 for supplying a power supply voltage for a high frequency circuit,
It has a power supply terminal Vp for the charge pump, and further has input / output terminals OSC IN and OSC OUT of the reference oscillator and a grounding terminal GND.

The power supply line 10 is a PLL / IC.
14 is connected to the charge pump power supply terminal Vp, and the power supply line 10 includes coils L1 and L2 and a capacitor C1.
Is connected to the reference potential point via the coil L1, L2 is connected to the reference potential point via the capacitor C2,
The DC voltage generated at the connection point between the coil L2 and the capacitor C1 is supplied to the power supply terminals Vcc1 and Vcc2 of the PLL IC14.

Further, the input terminals 11, 12 and 13 are connected to a 1 / N frequency division ratio of 1 / N frequency divider from a controller (not shown).
Clock pulse a1 for setting N, data signal b
1, the load pulse c1 is guided, and the input terminals 11, 12,
13 is a PLL via resistors R1, R2 and R3, respectively.
-It is connected to the clock pulse input terminal Clock of IC14, the data signal input terminal DATA, and the load pulse input terminal LE. The input terminals 11, 12, and 13 are connected to the reference potential point via capacitors C11, C12, and C13, respectively, and the input terminals Clock, DATA, and LE are respectively connected to the resistor R.
It is connected to the reference potential point via 4, R5 and R6.

A parallel circuit of a crystal oscillator 21 and a resistor R21 is connected between the input terminal OSC IN and the output terminal OSC OUT of the reference oscillator provided in the PLL IC 14, and the input terminal OSC IN and the output terminal OSC IN are connected. OSC OUT is connected to the reference potential point via capacitors C22 and C21.

Thus, the PLL / IC 14 has the input terminal f
The local oscillation signal supplied to in is divided into 1 / N and supplied to the phase comparator, and the phase comparator divides the 1 / N divided signal and the reference signal into 1 / R. The phase difference from the signal is detected, and the error signal g1 is guided to the output terminal fout via the charge pump. Further, the lock detection signal h of the PLL
1 is led to the lock detection signal output terminal LD.

The error signal g1 from the output terminal fout is supplied to the loop filter 30, and the loop filter 30
The error signal g1 is integrated to generate a control voltage i1, which is supplied to the voltage controlled oscillator 40.

Explaining the voltage controlled oscillator 40, the voltage controlled oscillator 40 includes resistors R41 to R55, capacitors C41 to C52, and transistors Tr41 and Tr4.
2, amplifier 41, variable capacitance diodes VD41, VD4
2 and inductances L41 and L42.

Specifically, the power supply line 10 is connected to the power supply terminal of the amplifier 41, and is also connected to the collector of the transistor Tr41 via the parallel connection of the resistors R41 and R42. The power supply line 10 is connected to the reference potential point through the series connection of the resistors R43 and R44, and is also connected to the reference potential point through the series connection of the resistors R45, R46 and R47. The connection point of the resistors R42 and R45 is connected to the wiring 10 via the capacitor C41.

On the other hand, the output terminal of the loop filter 30 (the connection point between the resistor R36 and the capacitor C34) is connected to the resistor R4.
Variable capacitance diode VD via 8 and R49 connected in series
It is connected to the cathode of 41 and one end of the inductance L41, and the connection point of the resistors R48 and R49 is connected to the reference potential point via the capacitor C42. The other end of the inductance L41 has a variable capacitance diode VD4.
Variable capacitance diode VD42 connected to the cathode of
The anode of is connected to the reference potential point via the inductance L42.

The anode of the variable capacitance diode VD41 is connected to the reference potential point via the resistor R50, and is also connected to the base of the transistor Tr42 via the capacitor C43. The base of the transistor Tr42 is
It is connected to the connection point of the resistors R46 and R47. Further, the emitter of the transistor Tr42 is connected to the base via the resistor R51 and the capacitor C44 connected in series, and is also connected to the reference potential point via the resistor R52.

The emitter of the transistor Tr42 is connected to the reference potential point through the series connection of the capacitors C45 and C46, and the collector of the transistor Tr42 is connected to the connection point of the resistors R45 and R46 and the capacitor C4.
It is connected to the connection point of C5 and C46, and is also connected to the reference potential point via the capacitor C47. The collector of the transistor Tr42 is connected to the base of the transistor Tr41 via the capacitor C48.

The base of the transistor Tr41 is
It is connected to the connection point of the resistors R43 and R44, the emitter of the transistor Tr41 is connected to the reference potential point via the parallel connection of the capacitors C49 and C50, and is also connected to the power supply line 10. Furthermore, the transistor Tr4
The emitter of No. 1 is connected to the reference potential point via the resistor R53, and is connected to the input terminal of the amplifier 41 via the series connection of the capacitor C51 and the resistor R54, and the output terminal of the amplifier 41 is connected to the capacitor C52 and the resistor. Oscillation signal input terminal f of PLL / IC14 via R55 series connection
It is connected to in.

With such a connection, the voltage controlled oscillator 4
In 0, the capacitances of the variable capacitance diodes VD41, VD42 are controlled based on the control voltage i1 from the loop filter 30, and the variable capacitance diodes VD41, VD42,
Inductance L41, L42 and transistor Tr4
The oscillation circuit including 2 oscillates and supplies the oscillation signal f1 from the voltage controlled oscillator 40 to the oscillation signal input terminal fin of the PLL / IC 14. Further, the oscillation signal f1 is the local oscillation signal c2, and the amplifier 182 of FIG.
I am trying to supply it to.

Next, the integrating circuit 60 will be described. The integrator circuit 60 converts the lock detection signal h1 from the output terminal LD of the PLL / IC 14 into a DC level, and guides the lock detector voltage VD to the lock detection terminal 15.
It is composed of a transistor Tr61, resistors R61 to R64, and capacitors C61 to C63.

The emitter of the transistor Tr61 is connected to the power supply line 10, the resistor R61 is connected between the emitter and the base, and the emitter is the capacitor C61.
The lock detection signal h1 from the PLL IC 14 is supplied to the base of the transistor Tr61. The base of the transistor Tr61 is connected to the reference potential point via the capacitor C62, and the collector of the transistor Tr61 is connected to the reference potential point via the resistor R62. Furthermore, the collector of the transistor Tr61 is connected to the lock detection terminal 15 via the resistor R63, and this terminal 15 is connected to the capacitor C.
It is connected to the reference potential point via 63.

With such a connection, the integrating circuit 60
The lock detection signal h1 from the PLL / IC 14 is set to the DC level, the lock detector voltage VD is guided to the detection terminal 15, and this lock detector voltage VD is used as a determination signal for determining whether or not the PLL is locked.

Next, a specific circuit configuration of the loop filter 30, which is a feature of the present invention, will be described in detail.

The loop filter 30 includes an operational amplifier 31,
It is composed of resistors R31 to R36 and capacitors C31 to C34. Of the above capacitors, 1000 pF
A characteristic of the capacitor having the above capacity is that a non-multilayer capacitor is used.

More specifically, the power supply voltage input terminal of the operational amplifier 31 is connected to the power supply line 10, and the power supply line 10 is
It is connected to the reference potential point through the series connection of the resistors R31 and R32. The connection point of the resistors R31 and R32 is connected to the non-inverting input terminal (+) of the operational amplifier 31 and also connected to the reference potential point via the capacitor C31, and the power supply voltage V1 is divided by the resistors R31 and R32 to form a capacitor. It is stabilized by C31 and supplied to the non-inverting input terminal (+) of the operational amplifier 31.

On the other hand, the output terminal of the operational amplifier 31 is connected to the non-inverting input terminal (-) of the operational amplifier 31 via the series circuit of the resistor R35 and the capacitor C33, and the resistor R35 is connected.
A capacitor C30 is connected in parallel with.

The output terminal fout of the PLL / IC14
Is connected to the inverting input terminal (−) of the operational amplifier 31 through the series connection of the resistors R33 and R34, and the resistors R33 and R34 are connected.
The connection point of 34 is connected to the reference potential point via the capacitor C32.

With such a connection, the resistors R34 and R3 are
5. The capacitor C33 constitutes an integrating circuit together with the operational amplifier 31, and the error signal g1 from the output terminal fout of the PLL / IC 14 is transferred to the capacitor C32 via the resistor R33.
Thus, the high frequency component is removed, and the high frequency component is supplied to the non-inverting input terminal (-) of the operational amplifier 31 via the resistor R34 and integrated.

The output terminal of the operational amplifier 31 is a resistor R36.
Is connected to the reference potential point through the series connection of the capacitor C34 and the capacitor C34, and the connection point of the resistor R36 and the capacitor C34 is
A control voltage i1 obtained by integrating the error signal g1 is derived,
It is adapted to be supplied to the voltage controlled oscillator 40.

Here, exemplifying the values of the resistors and capacitors forming the loop filter 30, resistors R31 and R32 are shown.
Has a resistance value of 100 kΩ, resistors R33, R34, and R36 have a resistance value of 1 kΩ, and a resistor R35 has a resistance value of 5.6 kΩ. The capacitor C31 has a capacitance of 0.49.
The μF non-stacked tantalum capacitors C32 and C34 have a capacitance of 2.2 nF, and the non-stacked cylindrical chip capacitor C33 has a capacitance of 1 n.
A non-laminated type plastic film capacitor of 0 nF is used. The capacitor C30 has a capacity of 7
A laminated type capacitor of 50 pF is used.

The operation of the loop filter 30 of such an embodiment will be described with reference to the explanatory views of FIGS. 3 and 4 below.

FIG. 3 is an explanatory diagram showing the output waveform of the second intermediate frequency signal h2 from the amplifier 178 of FIG. 2, and all the capacitors used for the loop filter 30 are multilayer capacitors similar to the conventional ones. The oscilloscope waveform in the case is shown.

The capacitor used in the loop filter 30 in this case will be specifically described. The capacitor C31 is a rectangular chip capacitor having a capacitance of 0.1 μF, and the capacitors C32 and C34 are rectangular chips having a capacitance of 2.2 nF. The capacitor and capacitor C33 have a rectangular chip capacitor with a capacity of 10 nF, and the capacitor C30 has a capacity of 750 p.
A multilayer type F capacitor is used.

Such a laminated type capacitor C3
When 1, C32, C33, C34 are used and vibration is applied to the entire frequency converter, the external effect of vibrations on these capacitors causes a piezoelectric effect and changes the equivalent capacitance. Therefore, as shown in FIG.
The output waveform of the second intermediate frequency signal h2 from 8 has a center frequency of 139.9810 MHz and a bandwidth of 100.00 k.
Although it is Hz, it becomes a state in which noise with large amplitude is superimposed.

On the other hand, FIG. 4 shows an oscilloscope waveform of the second intermediate frequency signal h2 when a non-multilayer capacitor is used for capacitors having a capacitance of 1000 pF or more among the capacitors used in the loop filter 30 of FIG. FIG.

In this case, the capacitor C31 is a non-stacked type tantalum capacitor having a capacitance of 0.49 μF, and the capacitors C32 and C34 have a capacitance of 2.2 nF.
Using a cylindrical chip capacitors of non-laminated type, and the capacitor C33, the capacitance that have used up <br/> Las plastic film capacitors of the non-lamination type 10 nF. As the capacitor C30, a laminated type capacitor having a capacity of 750 pF is used.

When vibration is applied to the entire frequency converter while using such a capacitor, the capacitor C31,
It was confirmed that the piezoelectric effects of C32, C33, and C34 did not occur much even when vibration was applied from the outside, and noise was not generated much. That is, the output waveform of the second intermediate frequency signal h2 from the amplifier 178 shown in FIG. 4 has a center frequency of 139.9810 MHz and a bandwidth of 100.00 kHz, and the amplitude of noise is 1/10 of that of FIG. It has become a degree.

Although noise due to the laminated type capacitor C30 may be considered, the influence on the output waveform of the frequency converter is small with a capacitance of about 750 pF.

As described above, according to the embodiment of the present invention, it is possible to reduce the generation of noise even when vibration is applied to the loop filter from the outside, it is possible to prevent interruption of digital data even when a digital transmission signal is received, and Can be prevented from being significantly disturbed.

In the embodiment of FIG. 1, the capacitor C3
As the combination of the non-laminated capacitors used for 1, C32, C33, and C34, another combination such as all non-laminated plastic film capacitors may be used.

In the embodiment shown in FIG. 1, the loop filter 3 is used in consideration of the manufacturing cost and high density mounting on the printed wiring board.
Of the capacitors used for 0, for capacitors with a capacity of 1000 pF or more, non-laminated capacitors are used,
The capacitor C30 having a capacitance of less than 1000 pF uses a laminated type capacitor, but has a capacitance of 1000 pF.
A non-multilayer capacitor may be used for the capacitor C30 having less than pF. Further, in the embodiment of the present invention shown in FIG. 1, the case where the digital transmission signal receiving circuit is applied to the satellite broadcast receiving apparatus has been described, but the invention may be applied to a device that receives other digital transmission signals.

[0069]

According to the present invention, noise can be reduced even when vibration is externally applied to the loop filter, so that it is possible to prevent interruption of digital data when a digital transmission signal is received, and to greatly reduce the screen size. Can be prevented from being disturbed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of a digital transmission signal receiving circuit according to the present invention.

FIG. 2 is a block diagram showing a case where the embodiment of FIG. 1 is applied to a satellite broadcast receiving device.

3 is an explanatory diagram showing an output waveform of a second intermediate frequency signal when a multilayer capacitor is used for all capacitors used in the loop filter 30 of FIG.

4 is an explanatory diagram showing an output waveform of a second intermediate frequency signal when a non-multilayer capacitor is used for most of the capacitors used in the loop filter 30 of FIG.

FIG. 5 is a block diagram showing a main part of a conventional digital transmission signal receiving circuit.

FIG. 6 is a block diagram showing the variable local oscillator of FIG.

[Explanation of symbols]

14 ... PLL / IC 30 ... Loop filter 40 ... Voltage controlled oscillator C31, C32, C33, C34 ... Non-stacked type capacitor 181 ... Variable local oscillator

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hideki Oto 1-9-2 Harara-cho, Fukaya-shi, Saitama, Ltd. Fukaya Plant, Toshiba Corporation (56) Reference JP-A-4-348608 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H04B 1/26 H03L 7/ 06-7/14 H03H 11/00-11/54

Claims (7)

(57) [Claims]
1. A digital transmission signal receiving circuit having a frequency conversion circuit for mixing an input digital transmission signal and a local oscillation signal and converting the mixture into an intermediate frequency signal, wherein the means for generating the local oscillation signal comprises: A voltage-controlled oscillator and a phase-locked loop that controls the oscillation frequency of the voltage-controlled oscillator are provided, and a loop filter is provided in the phase-locked loop. A non-laminated capacitor is used as a part of the capacitor used for the loop filter. A digital transmission signal receiving circuit characterized by using.
2. An input digital transmission signal and local oscillation
Frequency conversion that mixes with the signal and converts it to an intermediate frequency signal
A digital transmission signal receiving circuit having a circuit, wherein the means for generating the local oscillation signal is a voltage controlled oscillator.
A phase-locked loop that controls the oscillation frequency of this voltage-controlled oscillator.
Loop and a loop filter in the phase-locked loop.
Made has, in a part of the capacitor used in the loop filter, the non
Characterized by using a multilayer type cylindrical chip capacitor
And a digital transmission signal receiving circuit.
3. Input digital transmission signal and local oscillation
Frequency conversion that mixes with the signal and converts it to an intermediate frequency signal
A digital transmission signal receiving circuit having a circuit, wherein the means for generating the local oscillation signal is a voltage controlled oscillator.
A phase-locked loop that controls the oscillation frequency of this voltage-controlled oscillator.
Loop and a loop filter in the phase-locked loop.
Made has, in a part of the capacitor used in the loop filter, the non
Using a laminated type plastic film capacitor
A digital transmission signal receiving circuit characterized by the above.
4. A digital transmission signal is converted into a first intermediate frequency signal by a converter, this first intermediate frequency signal is converted into a second intermediate frequency signal by a local oscillation signal from a local oscillator, and this second intermediate frequency signal is converted. Is a digital transmission signal receiving circuit for demodulating into a video signal, the means for generating the local oscillation signal comprises a voltage-controlled oscillator and a phase-locked loop for controlling the oscillation frequency of the voltage-controlled oscillator. A digital transmission signal receiving circuit, characterized in that a non-multilayer capacitor is used as a part of the capacitor used in the loop filter.
5. The digital transmission signal is a first intermediate frequency signal.
And a first intermediate frequency signal from the converter means for amplifying the first intermediate frequency signal
And a first amplification means that is amplified by the first amplification means.
Level adjustment for adjusting the output level of the first intermediate frequency signal
Means and a first intermediate frequency level-adjusted by the level adjusting means
Second amplification means for amplifying the signal, and varying the frequency of the local oscillation signal based on the tuning data
A variable local oscillator, which is a voltage-controlled oscillator and this voltage
Equipped with a phase locked loop that controls the oscillation frequency of the controlled oscillator
The phase-locked loop has a loop filter.
, A part of the capacitor used for the loop filter,
Variable local oscillation means using a non-stacked capacitor, and a first local amplification means for amplifying the local oscillation signal from the variable local oscillation means.
3 amplifying means, the first intermediate frequency signal from the second amplifying means, and the first intermediate frequency signal
Input the local oscillation signal amplified by the amplifying means of 3,
Convert the first intermediate frequency signal to the second intermediate frequency signal
Mixer means for outputting and unwanted signal from the second intermediate frequency signal from said mixer means
Filter means for removing the
2 means for digitally demodulating the intermediate frequency signal,
A digital transmission signal receiving circuit characterized by the above.
6. A condenser used for the loop filter.
Of the capacitors having a capacity of at least 1000 pF or more
Is characterized by using a non-multilayer capacitor
Digital transmission according to any one of claims 1 to 5.
Signal receiving circuit.
7. The loop filter includes an operational amplifier,
At least the inverting input and output terminals of this operational amplifier
It is composed of an integrating circuit including a first capacitor connected between
At least among the capacitors of the loop filter
Non-stacked type with a capacity of 1000 pF or more
6. A capacitor is used, and the capacitor is used.
The digital transmission signal receiving circuit according to any one of claims.
JP07756594A 1994-04-15 1994-04-15 Digital transmission signal receiving circuit Expired - Fee Related JP3461905B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07756594A JP3461905B2 (en) 1994-04-15 1994-04-15 Digital transmission signal receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07756594A JP3461905B2 (en) 1994-04-15 1994-04-15 Digital transmission signal receiving circuit

Publications (2)

Publication Number Publication Date
JPH07288483A JPH07288483A (en) 1995-10-31
JP3461905B2 true JP3461905B2 (en) 2003-10-27

Family

ID=13637542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07756594A Expired - Fee Related JP3461905B2 (en) 1994-04-15 1994-04-15 Digital transmission signal receiving circuit

Country Status (1)

Country Link
JP (1) JP3461905B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3492225B2 (en) 1999-01-19 2004-02-03 松下電器産業株式会社 Transceiver

Also Published As

Publication number Publication date
JPH07288483A (en) 1995-10-31

Similar Documents

Publication Publication Date Title
US5737035A (en) Highly integrated television tuner on a single microcircuit
US7006805B1 (en) Aliasing communication system with multi-mode and multi-band functionality and embodiments thereof, such as the family radio service
US7127217B2 (en) On-chip calibration signal generation for tunable filters for RF communications and associated methods
DE3913593C2 (en) Circuit arrangement for converting a received modulated information signal into an intermediate frequency signal
US5437051A (en) Broadband tuning circuit for receiving multi-channel signals over a broad frequency range
US5600680A (en) High frequency receiving apparatus
US7272374B2 (en) Dynamic selection of local oscillator signal injection for image rejection in integrated receivers
US7505746B2 (en) IC receiver to minimize tracking error
US5715529A (en) FM receiver including a phase-quadrature polyphase if filter
US6091304A (en) Frequency band select phase lock loop device
DE60033114T2 (en) Multiband mobile unit
US7187913B1 (en) Integrated circuit tuner with broad tuning range
US5752179A (en) Selective RF circuit with varactor tuned and switched bandpass filters
US7715815B2 (en) Integrated tracking filters for direct conversion and low-IF single conversion broadband filters
US7620379B2 (en) Radio frequency tuner
US5701598A (en) Scanning receiver with direct digital frequency synthesis and digital signal processing
US6888580B2 (en) Integrated single and dual television tuner having improved fine tuning
CA2104182C (en) Double conversion digital tuning system
KR20060120593A (en) Broadband integrated digitally tunable filters
US6094236A (en) Tuner circuit
US8139161B2 (en) Broadband integrated tuner
US6658239B1 (en) Fully integrated ALL-CMOS AM transmitter with automatic antenna tuning
EP1195889B1 (en) Tuner
US4162452A (en) Channel selection for a television receiver having low-gain high frequency RF-IF section
US5758276A (en) Double super-heterodyne receiver with low-pass and high-pass filters controlled by respective switching devices

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070815

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080815

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090815

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090815

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100815

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100815

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110815

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110815

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120815

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120815

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130815

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees