JP2005245089A - Power conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce switching loss when a main switch is turned on and when it is turned off and reduce noise in a power conversion apparatus having a V connection inverter circuit. <P>SOLUTION: The output terminal of a voltage step-up conversion circuit 30 is connected to a relay terminal 4. A series circuit of a first and a second capacitors Ca and Cb for dividing voltage is connected between the relay terminal 4 and a second direct-current terminal 2 through a first auxiliary switch Q1. One end of a series circuit of a second auxiliary switch Q2 and a resonance reactor Lr is connected to the relay terminal 4, and the other end of it is connected to the point of interconnection between the first and second capacitors Ca and Cb for dividing voltage. The V connection inverter circuit is connected to the output stage of the relay terminal 4. The balance between the positive current and the negative current of the resonance reactor Lr is improved by providing a period in which the first and second switches Sp and Sn for voltage step-up conversion included in the voltage step-up conversion circuit 30 are simultaneously on-controlled. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a power converter that includes a soft switching circuit and converts direct current to alternating current or alternating current to alternating current.

In the case of obtaining a two-phase AC output in a switching type power converter used for a power conditioner, an uninterruptible power supply, a motor drive inverter, a battery charger, etc., a three-phase inverter or V having a three-phase switching circuit Use a wired inverter. FIG. 1 shows a conventional three-phase voltage type inverter having a V-connection configuration. The inverter shown in FIG. 1 includes first and second DC terminals 1 and 2 to which a DC power source 50 composed of a solar cell, a boost chopper, a rectifier, an electrolytic capacitor, a battery, or the like is connected. The voltage dividing capacitors Ca and Cb, the first and second main switches S1 and S2 constituting the first phase (U phase) switching circuit, and the third and third constituting the third phase (W phase) switching circuit. 4 main switches S3 and S4, individual or parasitic (built-in) first to fourth main diodes D1 to D4 connected in parallel to the first to fourth main switches S1 to S4, and the first and first 2 reactors Lu and Lw, first and second filter capacitors Cf1 and Cf2, first, second and third phase AC terminals 3u, 3v and 3w, a voltage reference value generator 51, and a sawtooth wave Generator 52 and first and second comparators 53, 54 And a switch control signal forming circuit 55.
The first and second voltage dividing capacitors Ca and Cb are connected between the first and second DC terminals 1 and 2 and connected in series with each other. The second-phase AC terminal 3v is connected to an interconnection point between the first and second voltage dividing capacitors Ca and Cb.

The voltage reference value generator 51 generates a first phase voltage reference value Vru and a third phase voltage reference value Vrw composed of a sine wave shown in FIG. The first phase voltage reference value Vru and the third phase voltage reference value Vrw have a phase difference of 60 degrees. Although only one period Tac of the AC voltage is shown in FIG. 2, the voltage reference value generator 51 repeatedly generates the first and third phase voltage reference values Vru and Vrw of FIG.
The sawtooth generator 52 generates the sawtooth voltage Vt shown in FIG. 2A at a frequency sufficiently higher than the repetition frequency of the first and third phase voltage reference values Vru and Vrw of the sine wave.
The first and second comparators 53 and 54 compare the first and third phase voltage reference values Vru and Vrw with the sawtooth voltage Vt and compare the first and third comparators 53 and 54 shown in FIGS. The first and third control signals Vg1 and Vg3 for the main switches S1 and S3 are generated. The switch control signal forming circuit 55 sends the first and third switch control signals Vg1 and vg3 of FIGS. 2B and 2C to the control terminals (gates) of the first and third main switches S1 and S3. The second and fourth switch control signals Vg2 and Vg4, which are phase inversion signals of the first and third switch control signals Vg1 and Vg3, are formed and used as the control terminals of the second and fourth main switches S2 and S4. send.

  By the way, if the current is directly cut off by the first to fourth main switches S1 to S4 in FIG. 1, an electrical stress is applied to the main switches S1 to S4 at the time of turn-off, and switching surge, switching noise, and switching loss are caused. Arise. In addition, switching surge and switching loss become a problem even when the main switches S1 to S4 are turned on.

  It is disclosed in Patent Document 1 described later that soft switching is performed on a conversion switch in a three-phase full-bridge inverter to reduce switching surge, switching noise, and switching loss. However, the soft switching circuit of Patent Document 1 cannot be used as it is in the inverter having the V-connection configuration shown in FIG. Further, the three-phase full-bridge type inverter has a disadvantage that the number of main switches is larger than that of an inverter having a V-connection configuration, which inevitably increases in cost and size.

In view of this, the present applicant has proposed in Japanese Patent Application No. 2003-46219 a power conversion device in which a soft switching circuit is added to the inverter having the V-connection configuration shown in FIG. As shown in FIG. 3, the power conversion device disclosed in the above application is connected to a DC power source composed of a solar cell, a step-up chopper, a rectifier, an electrolytic capacitor, a battery, or the like, like the inverter of FIG. 1 and second DC terminals 1 and 2, first and second voltage dividing capacitors Ca and Cb, and first and second main switches S1 and S2 constituting a first phase (U phase) switching circuit. And the third and fourth main switches S3 and S4 constituting the third phase (W phase) switching circuit and the individual or parasitic (internal) connected in parallel to the first to fourth main switches S1 to S4 First to fourth main diodes D1 to D4 made of diodes, first and second reactors Lu and Lw, first and second filter capacitors Cf1 and Cf2, and first, second and third Has phase AC terminals 3u, 3v, 3w In addition, the first, second, third and fourth resonance capacitors C1, C2, C3, C4 connected in parallel to the first to fourth main switches S1 to S4, and the first and second Auxiliary switches Q1 and Q2, first and second auxiliary diodes Da and Db, and a resonant reactor Lr are provided.

  In FIG. 3, the first to fourth main switches S1 to S4 and the first and second auxiliary switches Q1 and Q2 are shown as IGBTs (Insulated Gate Bipolar Transistors). These are NPN type or PNP type. Another controllable semiconductor switch, such as a transistor, a field effect transistor, or the like can be used.

  The first to fourth main diodes D1 to D4 connected in reverse parallel to the first to fourth main switches S1 to S4 may be individual diodes, or the first to fourth main switches S1 to S4. It may be a known parasitic or built-in diode formed in the semiconductor substrate of S4. The first and second auxiliary diodes Da and Db connected in reverse parallel to the first and second auxiliary switches Q1 and Q2 may be individual diodes, or the first and second auxiliary switches. It may be a known parasitic or built-in diode formed in the semiconductor substrate of Q1 and Q2. The first to fourth main diodes D1 to D4 have a direction to regenerate the power of the load connected to the first, second and third phase AC terminals 3u, 3v and 3w to the DC side. The first and second auxiliary diodes Da and Db have a direction that is reverse-biased by the voltage between the first and second DC terminals 1 and 2.

  The first to fourth resonance capacitors C1 to C4, which can also be called snubber capacitors, may be individual capacitors, or between the main terminals of the first to fourth main switches S1 to S4 (between collector and emitter). May be a parasitic capacitance. In FIG. 3, the sum of the capacitance of the individual capacitors and the parasitic capacitance is shown as first to fourth resonance capacitors C1 to C4.

  The first and second voltage dividing capacitors Ca and Cb made of electrolytic capacitors are connected between the first and second DC terminals 1 and 2 and are connected in series with each other. The second-phase AC terminal 3v is connected to an interconnection point between the first and second voltage dividing capacitors Ca and Cb.

  The power conversion device in FIG. 3 has a relay terminal 4. The relay terminal 4 here means a connecting conductor, a part of an electric circuit, or a boundary point between a soft switching circuit and an inverter circuit.

  The first auxiliary switch Q1 is connected between the first DC terminal 1 and the relay terminal 4 so as to flow current from the first DC terminal 1 toward the relay terminal 4.

The series circuit of the second auxiliary switch Q2 and the resonant reactor Lr is connected to the junction point of the relay terminal 4, the second phase AC terminal 3v, and the first and second voltage dividing capacitors Ca and Cb. The second auxiliary switch Q2 has a direction of flowing current from the relay terminal 4 to the second voltage dividing capacitor Cb.
The resonance reactor Lr as an inductor resonates with the first to fourth resonance capacitors C1 to C4 and can also be called a commutation reactor.

  The first, second, and third phase AC terminals 3u, 3v, 3w output the first, second, and third line voltages Vuv, Vvw, Vwu having a phase difference of 120 degrees from each other. When the first to fourth main switches S1 to S4 are operating as inverters, they function as first, second and third phase output AC terminals.

  The first main switch S1 of the inverter circuit is connected between the relay terminal 4 and the first phase AC terminal 3u via a first reactor Lu. The second main switch S2 is connected between the first phase AC terminal 3u and the second DC terminal 2 via the first reactor Lu. The third main switch S3 is connected between the relay terminal 4 and the third phase AC terminal 3w via a second reactor Lw. The fourth main switch S4 is connected between the third-phase AC terminal 3w and the second DC terminal 2 via the second reactor Lw. Accordingly, the first and second main switches S1 and S2 constitute a first-phase (U-phase) half-bridge conversion circuit, and the third and fourth main switches S3 and S4 are third-phase (W-phase) half-bridges. A conversion circuit is configured.

The first reactor Lu is connected in series between the interconnection point of the first and second main switches S1, S2 and the first phase AC terminal 3u. The second reactor Lw is connected in series between the interconnection point of the third and fourth main switches S3 and S4 and the third phase AC terminal 3w. The first and second reactors Lu and Lw function as filters that remove high-frequency components due to on / off of the first to fourth main switches S1 to S4.
The first filter capacitor Cf1 is connected between the first and second phase AC terminals 3u, 3v. The second filter capacitor Cf2 is connected between the second and third phase AC terminals 3v and 3w. The first and second filter capacitors Cf1 and Cf2 are for removing high-frequency components due to on / off of the first to fourth main switches S1 to S4.
The capacities of the first to fourth resonance capacitors C1 to C4 and the capacities of the first and second filter capacitors Cf1 and Cf2 are much larger than the capacities of the first and second voltage dividing capacitors Ca and Cb. Small.

  In order to form the first to fourth main switch control signals Vg1, Vg2, Vg3, Vg4 for the first to fourth main switches S1 to S4, first and second current detectors CTu, CTw and A main switch control circuit 5 is provided. Further, an auxiliary switch control circuit 6 is provided to form control signals Vq1 and Vq2 for the first and second auxiliary switches Q1 and Q2. The first and second current detectors CTu and CTw detect the currents Iu and Iw flowing through the first and second reactors Lu and Lw, and the main switch control circuit 5 and the auxiliary switch control circuit 6 are detected by lines 7 and 8, respectively. Send to. The main switch control circuit 5 has first, second, third and fourth output lines 9, 10, 11 and 12 for the first, second, third and fourth main switches S1, S2, S3 and S4. The control terminal (gate) is connected via a drive circuit (not shown). The main switch control circuit 5 has a first to a fourth main switch control signals Vg1 to Vg1 in a well-known manner so that a three-phase AC voltage can be obtained at the first, second and third phase AC terminals 3u, 3v and 3w. Vg4 is formed.

  The auxiliary switch control circuit 6 is connected to the lines 7 and 8 for detecting the currents Iu and Iw, and is connected to the main switch control circuit 5 by the line 15, and when the first to fourth main switches S1 to S4 are turned on. The first and second for previously setting the voltage of the first to fourth resonance capacitors C1 to C4 and the voltage between the relay terminal 4 and the second DC terminal 2 to zero or almost zero lower than the power supply voltage. Two auxiliary switch control signals Vq1 and Vq2 are formed and sent to lines 13 and 14, respectively. The lines 13 and 14 are connected to control terminals (gates) of the first and second auxiliary switches Q1 and Q2 through a drive circuit (not shown).

  FIG. 4 is a circuit diagram showing in detail the main switch control circuit 5 and the auxiliary switch control circuit 6 of FIG. The main switch control circuit 5 includes a voltage reference value generator 51, a sawtooth generator 52, first and second comparators 53 and 54, which are formed in the same manner as the conventional inverter control circuit of FIG. In addition to the signal forming circuit 55, a U-phase correction circuit 56 as a first correction circuit and a W-phase correction circuit 57 as a second correction circuit are provided.

  The voltage reference value generator 51 repeatedly generates the first and second voltage reference values Vru and Vrw shown in FIGS. 5B and 5C with a period Tac. The first voltage reference value Vru is the same sine wave as the line voltage Vuv between the first phase, that is, the U phase and the second phase, ie, the V phase, of the three-phase sine wave AC voltage, and the second voltage reference value. Vrw is the same sine wave as the negative phase line voltage Vwv having a phase difference of 180 degrees with respect to the line voltage Vvw between the second phase, ie, the V phase and the third phase, ie, the W phase. Accordingly, as shown in FIGS. 5B and 5C, the first and second voltage reference values Vru and Vrw have a phase difference of 60 degrees, and the second voltage reference value Vrw is the first voltage reference value Vrw. It is 60 degrees ahead of the voltage reference value Vru. Note that the first and second voltage reference values Vru and Vrw in FIGS. 5B and 5C are the same as the first and second voltage reference values Vru and Vrw shown in FIG. When the first voltage reference value Vru is used as a reference, the second voltage reference value Vrw is delayed by 300 degrees from the first voltage reference value Vru.

  The sawtooth generator 52 generates the sawtooth voltage Vt shown in FIG. 5A at a frequency (for example, 20 kHz) sufficiently higher than the frequency (for example, 50 Hz) of the first and second voltage reference values Vru and Vrw. The sawtooth voltage Vt rises at an inclination and then falls vertically. Of course, a sawtooth voltage having a slope opposite to that of the sawtooth voltage Vt in FIG. The U-phase and W-phase correction circuits 56 and 57 are connected between the sawtooth generator 52 and the first and second comparators 53 and 54, and output lines of the first and second current detectors CTu and CTw. The phase of the sawtooth voltage Vt is controlled in response to the signals 7 and 8. That is, as shown in FIG. 5B, the U-phase correction circuit 56 performs the saw operation shown in FIG. 5A during the period t0 to t3 when the U-phase load current Iu shown in FIG. The same phase sawtooth voltage as the wave voltage Vt is output, and the sawtooth voltage Vt of the phase opposite to that of the sawtooth voltage Vt in FIG. 5A is output during the period t3 to t6 when the U phase load current Iu is negative half wave. Output. A first corrected sawtooth voltage Vtu, which is a combination of the positive phase sawtooth voltage and the negative phase sawtooth voltage shown in FIG. 5B, is input to the first comparator 53.

  As shown in FIG. 5 (C), the W-phase correction circuit 57 is shown in FIG. 5 (A) in the periods to to t1 and t4 to t6 in which the W-phase load current Iw shown in FIG. A positive-phase sawtooth voltage equal to the sawtooth voltage Vt is output, and a negative-phase sawtooth voltage is output during a period t1 to t4 in which the W-phase load current Iw is negative half-wave. A second sawtooth voltage Vtw that is a combination of the positive-phase sawtooth voltage and the negative-phase sawtooth voltage shown in FIG. 5C is input to the second comparator 54. As is apparent from FIGS. 5B and 5C, the intermediate position between the positive and negative peaks of the first and second voltage reference values Vru and Vrw and the first and second corrected sawtooth voltages Vtu, The respective levels are set so that the intermediate positions of the positive and negative peaks of Vtw coincide with each other.

  The first and second comparators 53 and 54 connected to the voltage reference value generator 51, the U-phase and W-phase correction circuits 56 and 57, and the main switch control signal forming circuit 55 are shown in FIG. ), The first and second voltage reference values Vru, Vrw are compared with the first and second corrected sawtooth voltages Vtu, Vtw, and the first and second voltage reference values Vru, Vtw shown in FIGS. 3 main switch control signals Vg1 and Vg3 are formed and sent to the main switch control signal forming circuit 55. The first and second comparators 53 and 54 have a high level, that is, a logic level when the first and second voltage reference values Vru and Vrw are larger than the first and second corrected sawtooth voltages Vtu and Vtw. 1 is output, and other than this, low level, that is, logic 0 is output.

  The main switch control signal forming circuit 55 receives the first and third main switch control signals Vg1 and Vg3 formed by the first and second comparators 53 and 54 via the lines 9 and 11 and the first switch shown in FIG. And second and fourth main switch control signals Vg2 and Vg4, which are made of opposite phase signals of the first and third main switch control signals Vg1 and Vg3, and are sent to the control terminals of the third main switches S1 and S3. Then, the signals are sent to the control terminals of the second and fourth main switches S2 and S4 in FIG. The main switch control signal forming circuit 55 includes a known dead time giving means. This dead time providing means prevents the first and second main switches S1, S2 from being turned on at the same time, and prevents the third and fourth main switches S3, S4 from being turned on at the same time. A period is provided.

The auxiliary switch control circuit 6 shown in FIG. 4 controls the first and second auxiliary switches Q1 and Q2 to be turned on and off so that the first to fourth main switches S1 to S4 can be soft-switched. Vta setting circuit 58 for setting voltage level Vta, Vtb setting circuit 59 for setting second voltage level Vtb, third and fourth comparators 60 and 61, exclusive OR circuit 62, and NOT circuit 63.
The sawtooth generator 52 can be included in the auxiliary switch control circuit 6.

The Vta setting circuit 58 sets the first voltage level Vta shown on the upper side of FIG. 6A and supplies it to the third comparator 60. The Vtb setting circuit 59 sets a second voltage level Vtb shown on the lower side of FIG. 6A and supplies it to the fourth comparator 61. The Vta setting circuit 58 and the Vtb setting circuit 59 include calculation means, and are based on the U-phase and W-phase load currents Iu and Iw of the lines 7 and 8 and the constants of the respective parts in FIG. The first and second voltage levels Vta and Vtb are determined so that the .about.t3 period Ta and the t3 to t6 period Tb have the optimum time length. At this time, the first and second voltage levels Vta and Vtb are determined in consideration of the amplitude of the sawtooth voltage Vt.
Since the first and second voltage levels Vta and Vtb determine the on / off timings of the first and second auxiliary switches Q1 and Q2, they can also be referred to as first and second timing signal command values. The first and second voltage levels Vta and Vtb can be set to constant values across the sawtooth voltage Vt. In this embodiment, the U-phase load current Iu and the W-phase load current Iw are changed. Switching is performed accordingly. For this purpose, the Vta setting circuit 58 and the Vtb setting circuit 59 are connected to the detection lines 7 and 8 for the U-phase and W-phase load currents Iu and Iw.

An example of an arithmetic expression for setting the first and second voltage levels Vta and Vtb by the Vta setting circuit 58 and the Vtb setting circuit 59 is shown below.
When Iu <0, Iw <0,
Vta = Vt.times. [1-{(2.times.Lr.times. (Iu '+ Iw')) / Vdc + .pi..sqroot. (Lr.times.C)} / T]
Vtb = Vt × [2 × Lr x {(Iu ′ + Iw ′)} / Vdc + π√ (Lr × C)] / T
When Iu <0, Iw> 0,
Vta = Vt * [1-{(2xLr x (Iu ')) / Vdc + π√ (Lr xC)} / T]
Vtb = Vt × [2 × Lr x {(Iu ′ + Iw ′)} / Vdc + π√ (Lr × C)] / T
When Iu> 0, Iw <0,
Vta = Vt * [1-{(2xLr x (Iw ')) / Vdc + π√ (Lr xC)} / T]
Vtb = Vt × [2 × Lr x {(Iw ′ + Iu ′)} / Vdc + π√ (Lr × C)] / T
When Iu> 0 and Iw> 0,
Vta = Vt × [1- {π√ (Lr × C)} / T]
Vtb = Vt × [2 × Lr x {(Iw ′ + Iu ′)} / Vdc + π√ (Lr × C)] / T
Where Vt is the sawtooth voltage in FIG.
Vdc is the maximum amplitude of the sawtooth voltage Vt,
T is the period of the sawtooth voltage Vt,
Lr is the inductor value of the resonant reactor Lr in FIG.
C is a capacity between the relay terminal 4 and the second DC terminal 2, that is, C1 + C4 or C2 + C3 or C1 + C3 or C2 + C4,
Iu 'and Iw' are absolute values of U-phase and W-phase load currents Iu and Iw.

  The third comparator 60 is connected to the Vta setting circuit 58 and the line 15, and compares the sawtooth voltage Vt of the line 15 connected to the sawtooth generator 52 with the first voltage level Vta. When the sawtooth voltage Vt is higher than the first voltage level Vta, the signal Pta shown in FIG. The first voltage level Vta is set to a value slightly lower than the maximum value of the sawtooth voltage Vt.

  The fourth comparator 61 is connected to the Vtb setting circuit 59 and the line 15, compares the sawtooth voltage Vt of the line 15 with the second voltage level Vtb, and the second voltage level Vtb is the sawtooth voltage Vt. When it is higher than that, the signal Ptb of FIG.

The exclusive OR circuit 62 is connected to the third and fourth comparators 60 and 61, and is high when the signals Pta and Ptb output from the third and fourth comparators 60 and 61 are at different voltage levels. A level signal is generated as shown in FIG. The output of the exclusive OR circuit 62 becomes a first auxiliary switch control signal Vq1 for controlling the first auxiliary switch Q1. A NOT circuit 63 connected to the exclusive OR circuit 62 inverts the phase of the output of the exclusive OR circuit 62 and a second auxiliary switch control signal for controlling the second auxiliary switch Q2 shown in FIG. 6 (D). Vq2 is output. The first and second auxiliary switch control signals Vq1, Vq2 are sent to the control terminals of the first and second auxiliary switches Q1, Q2 of FIG.
The third comparator 60 is modified so that the output of the third comparator 60 becomes a low level, that is, a logic 0 when the sawtooth voltage Vt is higher than the first voltage level Vta, and the exclusive OR is performed. The circuit 62 can be transformed into an AND gate. Further, another logic circuit equivalent to the exclusive OR circuit 62 can be provided.

Next, the operation of the circuit of FIG. 3 will be described with reference to the waveform diagram of FIG. 7 and the current path diagrams of FIGS. In the following description, the current path may be indicated only by reference numerals of circuit elements.
7, 8 and 9 show the states of the respective parts at the timing when the U-phase load current Iu is larger than zero, the V-phase load current Iv is zero, and the W-phase load current Iw is smaller than zero. Further, the time points t1, t3, and t6 in FIG. 7 indicate the same time points as the time points t1, t3, and t6 in FIG. 7 is a time sufficiently shorter than the period T of the sawtooth voltage Vt (for example, T / 20 to T / 10). Further, the current I _Lr in FIG. 7E indicates the current of the resonant reactor Lr. Further, the DC link voltage Vlink of FIG. 7 (F) is the series circuit of the first and second main switches S1, S2 or the series of the third and fourth main switches S3, S4 as shown in FIG. 8 (A). Indicates the voltage across the circuit. In FIG. 7G, Vs1 indicates a voltage between both terminals of the first main switch S1, and Is1 indicates a current flowing through the first main switch S1 and the first main diode D1. Vs1 is referred to as a first main switch voltage, and Is1 is referred to as a first main switch current.
8 and 9, a current path through which a current flows is indicated by a thick line, and a portion where the current does not substantially flow is indicated by a thin line. Further, the first and second DC terminals 1 and 2 are omitted in FIGS. Further, arrows indicating current directions and values indicating relative levels of current values are attached to the U-phase, V-phase, and W-phase AC terminals 3u, 3v, and 3w.

(Before t1)
Before the time t1 in FIG. 7, the first and fourth main switches S1 and S4 are turned off, the second and third main switches S2 and S3 are turned on, and the first auxiliary switch Q1 is turned on. The second auxiliary switch Q2 is off-controlled. Since the first and fourth main switches S1 and S4 are on during the period before the time t0 in FIG. 6, a positive U-phase load current Iu flows through the first reactor Lu, and the second reactor Lw. W-phase load current Iw flows in the negative direction, energy is accumulated in the first and second reactors Lu and Lw, and the first and second reactors are turned off during the off period of the first and fourth main switches S1 and S4. The stored energy of Lu and Lw is released, and a current flows through the path of Lu-3u-3w-Lw-D3-Da-Ca-Cb-D2. At this time, the voltage Vs1 between both terminals of the first main switch S1 is kept substantially at the power supply voltage Vdc as shown in FIG. The power supply voltage Vdc corresponds to the sum of the voltage between the first and second DC terminals 1 and 2 and the voltage of the first and second voltage dividing capacitors Ca and Cb. At this time, the DC link voltage Vlink in FIG. 7F is substantially the same as the power supply voltage Vdc.

(T1 to t2)
When the first auxiliary switch Q1 is turned off and the second auxiliary switch Q2 is turned on at time t1 in FIG. 7, in addition to the current path of FIG. 8A, Lu-3u-3w-Lw- D3 -Q2 -lR the path of -Cb -D2 current I _Lr in the resonant reactor Lr shown in FIG. 7 (E) starts to flow. This current I _Lr increases with time. That is, a part of the current flowing through the first auxiliary diode Da in FIG. 8A is commutated to the resonant reactor Lr, and the current of the first auxiliary diode Da is gradually decreased, and conversely, the current of the resonant reactor Lr. I _Lr gradually increases. Therefore, the turn-off of the first auxiliary switch Q1 is zero voltage switching (ZVS), and the turn-on of the second auxiliary switch Q2 is zero current switching (ZCS).

(T2 to t3)
When the current passing through the first auxiliary diode Da becomes zero at time t2 in FIG. 7, the current in the path of Lu-3u-3w-Lw-D3-Q2-Lr-Cb-D2 is the same as in FIG. In addition, a resonance current in the path C1-Q2-Lr-Cb-D2 and a resonance current in the path C4-D3-Q2-Lr-Cb flow, and the voltages of the first and fourth resonance capacitors C1, C4 The DC link voltage Vlink shown in FIG. 7 (F), the voltage Vs1 between both terminals of the first main switch S1 shown in FIG. 7 (G), and both terminals of the fourth main switch S4 not shown are gradually decreased. The voltage in between decreases gradually and becomes almost zero before time t3. The current I _Lr flowing through the resonant reactor Lr gradually decreases after a slight overshoot at time t2 in FIG.

(T3 to t4)
At time t3, the first and fourth main switches S1 and S4 are simultaneously turned on. As shown in FIGS. 5B and 5C, the first and fourth main switches S1 and S4 are simultaneously turned on and the second and third main switches S2 and S3 are simultaneously turned on. This is achieved by forming the second corrected sawtooth voltages Vtu and Vtw. The turn-on of the first and fourth main switches S1 and S4 at time t3 in FIG. 7 is zero voltage switching (ZVS). In addition, since the currents of the first and fourth main switches S1 and S4 increase with a slope from the time point t3, these turn-ons also become zero current switching (ZCS). When the first and fourth main switches S1 and S4 are turned on at time t3, the current of the path Lu-3u-3w-Lw-D3-S1, the current of the path Lu-3u-3w-Lw-S4-D2 flow, current I _Lr path Lu -3u-3w-Lw -D3 -Q2 -Lr -Cb -D2 decreases toward zero as shown in FIG. 7 (E).

(T4 to t5)
After the current I _Lr in the resonant reactor Lr becomes zero at the time t4 shown in FIG. 7 (E), the current I _Lr flows in the opposite direction. That is, the t4 t5 period, as shown in FIG. 8 (E), the current I _Lr path Lu -3u-3w-Lw -S4 -Cb -Lr -Db -S1, Lu -3u-3w- The current in the path Lw-D3-S1 and the current in the path Lu-3u-3w-Lw-S4-D2 flow. While the current I _Lr flowing in the reverse direction through the resonant reactor Lr is smaller than the current flowing through the third main diode D3, charging of the second and third resonance capacitors C2 and C3 does not start, and FIG. The DC link voltage Vlink is maintained at zero or almost zero.

(T5 to t6)
When the current I _Lr in the resonant reactor Lr in time t5 of FIG. 7 is greater than the current of the second and third main diodes D2, D3, now the second and third main diodes D2, D3 are turned off, Fig. 9 The second resonance capacitor C2 is charged through the path Lr-Db-S1-C2-Cb shown in FIG. 5A, and at the same time the third resonance capacitor C3 is charged through the path Lr-Db-C3-S4-Cb. Then, the DC link voltage Vlink in FIG. 7F gradually increases and becomes the power supply voltage Vdc before time t6.

(T6-t7)
Since the DC link voltage Vlink is the same or substantially the same as the power supply voltage Vdc at time t6 in FIG. 7, the voltage between both terminals of the first auxiliary switch Q1 is zero or almost zero. Therefore, when the first auxiliary switch Q1 is turned on at time t6 as shown in FIG. 7C, zero voltage switching (ZVS) is achieved. In this embodiment, in order to easily form the control signals Vq1 and Vq2 of the first and second auxiliary switches Q1 and Q2, the second auxiliary switch Q2 is turn-off controlled at time t6. However, since no current flows through the second auxiliary switch Q2 from the time point t4, the turn-off control can be performed at the time point t4 or later. The turn-off control of the second auxiliary switch Q2 is preferably performed during the period from t4 to t7 during which the second auxiliary diode Db flows for zero voltage switching (ZVS).
During the period from t6 to t7, a current flows through the path of Cb-Ca-Q1-S1-Lu-3u-3w-Lw-S4, and Lr-Db-S1-Lu-3u-3w-Lw-Sw-S4-Cb A current flows through the path, and the remaining energy of the resonant reactor Lr is regenerated to the load side.

(After t7)
When the release of the energy stored in the resonant reactor Lr is completed at time t7, the second auxiliary diode Db is in a reverse bias state, and Cb-Ca-Q1-S1-Lu-3u-3w-Lw- shown in FIG. Current flows through the path of S4.

The second and third main switches S2 and S3 are turned on in synchronization with the rise or fall of the sawtooth voltage Vt and the first and second corrected sawtooth voltages Vtu and Vtw, and the first and fourth main switches Before and after the switches S1 and S4 are turned off, operations similar to those shown in FIGS.
Further, even when the U-phase, V-phase, and W-phase load currents Iu, Iv, and Iw are different in magnitude from the states shown in FIGS. 7 to 9, substantially the same operations as in FIGS. 7 to 9 occur.
When the second and third main switches S2 and S3 are turned on after time t6 in FIG. 6, the route of Lu-3u-3w-Lw-C3-C1 and Lu-3u-3w-Lw- A current flows through the path C4-C2, the second and third resonance capacitors C2 and C3 are reversely charged or discharged, and the first and fourth resonance capacitors C1 and C4 are gradually charged. Thereafter, when the reverse bias state of the second and third main diodes D2 and D3 is released, a current flows through the path of Lu-3u-3w-Lw-D3-Da-Ca-Cb-D2. If the second and third main switches S2 and S3 are turned on while the second and third main diodes D2 and D3 are conducting, their turn-on is substantially ZVS. Further, when the first and fourth switches S1 and S4 are turned off when the voltages of the first and fourth resonance capacitors C1 and C4 are zero or close to each other, these turn-offs are substantially ZVS. .

The power conversion device of FIG. 3 has the following effects.
(1) Soft switching of the first to fourth main switches S1 to S4 can be achieved with a relatively simple circuit, and surge, noise, and switching loss can be reduced.
(2) Soft switching of the first and second auxiliary switches Q1, Q2 is also achieved.
(3) Since the inverter circuit has a V-connection configuration, the number of main switches can be reduced as compared with the power converter of Patent Document 1, and the power converter can be reduced in size and cost. .

However, in the power conversion device according to the patent application, as shown in FIG. _7E , the positive half wave and the negative half wave of the current I _Lr flowing through the resonant reactor Lr are not the same, and the resonance current is DC. Is superimposed. This caused an imbalance in the intermediate voltage, that is, a mismatch between the voltages of the terminals of the first and second voltage dividing capacitors Ca and Cb. Note that if a current having a direct current component flows through the transformer in the output stage of the inverter, there is a risk that the transformer will be saturated.
JP 2000-262066 A

  Therefore, the problem to be solved by the present invention is that the voltage between the terminals of the first and second voltage dividing capacitors does not match in the power converter having the soft switching circuit.

Next, the present invention will be described with reference to the reference numerals of the drawings. However, the claims and the reference numerals used here are for helping the understanding of the present invention, and do not limit the present invention.
The present invention for solving the above-described problems includes first and second DC terminals (1, 2),
First, second and third phase AC terminals (3u, 3v, 3w);
A relay terminal (4);
A series circuit of first and second boost conversion switches (Sp, Sn) connected between the relay terminal (4) and the second DC terminal (2);
A step-up conversion reactor (Lin) connected between the first or second DC terminal (1, 2) and the second step-up conversion switch (Sn);
Individual or parasitic first and second boost conversion diodes (D11, D12) connected in parallel to the first and second boost conversion switches (Sp, Sn), respectively;
Individual or parasitic first and second snubber capacitors (C11, C12) connected in parallel to the first and second boost conversion switches (Sp, Sn), respectively;
A first voltage dividing capacitor (Ca) connected between the relay terminal (4) and the second phase AC terminal (3v) via a first auxiliary switch (Q1);
A second voltage dividing capacitor (Cb) connected between the second phase AC terminal (3v) and the second DC terminal (2);
A first main switch (S1) connected between the relay terminal (4) and the first phase AC terminal (3u);
A second main switch (S2) connected between the first phase AC terminal (3u) and the second DC terminal (2);
A third main switch (S3) connected between the relay terminal (4) and the third phase AC terminal (3w);
A fourth main switch (S4) connected between the third phase AC terminal (3w) and the second DC terminal (2);
Individual or parasitic first, second, third and fourth resonance capacitors connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. (C1, C2, C3, C4) and
An individual or parasitic first auxiliary diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A series circuit of a second auxiliary switch (Q2) and a resonant reactor (Lr) connected between the relay terminal (4) and the second phase AC terminal (3v);
An individual or parasitic second auxiliary diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
The first, second, third, and fourth so that a three-phase AC voltage (Vuv, Vvw, Vwu) can be obtained at the first, second, and third phase AC terminals (3u, 3v, 3w). A main switch control circuit (5) for controlling on / off of the main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage;
The voltages of the first, second, third and fourth resonance capacitors (C1, C2, C3, C4) are changed to the first, second, third and fourth main switches (S1, S2, S3, An auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the turn-on time of S4);
On / off control of the second boost conversion switch (Sn) at a frequency higher than the frequency of the three-phase AC voltage to boost the voltage between the first and second DC terminals (1, 2). And a step-up conversion switch that controls on / off of the first step-up conversion switch (Sp) so as to reduce the difference between the value of the forward current flowing in the resonant reactor (Lr) and the value of the reverse current. The present invention relates to a power converter characterized by having a control circuit (31).

In addition, as shown in Claims 2, 3, 5 and 7, the first and second values can be reduced so as to reduce the difference between the value of the forward current flowing in the resonant reactor (Lr) and the value of the reverse current. The main switch (S1, S2), the third and fourth main switches (S3, S4) or the first to fourth main switches (S1 to S4) can be simultaneously turned on.
Moreover, as shown in claim 3, the power converter is
First and second DC terminals (1, 2);
First, second and third phase AC terminals (3u, 3v, 3w);
A relay terminal (4);
A first voltage dividing capacitor (Ca) connected between the first DC terminal (1) and the second phase AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second DC terminal (2) and the second phase AC terminal (3v);
A first main switch (S1) connected between the relay terminal (4) and the first phase AC terminal (3u);
A second main switch (S2) connected between the first phase AC terminal (3u) and the second DC terminal (2);
A third main switch (S3) connected between the relay terminal (4) and the third phase AC terminal (3w);
A fourth main switch (S4) connected between the third phase AC terminal (3w) and the second DC terminal (2);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) connected between the first DC terminal (1) and the relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A series circuit of a second auxiliary switch (Q2) and a resonant reactor (Lr) connected between the relay terminal (4) and the second phase AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
The first, second, third, and fourth so that a three-phase AC voltage (Vuv, Vvw, Vwu) can be obtained at the first, second, and third phase AC terminals (3u, 3v, 3w). A main switch control circuit (5 or 5a) for controlling on / off of the main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage;
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the time of turn-on. Can be configured.
Moreover, as shown in claim 4, the power converter is
At least first and second input AC terminals (1r, 1t);
First, second and third phase output AC terminals (3u, 3v, 3w);
First and second relay terminals (4, 4a);
A first main switch (S1) connected between the first relay terminal (4) and the first phase output AC terminal (3u);
A second main switch (S2) connected between the first phase output AC terminal (3u) and the second relay terminal (4a);
A third main switch (S3) connected between the first relay terminal (4) and the third phase output AC terminal (3w);
A fourth main switch (S4) connected between the third phase output AC terminal (3w) and the second relay terminal (4a);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) having one end connected to the first relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A first voltage dividing capacitor (Ca) connected between the other end of the first auxiliary switch (Q1) and the second phase output AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second phase output AC terminal (3v) and the second relay terminal (4a);
A series circuit of a second auxiliary switch (Q2) and a resonance reactor (Lr) connected between the first relay terminal (4) and the second phase output AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
A first conversion switch (Q11) connected between the first input AC terminal (1r) and the first relay terminal (4), the first input AC terminal (1r) and the first A second conversion switch (Q12) connected between the second relay terminal (4a) and the second input AC terminal (1t) and the first relay terminal (4). And a third conversion switch (Q13) and a fourth conversion switch (Q14) connected between the second input AC terminal (1t) and the second relay terminal (4a). An AC-DC conversion circuit (30b);
The first, second, third and third phase AC voltages (Vuv, Vvw, Vwu) can be obtained at the first, second and third phase output AC terminals (3u, 3v, 3w). A main switch control circuit (5 or 5a) for controlling on / off of the four main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage;
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the time of turn-on. ,
A function of controlling the first, second, third and fourth conversion switches (Q11, Q12, Q13, Q14) so as to obtain a DC output voltage from the AC-DC conversion circuit (30b); The first and second conversion switches (Q11, Q12) or the third and fourth conversions so as to reduce the difference between the value of the forward current and the value of the reverse current flowing through the resonant reactor (Lr). And a conversion switch control circuit (31b) having a function of simultaneously turning on the switches (Q13, Q14) or the first to fourth conversion switches (Q11 to Q14).
Further, as shown in claim 5, in the fourth aspect, the first to fourth conversions are performed so as to reduce the difference between the value of the forward current flowing in the resonant reactor (Lr) and the value of the backward current. Instead of controlling the switches (Q11 to Q14), the first and second main switches (S1, S2) or the third and fourth main switches (S3, S4) or the first to fourth main switches The switches (S1 to S4) can be simultaneously turned on.
Moreover, as shown in claim 6, the power conversion device is
First, second and third phase input AC terminals (1r, 1s, 1t);
First, second and third phase output AC terminals (3u, 3v, 3w);
First and second relay terminals (4, 4a);
A first main switch (S1) connected between the first relay terminal (4) and the first phase output AC terminal (3u);
A second main switch (S2) connected between the first phase output AC terminal (3u) and the second relay terminal (4a);
A third main switch (S3) connected between the first relay terminal (4) and the third phase output AC terminal (3w);
A fourth main switch (S4) connected between the third phase output AC terminal (3w) and the second relay terminal (4a);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) having one end connected to the first relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A first voltage dividing capacitor (Ca) connected between the other end of the first auxiliary switch (Q1) and the second phase output AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second phase output AC terminal (3v) and the second relay terminal (4a);
A series circuit of a second auxiliary switch (Q2) and a resonance reactor (Lr) connected between the first relay terminal (4) and the second phase output AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
AC-DC converter circuit (30b) connected between the first, second and third phase input AC terminals (1r, 1s, 1t) and the first and second relay terminals (4, 4a). When,
The first, second, third and third phase AC voltages (Vuv, Vvw, Vwu) can be obtained at the first, second and third phase output AC terminals (3u, 3v, 3w). A main switch control circuit (5 or 5a) for controlling on / off of four main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the time of turn-on. ,
An AC-DC conversion control circuit (31b) for controlling the AC-DC conversion circuit (30b), and the AC-DC conversion circuit (30b) is connected to the first and second relay terminals (4). 4a) a first series circuit of first and second conversion switches (Q11, Q12) and a second series circuit of third and fourth conversion switches (Q13, Q14) connected between , First, second, third and fourth snubber capacitors or parasitics connected in parallel to the first, second, third and fourth conversion switches (Q11, Q12, Q13, Q14), respectively. Capacitors (C11, C12, C13, C14), the first phase input AC terminal (1r) and the first connection point between the first and second conversion switches (Q11, Q12). 1 input reactor (L11), the third phase input AC terminal (1t), the third and the third And a second input reactor (L12) connected between the mutual connection points of the conversion switches (Q13, Q14), and the second phase input AC terminal (1s) is the first and second Can be connected to the interconnection point of the dividing capacitors (Ca, Cb). The AC-DC conversion control circuit (31b) of the power converter is configured to convert the first, second, third, and fourth conversion switches (Q11, Q12, Q13, In addition to the function of controlling Q14), the first and second conversion switches (Q11, Q11, Q2) are used to reduce the difference between the value of the forward current and the value of the reverse current flowing through the resonant reactor (Lr). Q12) or the third and fourth conversion switches (Q13, Q14) or the first to fourth conversion switches (Q11 to Q14) are preferably turned on simultaneously.
Further, as shown in claim 7, in order to reduce the difference between the value of the forward current flowing in the resonant reactor (Lr) and the value of the reverse current, the first to fourth conversion elements in claim 6 are used. Instead of turning on the switches (Q11 to Q14), the first and second main switches (S1, S2) or the third and fourth main switches (S3, S4) or the first to fourth switches The main switches (S1 to S4) can be simultaneously turned on.
Further, as shown in claim 8, a first filter reactor (Lu) connected between the first and second main switches (S1, S2) and the first phase AC terminal (3u). And a second filter reactor (Lw) connected between the third and fourth main switches (S3, S4) and the third-phase AC terminal (3w). desirable.
According to a ninth aspect of the present invention, each of the first, second, third and fourth main switches (S1, S2, S3, S4) connected in parallel in the reverse direction is further provided. It is desirable to have first, second, third and fourth main diodes (D1, D2, D3, D4).
Further, as shown in claim 10, the auxiliary switch control circuit (6) is a little before the turn-on time (t3) of at least one of the first to fourth main switches (S1 to S4). From the first time point (t1) to the second time point (t6) a little later than the turn-on time point (t3), the first auxiliary switch (Q1) is controlled to be in the OFF state and the second auxiliary switch ( Q2) is controlled to be in an ON state, and a first time length (Ta) from the first time point (t1) to the turn-on time point (t3) is determined by the action of the resonance reactor (Lr). By the time, the voltage between the relay terminal (4) and the second DC terminal (2) or between the first relay terminal (4) and the second relay terminal (4a) is reduced to zero or The time length can be almost zero. When the second time length (Tb) from the turn-on time (t3) to the second time (t6) is set to the second time (t6) by the action of the resonance reactor (Lr), the first auxiliary switch It is desirable that the time length is such that the voltage of (Q1) can be zero or almost zero.
As shown in claim 11, the step-up conversion switch control circuit (31) according to claim 1 measures a desired time in synchronization with the turn-on of the second auxiliary switch (Q2), and the desired time ( It is desirable to have a timer (47) for turning on the first step-up conversion switch (Sp) by Tc).
According to a twelfth aspect of the present invention, the step-up conversion switch control circuit (31) according to the eleventh aspect reduces the difference in voltage between the first and second voltage dividing capacitors (Ca, Cb). It is desirable to have means for controlling the length of the desired time (Tc) measured by the timer (47).
According to a thirteenth aspect of the present invention, the main switch control circuit (5 or 5a) according to the second, third, fifth or seventh aspect includes the first, second, third and fourth main switches (S1, S1). It is desirable to have means for selectively extending the on period of S2, S3, S4).

According to the invention of each claim, the following effects can be obtained.
(1) By connecting the first and second auxiliary switches Q1, Q2 and the first and second auxiliary diodes Da, Db and the resonant reactor Lr to the states specified in the present invention, the first to fourth main switches The electrical stress of the switches S1 to S4 can be reduced, and switching surge, switching noise, and switching loss can be reduced.
(2) First and second step-up conversion switches Sp and Sn or first and second main switches S1, S2 or third and fourth main switches S3, S4 or first and second conversion switches By simultaneously turning on Q11 and Q12 or the third and fourth conversion switches Q13 and Q14, the current of the resonant reactor can be adjusted, and the balance between the positive and negative currents of the resonant reactor and the The balance between the terminals of the first and second voltage dividing capacitors can be easily improved.

  Next, an embodiment of the present invention will be described with reference to FIGS.

The power converter of Example 1 shown in FIG. 10 includes a boost converter 30 as a DC-DC converter and a switch control circuit 31 for boost converter for the power converter shown in FIG. 3 is formed identically. Therefore, in FIG. 10, substantially the same parts as in FIG.
The step-up conversion circuit 30 includes a step-up conversion reactor Lin, first and second step-up conversion switches Sp and Sn including semiconductor switches such as IGBTs, first and second step-up conversion diodes D11 and D12, The first and second snubber capacitors C11 and C12 are provided. A series circuit of the first and second boost conversion switches Sp and Sn is connected between the relay terminal 4 and the second DC terminal 2. Since the first and second step-up conversion switches Sp and Sn are also used to improve the balance between the positive direction current and the negative direction current of the resonant reactor Lr, they are used as the third and fourth auxiliary switches. Can also be called. The first and second boost conversion diodes D11 and D12 have a direction to be reverse-biased by the voltages of the first and second voltage dividing capacitors Ca and Cb, and have the first and second boost conversion diodes. These are individual diodes connected in reverse parallel to the switches Sp and Sn or parasitic or built-in diodes of the first and second boost conversion switches Sp and Sn. The first and second snubber capacitors C11 and C12 are individual capacitors connected in parallel to the first and second boost conversion switches SP and Sn, or parasitics of the first and second boost conversion switches Sp and Sn. The capacitance is sufficiently smaller than the first and second voltage dividing capacitors Ca and Cb.
One end of the boost conversion reactor Lin is connected to the first DC terminal 1, and the other end is connected to an interconnection point of the first and second conversion switches Sp and Sn.

  The step-up conversion switch control circuit 31 is connected to the control terminals of the first and second step-up conversion switches Sp and Sn by lines 32 and 33, and turns on and off the first and second step-up conversion switches Sp and Sn. First and second boost conversion switch control signals Vsp and Vsn for control are formed. The step-up conversion switch control circuit 31 has a function to improve the positive / negative balance of the current of the resonance reactor Lr, in addition to the function of turning on / off the second step-up conversion switch Sn for step-up conversion. It also has a function of controlling on / off of one step-up conversion switch Sp. The step-up conversion switch control circuit 31 is connected to the sawtooth generator 52 of the main switch control circuit 5, and performs turn-on control of the first step-up conversion switch Sp in synchronization with the turn-on of the first main switch S1. Therefore, the electric charge of the first snubber capacitor C11 is released by the resonance operation before the turn-on time of the first boost conversion switch Sp, and zero voltage switching (ZVS) of the first boost conversion switch Sp is achieved. . The second step-up conversion switch Sn is turn-on controlled in synchronization with the first and fourth main switches S1, S4 or the second and third main switches S2, S3, and the first to fourth main switches Zero voltage switching (ZVS) is performed as in S to S4. The first and second snubber capacitors C11 and C12 also contribute to soft switching when the first and second boost conversion switches Sp and Sn are turned off.

A voltage detection circuit 40 is provided to configure a feedback control circuit for stabilizing the DC voltage between the relay terminal 4 and the second DC terminal 2. The voltage detection circuit 40 is connected to the relay terminal 4 and the second DC terminal 2, and sends a voltage detection signal indicating a DC voltage between them to the boost conversion switch control circuit 31 via the line 41.
In order to turn on the first step-up conversion switch Sp in synchronization with the second auxiliary switch Q2, the step-up conversion switch control circuit 31 is connected to the transmission line 14 of the second auxiliary switch control signal Vq2 by the line 43. Has been. In order to turn on the second step-up conversion switch Sn in synchronization with the on / off of the first to fourth main switches S1 to S4, the step-up conversion switch control circuit 31 is connected to the main switch control circuit by the line 42. 5 is connected.

  FIG. 11 shows details of the main switch control circuit 5, the auxiliary switch control circuit 6, and the step-up conversion switch control circuit 31. In FIG. 11, parts that are substantially the same as those in FIG.

  The main switch control circuit 5 and the auxiliary switch control circuit 6 in FIG. 11 are formed in the same manner as in FIG. The step-up conversion switch control circuit 31 includes a reference voltage source 44, an error amplifier 45, a comparator 46, and a timer 47.

  One input terminal of the error amplifier 45 is connected to the voltage detection circuit 40 of FIG. 10 by a line 41, and the other input terminal is connected to the reference voltage source 44. Therefore, the error amplifier 45 outputs a feedback control signal Vf indicating the difference between the detected voltage of the line 41 and the reference voltage of the reference voltage source 44 as shown in FIG. One input terminal of the comparator 46 is connected to the error amplifier 45, and the other input terminal is connected to the sawtooth generator 52 by a line 42. Accordingly, the comparator 46 compares the sawtooth voltage Vt and the feedback control signal Vf as shown in FIG. 12C to form the control signal Vsn shown in FIG. 10 is sent to the control terminal of the second step-up conversion switch Sn. As is well known, energy is stored in the boost conversion reactor Lin during the ON period of the second boost conversion switch Sn, and the stored energy of the boost conversion reactor Lin is released during the OFF period of the second boost conversion switch Sn. Then, the voltage of the step-up conversion reactor Lin is added to the voltage between the first and second DC terminals 1 and 2 and output.

The timer 47 can also be called a first step-up conversion switch control signal forming circuit, and is synchronized with the second auxiliary switch control signal Vq2 shown in FIGS. 12 (K) and 13 (D). A first boost conversion switch control signal Vsp shown in FIG. 12 (L) and FIG. 13 (E) is formed and sent to the control terminal of the first boost conversion switch Sp of FIG. That is, the timer 47 is triggered at the rise time t1 of the second auxiliary switch control signal Vq2 shown in FIG. 13D and measures the time Tc shown in FIG. 13E, and has a duration of this time Tc. Output a pulse. This pulse is used to turn on the first step-up conversion switch Sp. Since the first boost conversion switch Sp is connected in parallel to the first boost conversion diode D11 essential in the boost conversion circuit 30, it is referred to as a boost conversion switch here for convenience of explanation. Since it mainly contributes to improving the positive / negative balance of the current of the resonant reactor Lr, it can also be called a current balance improving switch or a third auxiliary switch. As shown in FIG. 7E, in the conventional circuit, since the negative direction current of the resonant reactor Lr is smaller than the positive direction current, increasing the negative direction current improves the current balance. Therefore, it is only necessary to turn on the first step-up conversion switch Sp only during a period in which a negative direction current can flow through the resonance reactor Lr. However, in this embodiment, in order to simplify the control circuit of the first step-up conversion switch Sp and to achieve this soft switching, the second auxiliary switch control signal Vq2 shown in FIG. 13 (D) is turned on. In synchronization with the time t1, the first step-up conversion switch control signal Vsp is turn-on controlled as shown in FIG. 13 (E). The time Tc indicating the continuation of the on-control of the first step-up conversion switch control signal Vsp is determined so that a negative current can flow through the resonance reactor Lr, and ends at the time t5. Incidentally, the time Tc, taking into account the circuit constant of each part of the path of the current through the resonant inductor Lr, the magnitude and the negative direction component of the positive component of the current I _Lr in the resonant reactor Lr shown in FIG. 13 (G) It is determined so that the difference from the size can be minimized. As apparent from FIGS. 13E and 13F, the first and second step-up conversion switch control signals Vsp and Vsn have periods t3 to t5 which are turned on simultaneously. This produces a path to flow a negative current in the resonant reactor Lr, resonant positive and negative balance of current I _Lr of reactor Lr is improved, the first and second voltage dividing capacitor Ca, the voltage balance of Cb improved The

  Next, operations of the inverter circuit, the soft switching circuit, and the boost converter circuit 30 of FIG. 10 will be described with reference to the waveform diagrams of FIGS. 12 and 13 and the current path diagrams of FIGS. In the following description, the current path may be indicated only by reference numerals of circuit elements.

12, FIG. 13 and FIGS. 14 to 16 show a state in the vicinity of 300 degrees of the U-phase load current Iu composed of a sine wave. Also, the time points t1 to t8 in FIG. 12 indicate the same time points as the time points t1 to t8 in FIG. Therefore, t1 to t8 in FIG. 13 are sufficiently shorter than the period T of the sawtooth voltage Vt shown in FIG. 12C (for example, T / 20 to T / 10). Further, as shown in FIG. 14A, the DC link voltage Vlink in FIG. 13H is a series circuit of the first and second main switches S1, S2 or a series of the third and fourth main switches S3, S4. Indicates the voltage across the circuit. In FIG. 13I, Vs3 indicates a voltage between both terminals of the third main switch S3, and Is3 indicates a current flowing through the third main switch S3 and the third main diode D3. Vs3 is referred to as a third main switch voltage, and Is3 is referred to as a third main switch current.
14 to 16, a current path through which a current flows is indicated by a thick line, and a portion where the current does not substantially flow is indicated by a line thinner than the thick line. Moreover, the arrow which shows an electric current direction is attached | subjected to the 1st and 2nd DC terminals 1 and 2, U phase, V phase, and W phase AC terminals 3u, 3v, and 3w.

  The operation of the inverter circuit composed of the first to fourth main switches S1 to S4 in FIG. 10, the operation of the soft switching circuit composed of the first and second auxiliary switches Q1, Q2 and the resonant reactor Lr, and the main switch control circuit The operation of No. 5 and the operation of the auxiliary switch control circuit 6 are the same as the operations of the portions corresponding to these in FIG. 3, and thus detailed description thereof will be omitted.

  Inputs of the first and second comparators 53 and 54 which are omitted in FIG. 6 are shown in FIGS. As shown in FIG. 12A, the first comparator 53 compares the first corrected sawtooth voltage Vtu with the first voltage reference value Vru to compare the first main switch control shown in FIG. A signal Vg1 is formed. The second main switch control signal Vg2 in FIG. 12E is a phase inversion signal of the first main switch control signal Vg1. The second comparator 54 compares the second corrected sawtooth voltage Vtw and the second voltage reference value Vrw as shown in FIG. 12B, and performs the third main switch control shown in FIG. Signal Vg3 is formed. The fourth main switch control signal Vg4 in FIG. 12G is a phase inversion signal of the third main switch control signal Vg3.

  12 (C), (H), (I), (J), and (K) relating to the auxiliary switch control circuit 6 are the same as those in FIGS. 6 (A), (B), (C), (D), and (E). However, the feedback control signal Vf for forming the second step-up conversion switch control signal Vsn of FIG. 12 (M) is added to FIG. 12 (C). FIGS. 12L and 12M show the same first and second boost conversion switch control signals Vsp and Vsn as in FIGS. 13E and 13F.

(Before t1)
The operation shown in FIG. 14A occurs before the time t1. That is, before the time t1 in FIG. 13, the first and fourth main switches S1 and S4 are turned on, the second and third main switches S2 and S3 are turned off, and the first auxiliary switch Q1 is turned on. The control and second auxiliary switch Q2 are off-controlled. Since the second and third main switches S2 and S3 are on during the period before the time t0 in FIG. 12, the positive W-phase load current Iw flows through the second reactor Lw, and the first reactor Lu Negative direction U-phase load current Iu flows, energy is accumulated in the first and second reactors Lu and Lw, and the first and second main switches S2 and S3 are turned off thereafter. The reactors Lu and Lw are released, and current flows through the path Lw-3w-3u-Lu-D1-Da-Ca-Cb-D4 and the path Lw-3w-3v-Cb-D4. At this time, the voltage Vs3 between both terminals of the third main switch S3 is kept substantially at the power supply voltage Vdc as shown in FIG. Since the power supply voltage Vdc corresponds to the sum of the voltages of the first and second voltage dividing capacitors Ca and Cb, the DC link voltage Vlink in FIG. 13 (H) is substantially the same as the power supply voltage Vdc. Since the second step-up conversion switch Sn is off during the period before the time t1, a current path of 1-Lin-D11-Da-Ca-Cb-2 is also formed.

(T1 to t2)
The operation shown in FIG. 14B occurs during the period from t1 to t2. That is, when the first auxiliary switch Q1 is turned off and the second auxiliary switch Q2 is turned on at time t1 in FIG. 13, in addition to the current path of FIG. 14A, Lw-3w-3u- The current I _{Lr of the} resonant reactor Lr shown in FIG. This current I _Lr increases with time. That is, a part of the current flowing through the first auxiliary diode Da in FIG. 14A is commutated to the resonant reactor Lr, and the current of the first auxiliary diode Da is gradually decreased, and conversely, the current of the resonant reactor Lr. I _Lr gradually increases. Therefore, the turn-off of the first auxiliary switch Q1 is zero voltage switching (ZVS), and the turn-on of the second auxiliary switch Q2 is zero current switching (ZCS).

(T2 to t3)
In the period from t2 to t3, the operation shown in FIG. That is, when the current passing through the first auxiliary diode Da becomes zero at the time t2 in FIG. 13, in addition to the current path in FIG. 14B, the resonance current and C2 in the path C3-Q2-Lr-Cb-D4 are added. -D1-Q2-Lr-Cb path resonance current and C12-D11-Q2-Lr-Db path resonance current flow, the second and third resonance capacitors C3, C2 and the second snubber capacitor The voltage of C12 gradually decreases, the DC link voltage Vlink shown in FIG. 13 (H), the voltage Vs3 between the terminals of the third main switch S3 shown in FIG. 13 (I), and the second main switch (not shown). The voltage between both terminals of S2 and the second step-up conversion switch Sn also gradually decreases and becomes almost zero before the time t3. The current I _Lr flowing through the resonant reactor Lr gradually decreases after a slight overshoot at time t2 in FIG.

(T3 to t4)
The operation shown in FIG. 15A occurs during the period from t3 to t4. That is, at time t3, the second and third main switches S2, S3 and the second boost conversion switch Sn are simultaneously turned on. The simultaneous ON control of the second and third main switches S2, S3 and the second step-up conversion switch Sn is synchronized with each other by the first and second correction saws shown in FIGS. This is achieved by using the wave voltages Vtu and Vtw and the sawtooth voltage Vt of FIG. The turn-on of the second and third main switches S2, S3 and the second boost conversion switch Sn at time t3 in FIG. 13 is zero voltage switching (ZVS). Further, since the currents of the second and third main switches S2, S3 and the second step-up conversion switch Sn increase with a slope from the time point t3, these turn-ons are also applied to zero current switching (ZCS). Become. When the second and third main switches S2, S3 and the second step-up conversion switch Sn are turned on at time t3, the current in the path Lw-3w-3u-Lu-D1-S3, Lw-3w-3u- A current in the path Lu-S2-D4, a current in the path Lr-Cb-Sn-D11-Q2, and a current in the path 1-Lin-Sn-2 flow. Note that the current I _Lr of the resonant reactor Lr decreases toward zero as shown in FIG.

(T4 to t5)
The operation shown in FIG. 15B occurs during the period from t4 to t5. That is, after the current I _Lr in the resonant reactor Lr becomes zero at the time t4 in FIG. 13 (G), the current I _Lr flows in the opposite direction. During the period from t4 to t5, as shown in FIG. 15B, the current in the path of Lw-3w-3u-Lu-S2-Cb-Lr-Db-S3 and Lw-3w-3v-Lr-Db -S3 path current, Lw-3w-3u-Lu-D1-S3 path current, Lw-3w-3u-Lu-S2-D4 path current, and Lr-Db-Sp-Sn- The current balance improvement current according to the present invention in the path Cb and the current in the path 1-Lin-Sn-2 flow. While the current I _Lr flowing in the reverse direction through the resonant reactor Lr is smaller than the current flowing through the first and fourth main diodes D1 and D4, charging of the first and fourth resonance capacitors C1 and C4 does not start. The DC link voltage Vlink in FIG. 13H is kept at zero or almost zero.

(T5 to t6)
In the period from t5 to t6, the operation shown in FIG. That is, when the current I _Lr of the resonant reactor Lr becomes larger than the currents of the first and fourth main diodes D1 and D4 at time t5 in FIG. 13, the first and fourth main diodes D1 and D4 are turned off. The fourth resonance capacitor C4 is charged through the path Lr-Db-S3-C4-Cb shown in FIG. 16A, and at the same time, the first resonance capacitor C1 through the path Lr-Db-C1-S2-Cb. Is further charged, and the first snubber capacitor C11 is charged through the path of Lr-Db-C11-Sn-Cb, and the DC link voltage Vlink in FIG. The voltage becomes Vdc. In the period from t5 to t6, the same current as in the period from t4 to t5 flows through the portions other than the first and fourth resonance capacitors C1 and C4 and the first snubber capacitor C11.

(T6-t7)
The operation shown in FIG. 16B occurs in the period from t6 to t7. That is, since the DC link voltage Vlink is the same or substantially the same as the power supply voltage Vdc at time t6 in FIG. 13, the voltage between both terminals of the first auxiliary switch Q1 is zero or almost zero. Therefore, when the first auxiliary switch Q1 is turned on at time t6 as shown in FIG. 13C, zero voltage switching (ZVS) is achieved. In this embodiment, the second auxiliary switch Q2 is turned off at time t6 in order to easily form the control signals Vq1 and Vq2 of the first and second auxiliary switches Q1 and Q2. However, since no current flows through the second auxiliary switch Q2 from the time point t4, the turn-off control can be performed at the time point t4 or later. The turn-off control of the second auxiliary switch Q2 is preferably performed during the period from t4 to t7 during which the second auxiliary diode Db flows in order to achieve zero voltage switching (ZVS).
During the period from t6 to t7, current flows through the path of Cb-Ca-Q1-S3-Lw-3w-3u-Lu-S2, and Lr-Db-S3-Lw-3w-3u-Lu-S2-Cb A current flows through the path, and the remaining energy of the resonant reactor Lr is regenerated to the load side. During the period from t6 to t7, a current also flows through the 1-Lin-Sn-2 path, and energy is stored in the boost conversion reactor Lin.

(After t7)
In the period after t7, the operation shown in FIG. That is, when the discharge of the stored energy of the resonant reactor Lr is completed at the time t7, the second auxiliary diode Db is in a reverse bias state, and a current flows through the path of Cb-Ca-Q1-S3-Lw-3w-3u-Lu-S2. Flows. In the period after t7, a current also flows through the 1-Lin-Sn-2 path, and energy is stored in the boost conversion reactor Lin.

The first and fourth main switches S1 and S4 are turned on in synchronization with the rise or fall of the sawtooth voltage Vt and the first and second corrected sawtooth voltages Vtu and Vtw, and the second and third main switches Before and after the switches S2 and S3 are turn-off controlled, the same operation as in FIGS. 13 to 16 occurs except for the difference in the current path.
Further, even when the magnitude relationship between the U-phase, V-phase, and W-phase load currents Iu, Iv, and Iw is different from the states shown in FIGS. 13 to 16, substantially the same operation as that shown in FIGS.
When the first and fourth main switches S1 and S4 are turned on at time t9 in FIG. 12, the path of Lw-3w-3u-Lu-C1-C3 and the path of Lw-3w-3u-Lu-C2-C4 A current flows through the path, the first and fourth resonance capacitors C1 and C2 are reversely charged, that is, discharged, and the second and third resonance capacitors C2 and C3 are gradually charged. Thereafter, when the reverse bias state of the first and fourth main diodes D1 and D4 is released, the path of Lw-3w-3u-Lu-D1-Da-Ca-Cb-D4 and Lw-3w- A current flows through the path of 3v-Cb-D4. If the first and fourth main switches S1 and S4 are turned on while the first and fourth main diodes D1 and D4 are conducting, their turn-on is substantially ZVS. If the second and third switches S2 and S3 are turned off when the voltages of the second and third resonance capacitors C2 and C3 are zero or close to each other, these turn-offs are substantially ZVS. .

According to the first embodiment, the following effects can be obtained.
(1) Soft switching of the first to fourth main switches S1 to S4 can be achieved with a relatively simple circuit, and surge, noise, and switching loss can be reduced.
(2) Soft switching of the first and second auxiliary switches Q1, Q2 and the first and second boost conversion switches Sp, Sn is also achieved.
(3) Since the inverter circuit has a V-connection configuration, the number of main switches can be reduced as compared with the power converter of Patent Document 1, and the power converter can be reduced in size and cost. .
(4) Periods t3 to t5 in which the first and second boost conversion switches Sp and Sn are simultaneously turned on are provided, and the value of the negative direction current of the resonant reactor Lr is adjusted by adjusting the length of this period. The balance between the positive current value and the negative current value can be improved. As a result, the voltage balance of the first and second voltage dividing capacitors Ca and Cb is also improved.
(5) Since the positive / negative balance improvement of the current I _Lr of the resonant reactor Lr is executed using a part of the boost converter circuit 30, the balance improvement can be executed with a simple circuit.
(6) The series circuit of the first and second boost conversion switches Sp and Sn of the boost conversion circuit 30 is the series circuit of the first and second main switches S1 and S2 of the inverter circuit and the third and fourth main switches. Since it is the same configuration as the series circuit of the switches S3 and S4 and these can be integrated, the configuration can be simplified and the cost can be reduced. That is, using a three-phase arm structure of six switches made of an existing IGBT or the like, a series circuit of the first and second main switches S1 and S2 and a series of the third and fourth main switches S3 and S4. A series circuit of the circuit and the first and second boost conversion switches Sp and Sn can be formed.
(7) Since the first and second voltage dividing capacitors Ca and Cb can be used for both voltage division for V-connection and soft switching, the circuit configuration is simplified.

Next, the power converter of Example 2 is demonstrated with reference to FIGS. However, in FIGS. 17-19, the same code | symbol is attached | subjected to the part substantially the same as FIGS. 10-16, and the description is abbreviate | omitted.
The power conversion device of FIG. 17 is provided with a modified boost conversion circuit 30a, a boost conversion switch control circuit 31a, and a main switch control circuit 5a, and the other configuration is the same as that of FIG.

  The boost converter circuit 30a shown in FIG. 17 constitutes a DC-DC converter circuit, and the first boost converter switch Sp and the first snubber capacitor C11 are omitted from the boost converter circuit 30 shown in FIG. It corresponds to. The step-up conversion switch control circuit 31a has the same configuration as the step-up conversion switch control circuit 31 of FIG. 11 except that the timer 47 shown in FIG. 11 is omitted.

In Example 2 of FIG. 17, in order to improve the positive / negative balance of the current I _Lr of the resonant reactor Lr, the boost converter circuit 30 of Example 1 is used to connect between the relay terminal 4 and the second DC terminal 2. Instead of selectively short-circuiting the first and second main switches S1 and S2 and / or the third and fourth main switches S3 and S4 are simultaneously turned on, or By providing both, the relay terminal 4 and the second DC terminal 2 are selectively short-circuited. For example, as shown in FIG. 19B, the ON periods of the control signals Vg1 and Vg4 of the first and fourth main switches S1 and S4 are extended by t3 to t5 compared to FIG. The first and second main switches S1 and S2 are simultaneously on-controlled, and the third and fourth main switches S3 and S4 are simultaneously on-controlled. In FIG. 19B, only one of the control signals Vg1 and Vg4 of the first and fourth main switches S1 and S4 may be extended by t3 to t5.

The time t3 in FIG. 19 corresponds to the time of vertical rising or falling of the first and second corrected sawtooth voltages Vtu and Vtw in FIG. Accordingly, in FIG. 19, the ON periods of the first and fourth main switches S1 and S4 that are in the ON state immediately before the rising or falling time t3 of the first and second corrected sawtooth voltages Vtu and Vtw are t3 to t5. Has been extended only.
In some cases, the second and third main switches S2 and S3 are turned on immediately before the rising or falling time of the first and second corrected sawtooth voltages Vtu and Vtw. At this time, the ON periods of the second and third main switches S2 and S3 are extended by a period similar to that from t3 to t5 in FIG.
In the second embodiment, as shown in FIG. 19 (E), the extension signal Vd that becomes high at t3 to t5 is formed, and this is the first and fourth main switch control signals Vg1, Vg4 in FIG. 13 (B). To form the first and second main switch control signals Vg1 and Vg2 of FIG. 19B.

  FIG. 18 shows a part of the modified main switch control circuit 5a of FIG. The modified main switch control circuit 5a of FIG. 18 is a modification of the main switch control signal forming circuit 55 of the main switch control circuit 5 of FIG. 11, and the others are formed in the same manner as FIG. The modified main switch control signal forming circuit 55a shown in FIG. 18 includes first and second NOT circuits 73 and 74 connected to the output lines 71 and 72 of the first and second comparators 53 and 54, and First, second, third, and fourth extension circuits 75, 76, 77, 78, and an extension control circuit 79 are included. The first to fourth extension circuits 75 to 78 use the extension signal Vd indicating the extension period corresponding to t3 to t5 in FIG. 19 as the signal of the lines 71 and 72 and the output of the first and second NOT circuits 73 and 74. It consists of an addition circuit or an OR circuit for adding to the signal.

The extension control circuit 79 is connected to the sawtooth generator 52 shown in FIG. 11 by a line 52a, and is also connected to the current detection lines 7 and 8. The extension control circuit 79 forms an extension signal Vd that becomes high for a desired time t3 to t5 as shown in FIG. 19E in synchronization with the fall of the sawtooth voltage Vt of the line 52a. Vd is sent to the one selected from lines 79a, 79b, 79c, 79d. The lines 79a, 79b, 79c, 79d for selectively supplying the extension signal Vd are determined based on the phases of the U-phase and W-phase load currents Iu, Iw.
The first extension circuit 75 selectively adds the extension signal Vd of the line 79 a to the signal of the line 71, and sends the first main switch control signal Vg 1 to the line 9. The second extension circuit 76 selectively adds the extension signal Vd of the line 79b to the output signal of the first NOT circuit 73, and sends the second main switch control signal Vg2 to the line 10. 77 adds the extension signal Vd of the line 79c to the signal of the line 72 and sends the third main switch control signal Vg3 to the line 11. The third extension circuit 78 selectively adds the extension signal Vd of the line 79d to the output signal of the second NOT circuit 74 and sends the fourth main switch control signal Vg4 to the line 12.

In the second embodiment, when the first and second main switches S1 and S2 are simultaneously turned on, a current flows through the path Lr-Db-S1-S2-Cb, and the third and fourth main switches S3, S4 Are simultaneously turned on, a current flows through the path Lr-Db-S3-S4-Cb. Therefore, the improvement of the positive / negative balance of the current I _Lr of the resonant reactor Lr can be easily achieved as in the first embodiment by using the inverter circuit. Further, according to the second embodiment, the same effects as (1), (2) and (3) of the first embodiment can be obtained.
In FIG. 17, the boost converter circuit 30 of FIG. 10 can be provided instead of the boost converter circuit 30a.

  Next, the power converter of Example 3 shown in FIG. 20 will be described. The power conversion device of FIG. 20 includes first, second and third phase input AC terminals lr, ls, and lt, an AC-DC conversion circuit 30b, and a conversion switch control circuit 31b. In addition, the rest is formed substantially the same as FIG.

  In FIG. 20, one end of the series circuit of the first and second main switches S1 and S2 and the series circuit of the third and fourth main switches S3 and S4 constituting the inverter circuit is connected to the first relay terminal 4. These other ends are connected to the second relay terminal 4a. Therefore, the pair of conductors for inputting a DC voltage to the inverter circuit are the first and second relay terminals 4 and 4a. A series circuit of the first and second voltage dividing capacitors Ca and Cb is connected between the first and second relay terminals 4 and 4a via the first auxiliary switch Q1.

  The AC-DC conversion circuit 30b includes a first series circuit of first and second conversion switches Q11 and Q12 connected between the first and second relay terminals 4 and 4a, and a third and fourth conversion circuit. Switches Q13 and Q14, a first series circuit, first to fourth conversion diodes D11 to D14, first to fourth snubber capacitors C11 to C14, a first phase input AC terminal lr and A first input reactor L11 connected between the first and second conversion switches Q11 and Q12, a third phase input AC terminal lt, and third and fourth conversion switches Q13 and Q14. The second input reactor L12 connected between the first and second interconnection points, and the first and second input filter capacitors Cfr and Cft, the second phase input AC terminal ls being the first and second Voltage dividing capacitor Ca It is connected to the interconnection point of Cb. Therefore, the AC-DC conversion circuit 30b of FIG. 20 is configured as a V-connected converter circuit, similar to the V-connected inverter circuit including the first to fourth main switches S1 to S4.

  The first, second, third and fourth conversion diodes D11, D12, D13 and D14 are opposite to the first, second, third and fourth conversion switches Q11, Q12, Q13 and Q14. Connected in parallel direction. The first, second, third, and fourth snubber capacitors C11, C12, C13, and C14, which can also be called resonance capacitors, are the first, second, third, and fourth conversion switches Q11, Q12, respectively. , Q13, and Q14 are connected in parallel, and are configured by individual capacitors or parasitic capacitances having a sufficiently smaller capacity than the first and second voltage dividing capacitors Ca and Cb.

  The conversion switch control circuit 31b turns on and off the first to fourth conversion switches Q11 to Q14 by a well-known method. The first, second, third and fourth conversion switches Q11, Lines 65, 66, 67, and 68 for sending the first, second, third, and fourth conversion switch control signals Vq11, Vq12, Vq13, and Vq14 are provided to the control terminals of Q12, Q13, and Q14. The conversion switch control circuit 31b includes first, second, third, and fourth conversion switches for turning on / off the first to fourth conversion switches Q11 to Q14 so that AC-DC conversion can be performed. Control signals Vq11, Vq12, Vq13, Vq14 are formed by a known method. In order to turn on the first to fourth conversion switches Q11 to Q14 in synchronization with the first to fourth main switches S1 to S4, the conversion switch control circuit 31b generates a sawtooth generator of the main switch control circuit 5. 52 or the U-phase and W-phase correction circuits 56 and 57 are connected by a single or a plurality of transmission lines.

  First and second input reactors L11. L12 and the first and second filter capacitors Cfr and Cft function as filters that remove high-frequency components caused by turning on and off the first to fourth conversion switches Q11 to Q14.

  When the first to fourth conversion switches Q11 to Q14 constituting the AC-DC conversion circuit 30b are controlled to be turned on / off by a well-known method, the first, second and third phase input AC terminals lr, ls, lt The AC voltage is converted into a DC voltage and sent between the first and second relay terminals 4 and 4a, and the first and second voltage dividing capacitors Ca and Cb are charged.

The main switch control circuit 5a in FIG. 20 has the same configuration as that in FIG. Accordingly, as shown at t3 to t4 in FIG. 19, the negative direction current of the resonant reactor Lr is reduced by simultaneously turning on the first and second main switches S1, S2 or the third and fourth main switches S3, S4. Can be increased.
In FIG. 20, instead of simultaneously turning on the first and second main switches S1, S2 or the third and fourth main switches S3, S4, the first and second conversion switches Q11, Q12 or The third and fourth conversion switches Q13 and Q14 are the first and second boost conversion switches Sp and Sn of the first embodiment, or the first and second main switches S1 and S2, or the third and fourth switches. The main switches S3 and S4 can be turned on simultaneously. Signals for simultaneously turning on the first and second conversion switches Q11 and Q12 or the third and fourth conversion switches Q13 and Q14 in FIG. 20 are the timer 47 of the boost conversion switch control circuit 31 in FIG. Alternatively, it is formed by the same technique as the extension circuits 75 to 78 of the main switch control circuit 5a of FIG.

20 has the same effect as the power converters of FIGS. 3, 10, and 17, and can easily achieve soft switching of the first to fourth conversion switches Q <b> 11 to Q <b> 14. Have That is, the first to fourth conversion switches Q11 to Q14 are accompanied by the first to fourth snubber capacitors C11 to C14 in the same manner as the first to fourth main switches S1 to S4. The first to fourth conversion switches Q11 to Q14 can be soft-switched similarly to the first to fourth main switches S1 to S4.

The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) In FIG. 3, the main switch control circuit 5 a of FIG. 18 can be used instead of the main switch control circuit 5. Thereby, the inverter circuit and soft switching circuit of FIG. 3 operate in the same manner as the inverter circuit and soft switching circuit of FIG. 17, and the first and second main switches S1, S2 or the third and fourth main switches S3, By simultaneously turning on S4, the positive / negative balance of the current I _Lr of the resonant reactor Lr is improved, and the same effect as in the second embodiment can be obtained.
(2) As shown in FIG. 21, the first extension circuit 75 shown in FIG. 18 includes a delay circuit 80, a selection switch 81, an OR circuit 82, or a logic circuit similar thereto, and the second to fourth The extension circuits 76 to 78 can also be configured similarly to the first extension circuit 75 of FIG. The delay circuit 80 is set so as to give a delay corresponding to t3 to t5 in FIG. One input terminal of the OR circuit 82 of FIG. 21 is connected to the line 71, and the other input terminal is connected to the line 71 via the switch 81 and the delay circuit 80. The switch 81 is turned on by the control signal of the extension control circuit 79 in FIG. 18 when a delay is requested, and a logical sum signal of the non-delayed signal and the delayed signal is obtained from the OR circuit 82, which is the first signal on the line 9. Main switch control signal Vg1.
(3) The timer 47 in FIG. 11, the extension control circuit 79 in FIG. 18 and the delay circuit 80 in FIG. 21 are controlled by the signal on the output line 94 of the feedback control signal forming circuit 90 shown in FIG. Can be optimally controlled. 22 includes a Vca detection circuit 91 and a Vcb detection circuit 92 for detecting the voltages Vca and Vcb of the first and second voltage dividing capacitors Ca and Cb, and outputs of these outputs. And a subtractor 93 for forming a signal indicating the difference. The extension time and delay time are controlled so that the output of the subtractor 93 approaches zero. The balance between the voltage between the relay terminal 4 and the interconnection point Pm of the first and second voltage dividing capacitors Ca and Cb and the voltage between the interconnection point Pm and the second DC terminal 2 is detected. instead of, a current detector for detecting the current I _Lr in the resonant reactor Lr is provided to form a signal indicative of the positive and negative balance by detecting the positive component and a negative component of the current I _Lr, above thereby It is also possible to control the extension time or delay time.
(4) Instead of the step-up conversion circuit 30a of FIG. 17 showing the second embodiment, a well-known step-down conversion type DC-DC conversion circuit can be connected. Further, in place of the V-connection AC-DC conversion circuit 30b shown in the third embodiment, a general single-phase or three-phase bridge type AC-DC conversion circuit that does not use V-connection can be used.
(5) The first and second storage batteries having the same voltage can be connected instead of the first and second voltage dividing capacitors Ca and Cb having the same capacity.
(6) When the load connected to the first phase, second phase, and third phase AC terminals 3u, 3v, 3w has a filter action, the first and second reactors Lu, Lw and the first and second Any one or both of the filter capacitors Cf1, Cf2 can be omitted.
(7) The first to fourth main switch control signals Vg1 to Vg4 for the first to fourth main switches S1 to S4 may be formed as shown in FIGS.
(8) The circuit of FIG. 3 is provided with a circuit for detecting an abnormality of the power conversion device, and the first auxiliary switch Q1 can be controlled to be off when the abnormality is detected.
(9) The sawtooth generator 52 is not provided for the main switch control circuit 5 or 5a, the auxiliary switch control circuit 6, the step-up conversion switch control circuit 31 or 31a, or the conversion switch control circuit 31b, but can be provided independently. it can.

It is a circuit diagram which shows the conventional power converter device. It is a wave form diagram which shows the state of each part of FIG. It is a circuit diagram which shows the power converter device of the prior application and the modification of this invention. It is a block diagram which shows the main switch control circuit and auxiliary switch control circuit of the prior application of FIG. FIG. 5 is a waveform diagram schematically showing the state of each part in FIGS. 3 and 4. It is a wave form diagram which shows the state of each part of FIG. 4 in detail. It is a wave form diagram which shows the state of each part of FIG. 3 in the time of the turn-on of a 1st main switch, and its vicinity. FIG. 8 is a circuit diagram showing current paths in a plurality of divided sections in FIG. 7. FIG. 8 is a circuit diagram showing a current path in another divided section of FIG. 7. It is a circuit diagram which shows the power converter device of Example 1 of this invention. FIG. 11 is a block diagram illustrating a main switch control circuit, an auxiliary switch control circuit, and a boost conversion switch control circuit of FIG. 10. It is a wave form diagram which shows the state of each part of FIG. FIG. 12 is a waveform diagram showing the states of the respective parts in FIGS. 10 and 11 in the vicinity of the turn-on time of the third main switch in FIG. 12. It is a circuit diagram which shows the electric current path | route of the power converter device of FIG. 11 in three areas in eight divided | segmented areas of FIG. It is a circuit diagram which shows the electric current path | route of the power converter device of FIG. 11 in another two division | segmentation of FIG. It is a circuit diagram which shows the electric current path | route of the power converter device of FIG. 11 in another three area | regions divided | segmented of FIG. It is a circuit diagram which shows the power converter device of Example 2. FIG. It is a block diagram which shows a part of main switch control circuit of FIG. It is a wave form diagram which shows the state of each part of FIG. 17 similarly to FIG. It is a circuit diagram which shows the power converter device of Example 3. FIG. It is a circuit diagram which shows the modification of an extension circuit. It is a circuit diagram which shows a part of power converter device of a modification.

Explanation of symbols

1, 2 1st and 2nd DC terminals 3u, 3v, 3w 1st, 2nd and 3rd phase AC terminals 4 Relay terminal 5 Main switch control circuit 6 Auxiliary switch control circuit 30, 30a Boost conversion circuit 31, 31a Boost Conversion switch control circuits S1 to S4 First to fourth main switches Q1 and Q2 First and second auxiliary switches Sp and Sn First and second boost conversion switches C1 to C4 First to fourth resonances Capacitor Lr Resonant reactor

Claims (13)

First and second DC terminals (1, 2);
First, second and third phase AC terminals (3u, 3v, 3w);
A relay terminal (4);
A series circuit of first and second boost conversion switches (Sp, Sn) connected between the relay terminal (4) and the second DC terminal (2);
A step-up conversion reactor (Lin) connected between the first or second DC terminal (1, 2) and the second step-up conversion switch (Sn);
Individual or parasitic first and second boost conversion diodes (D11, D12) connected in parallel to the first and second boost conversion switches (Sp, Sn), respectively;
Individual or parasitic first and second snubber capacitors (C11, C12) connected in parallel to the first and second boost conversion switches (Sp, Sn), respectively;
A first voltage dividing capacitor (Ca) connected between the relay terminal (4) and the second phase AC terminal (3v) via a first auxiliary switch (Q1);
A second voltage dividing capacitor (Cb) connected between the second phase AC terminal (3v) and the second DC terminal (2);
A first main switch (S1) connected between the relay terminal (4) and the first phase AC terminal (3u);
A second main switch (S2) connected between the first phase AC terminal (3u) and the second DC terminal (2);
A third main switch (S3) connected between the relay terminal (4) and the third phase AC terminal (3w);
A fourth main switch (S4) connected between the third phase AC terminal (3w) and the second DC terminal (2);
Individual or parasitic first, second, third and fourth resonance capacitors connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. (C1, C2, C3, C4) and
An individual or parasitic first auxiliary diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A series circuit of a second auxiliary switch (Q2) and a resonant reactor (Lr) connected between the relay terminal (4) and the second phase AC terminal (3v);
An individual or parasitic second auxiliary diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
The first, second, third, and fourth so that a three-phase AC voltage (Vuv, Vvw, Vwu) can be obtained at the first, second, and third phase AC terminals (3u, 3v, 3w). A main switch control circuit (5) for controlling on / off of the main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage;
The voltages of the first, second, third and fourth resonance capacitors (C1, C2, C3, C4) are changed to the first, second, third and fourth main switches (S1, S2, S3, An auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the turn-on time of S4);
On / off control of the second boost conversion switch (Sn) at a frequency higher than the frequency of the three-phase AC voltage in order to boost the voltage between the first and second DC terminals (1, 2). And a step-up conversion switch for controlling on / off of the first step-up conversion switch (Sp) so as to reduce the difference between the value of the forward current and the value of the reverse current flowing through the resonant reactor (Lr). It has a control circuit (31), The power converter device characterized by the above-mentioned. First and second DC terminals (1, 2);
First, second and third phase AC terminals (3u, 3v, 3w);
A relay terminal (4);
A voltage conversion circuit (30) connected between the first and second DC terminals (1, 2) and the relay terminal (4);
A first voltage dividing capacitor (Ca) connected between the relay terminal (4) and the second phase AC terminal (3v) via a first auxiliary switch (Q1);
A second voltage dividing capacitor (Cb) connected between the second phase AC terminal (3v) and the second DC terminal (2);
A first main switch (S1) connected between the relay terminal (4) and the first phase AC terminal (3u);
A second main switch (S2) connected between the first phase AC terminal (3u) and the second DC terminal (2);
A third main switch (S3) connected between the relay terminal (4) and the third phase AC terminal (3w);
A fourth main switch (S4) connected between the third phase AC terminal (3w) and the second DC terminal (2);
Individual or parasitic first, second, third and fourth resonance capacitors connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. (C1, C2, C3, C4) and
An individual or parasitic first auxiliary diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A series circuit of a second auxiliary switch (Q2) and a resonant reactor (Lr) connected between the relay terminal (4) and the second phase AC terminal (3v);
An individual or parasitic second auxiliary diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
The first, second, third, and fourth so that a three-phase AC voltage (Vuv, Vvw, Vwu) can be obtained at the first, second, and third phase AC terminals (3u, 3v, 3w). A main switch control circuit (5a) for controlling on / off of the main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage;
The voltages of the first, second, third and fourth resonance capacitors (C1, C2, C3, C4) are changed to the first, second, third and fourth main switches (S1, S2, S3, And an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the turn-on time of S4). The main switch control circuit (5a) further includes the first and second main switches (5a) so as to reduce a difference between a forward current value and a reverse current value flowing through the resonant reactor (Lr). S1, S2) or the third and fourth main switches (S3, S4) or the first to fourth main switches (S1 to S4) are simultaneously turned on. Power conversion device. First and second DC terminals (1, 2);
First, second and third phase AC terminals (3u, 3v, 3w);
A relay terminal (4);
A first voltage dividing capacitor (Ca) connected between the first DC terminal (1) and the second phase AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second DC terminal (2) and the second phase AC terminal (3v);
A first main switch (S1) connected between the relay terminal (4) and the first phase AC terminal (3u);
A second main switch (S2) connected between the first phase AC terminal (3u) and the second DC terminal (2);
A third main switch (S3) connected between the relay terminal (4) and the third phase AC terminal (3w);
A fourth main switch (S4) connected between the third phase AC terminal (3w) and the second DC terminal (2);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) connected between the first DC terminal (1) and the relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A series circuit of a second auxiliary switch (Q2) and a resonant reactor (Lr) connected between the relay terminal (4) and the second phase AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
The first, second, third, and fourth so that a three-phase AC voltage (Vuv, Vvw, Vwu) can be obtained at the first, second, and third phase AC terminals (3u, 3v, 3w). A main switch control circuit (5a) for controlling on / off of the main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage;
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or substantially zero by the turn-on time. The main switch control circuit (5a) further includes the first and second so as to reduce the difference between the value of the forward current and the value of the reverse current flowing through the resonant reactor (Lr). The main switch (S1, S2), the third and fourth main switches (S3, S4) or the first to fourth main switches (S1 to S4) are turned on simultaneously. A power conversion device. At least first and second input AC terminals (1r, 1t);
First, second and third phase output AC terminals (3u, 3v, 3w);
First and second relay terminals (4, 4a);
A first main switch (S1) connected between the first relay terminal (4) and the first phase output AC terminal (3u);
A second main switch (S2) connected between the first phase output AC terminal (3u) and the second relay terminal (4a);
A third main switch (S3) connected between the first relay terminal (4) and the third phase output AC terminal (3w);
A fourth main switch (S4) connected between the third phase output AC terminal (3w) and the second relay terminal (4a);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) having one end connected to the first relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A first voltage dividing capacitor (Ca) connected between the other end of the first auxiliary switch (Q1) and the second phase output AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second phase output AC terminal (3v) and the second relay terminal (4a);
A series circuit of a second auxiliary switch (Q2) and a resonance reactor (Lr) connected between the first relay terminal (4) and the second phase output AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
A first conversion switch (Q11) connected between the first input AC terminal (1r) and the first relay terminal (4), the first input AC terminal (1r) and the first A second conversion switch (Q12) connected between the second relay terminal (4a) and the second input AC terminal (1t) and the first relay terminal (4). And a third conversion switch (Q13) and a fourth conversion switch (Q14) connected between the second input AC terminal (1t) and the second relay terminal (4a). An AC-DC conversion circuit (30b);
The first, second, third and third phase AC voltages (Vuv, Vvw, Vwu) can be obtained at the first, second and third phase output AC terminals (3u, 3v, 3w). A main switch control circuit (5 or 5a) for controlling on / off of four main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the time of turn-on. ,
A function of controlling the first, second, third and fourth conversion switches (Q11, Q12, Q13, Q14) so as to obtain a DC output voltage from the AC-DC conversion circuit (30b); and the resonance reactor. The first and second conversion switches (Q11, Q12) or the third and fourth conversion switches so as to reduce the difference between the value of the forward current flowing in (Lr) and the value of the reverse current. (Q13, Q14) or a conversion switch control circuit (31b) having a function of simultaneously turning on the first to fourth conversion switches (Q11 to Q14). Power conversion device. At least first and second input AC terminals (1r, 1t);
First, second and third phase output AC terminals (3u, 3v, 3w);
First and second relay terminals (4, 4a);
A first main switch (S1) connected between the first relay terminal (4) and the first phase output AC terminal (3u);
A second main switch (S2) connected between the first phase output AC terminal (3u) and the second relay terminal (4a);
A third main switch (S3) connected between the first relay terminal (4) and the third phase output AC terminal (3w);
A fourth main switch (S4) connected between the third phase output AC terminal (3w) and the second relay terminal (4a);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) having one end connected to the first relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A first voltage dividing capacitor (Ca) connected between the other end of the first auxiliary switch (Q1) and the second phase output AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second phase output AC terminal (3v) and the second relay terminal (4a);
A series circuit of a second auxiliary switch (Q2) and a resonance reactor (Lr) connected between the first relay terminal (4) and the second phase output AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
An AC-DC conversion circuit (30b) connected between the first and second input AC terminals (1r, 1t) and the first and second relay terminals (4, 4a);
The first, second, third and third phase AC voltages (Vuv, Vvw, Vwu) can be obtained at the first, second and third phase output AC terminals (3u, 3v, 3w). A main switch control circuit (5a) for controlling on / off of the four main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage;
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the time of turn-on. ,
The main switch control circuit (5a) further includes the first and second so as to reduce the difference between the value of the forward current and the value of the reverse current flowing through the resonant reactor (Lr). The main switch (S1, S2), the third and fourth main switches (S3, S4) or the first to fourth main switches (S1 to S4) are turned on simultaneously. A power conversion device. First, second and third phase input AC terminals (1r, 1s, 1t);
First, second and third phase output AC terminals (3u, 3v, 3w);
First and second relay terminals (4, 4a);
A first main switch (S1) connected between the first relay terminal (4) and the first phase output AC terminal (3u);
A second main switch (S2) connected between the first phase output AC terminal (3u) and the second relay terminal (4a);
A third main switch (S3) connected between the first relay terminal (4) and the third phase output AC terminal (3w);
A fourth main switch (S4) connected between the third phase output AC terminal (3w) and the second relay terminal (4a);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) having one end connected to the first relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A first voltage dividing capacitor (Ca) connected between the other end of the first auxiliary switch (Q1) and the second phase output AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second phase output AC terminal (3v) and the second relay terminal (4a);
A series circuit of a second auxiliary switch (Q2) and a resonance reactor (Lr) connected between the first relay terminal (4) and the second phase output AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
AC-DC converter circuit (30b) connected between the first, second and third phase input AC terminals (1r, 1s, 1t) and the first and second relay terminals (4, 4a). When,
The first, second, third and third phase AC voltages (Vuv, Vvw, Vwu) can be obtained at the first, second and third phase output AC terminals (3u, 3v, 3w). A main switch control circuit (5 or 5a) for controlling on / off of four main switches (S1, S2, S3, S4) at a frequency higher than the frequency of the three-phase AC voltage
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the time of turn-on. ,
An AC-DC conversion control circuit (31b) for controlling the AC-DC conversion circuit (30b), and the AC-DC conversion circuit (30b) includes the first and second relay terminals (4). 4a) a first series circuit of first and second conversion switches (Q11, Q12) and a second series circuit of third and fourth conversion switches (Q13, Q14) connected between , First, second, third and fourth snubber capacitors or parasitics connected in parallel to the first, second, third and fourth conversion switches (Q11, Q12, Q13, Q14), respectively. Capacitors (C11, C12, C13, C14), the first phase input AC terminal (1r) and the first connection point between the first and second conversion switches (Q11, Q12). 1 input reactor (L11), the third phase input AC terminal (1t), the third and the third And a second input reactor (L12) connected between the mutual connection points of the conversion switches (Q13, Q14), and the second phase input AC terminal (1s) is the first and second Connected to the interconnection point of the voltage dividing capacitors (Ca, Cb)
The AC-DC conversion control circuit (31b) controls the first, second, third and fourth conversion switches (Q11, Q12, Q13, Q14) so as to convert an AC voltage into a DC voltage. Function and the first and second conversion switches (Q11, Q12) or the third and A power converter having a function of simultaneously turning on the fourth conversion switch (Q13, Q14) or the first to fourth conversion switches (Q11 to Q14). First, second and third phase input AC terminals (1r, 1s, 1t);
First, second and third phase output AC terminals (3u, 3v, 3w);
First and second relay terminals (4, 4a);
A first main switch (S1) connected between the first relay terminal (4) and the first phase output AC terminal (3u);
A second main switch (S2) connected between the first phase output AC terminal (3u) and the second relay terminal (4a);
A third main switch (S3) connected between the first relay terminal (4) and the third phase output AC terminal (3w);
A fourth main switch (S4) connected between the third phase output AC terminal (3w) and the second relay terminal (4a);
First, second, third and fourth resonance capacitors or parasitic capacitances connected in parallel to the first, second, third and fourth main switches (S1, S2, S3, S4), respectively. C1, C2, C3, C4),
A first auxiliary switch (Q1) having one end connected to the first relay terminal (4);
A first auxiliary diode or parasitic diode (Da) connected in reverse parallel to the first auxiliary switch (Q1);
A first voltage dividing capacitor (Ca) connected between the other end of the first auxiliary switch (Q1) and the second phase output AC terminal (3v);
A second voltage dividing capacitor (Cb) connected between the second phase output AC terminal (3v) and the second relay terminal (4a);
A series circuit of a second auxiliary switch (Q2) and a resonance reactor (Lr) connected between the first relay terminal (4) and the second phase output AC terminal (3v);
A second auxiliary diode or parasitic diode (Db) connected in reverse parallel to the second auxiliary switch (Q2);
AC-DC converter circuit (30b) connected between the first, second and third phase input AC terminals (1r, 1s, 1t) and the first and second relay terminals (4, 4a). When,
The first, second, third and second phase AC voltages (Vuv, Vvw, Vwu) can be obtained at the first, second and third phase output AC terminals (3u, 3v, 3w). A main switch control circuit (5a) for controlling on / off of the four main switches (S1, S2, S3, S4) at a repetition frequency higher than the frequency of the three-phase AC voltage;
The voltage of the first, second, third and fourth resonance capacitors or parasitic capacitances (C1, C2, C3, C4) is set to the first, second, third and fourth main switches (S1, S2). , S3, S4), and an auxiliary switch control circuit (6) for controlling on / off of the first and second auxiliary switches (Q1, Q2) so that they can be reduced to zero or almost zero by the time of turn-on. ,
An AC-DC conversion control circuit (31b) for controlling the AC-DC conversion circuit (30b), and the AC-DC conversion circuit (30b) includes the first and second relay terminals (4). 4a) a first series circuit of first and second conversion switches (Q11, Q12) and a second series circuit of third and fourth conversion switches (Q13, Q14) connected between , First, second, third and fourth snubber capacitors or parasitics connected in parallel to the first, second, third and fourth conversion switches (Q11, Q12, Q13, Q14), respectively. Capacitors (C11, C12, C13, C14), the first phase input AC terminal (1r) and the first connection point between the first and second conversion switches (Q11, Q12). 1 input reactor (L11), the third phase input AC terminal (1t), the third and the third And a second input reactor (L12) connected between the mutual connection points of the conversion switches (Q13, Q14), and the second phase input AC terminal (1s) is the first and second Connected to the interconnection point of the voltage dividing capacitors (Ca, Cb)
The main switch control circuit (5a) further includes the first and second main switches (S1) so as to reduce the difference between the value of the forward current flowing in the resonance reactor (Lr) and the value of the reverse current. , S2) or the third and fourth main switches (S3, S4) or the first to fourth main switches (S1 to S4) at the same time. Conversion device.   Furthermore, a first filter reactor (Lu) connected between the first and second main switches (S1, S2) and the first phase AC terminal (3u), the third and fourth And a second filter reactor (Lw) connected between the main switch (S3, S4) and the third-phase AC terminal (3w). The power converter device in any one of. Furthermore, individual or parasitic first, second, third and second connected in reverse direction parallel to the first, second, third and fourth main switches (S1, S2, S3, S4). The power converter according to claim 1, comprising four main diodes (D 1, D 2, D 3, D 4).   The auxiliary switch control circuit (6) is turned on from a first time (t1) slightly before a turn-on time (t3) of at least one of the first to fourth main switches (S1 to S4). The function of controlling the first auxiliary switch (Q1) to the off state and controlling the second auxiliary switch (Q2) to the on state until a second time point (t6) slightly after the time point (t3). A first time length (Ta) from the first time point (t1) to the turn-on time point (t3) by the action of the resonance reactor (Lr) until the turn-on time point (t3). 4) and the second DC terminal (2) or the voltage between the first relay terminal (4) and the second relay terminal (4a) can be zero or almost zero. Time length, before the turn-on time (t3) The second time length (Tb) until the second time point (t6) is zeroed by the action of the resonance reactor (Lr) until the voltage of the first auxiliary switch (Q1) is zero by the second time point (t6). The power conversion device according to any one of claims 1 to 9, wherein the time length is set to be substantially zero. The step-up conversion switch control circuit (31) measures a desired time (Tc) in synchronization with the turn-on of the second auxiliary switch (Q2), and the first step-up conversion switch for the desired time (Tc). The power converter according to claim 1, further comprising a timer (47) for controlling the switch (Sp) to be turned on. The step-up conversion switch control circuit (31) has the desired time (Tc) measured by the timer (47) so as to reduce the voltage difference between the first and second voltage dividing capacitors (Ca, Cb). 12. The power conversion device according to claim 11, further comprising a unit for controlling the length of (). The main switch control circuit (5a) has means for selectively extending the ON period of the first, second, third and fourth main switches (S1, S2, S3, S4). The power conversion device according to claim 2, 3, 5, or 7.

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