JP2005243893A - Manufacturing method of mesa-type semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a high breakdown voltage and high reliability, by preventing cracks or chipping in a chip, in the element partitioning process of the mesa-type semiconductor device having glass coating. <P>SOLUTION: The manufacturing method of the mesa-type semiconductor device comprises a coating process of grooves for separating between the elements by glass coating, and a process of partitioning respective elements by cutting the central part of the grooves by a dicing blade. The feeding speed of dicing in the dicing blade is kept so as to be a low speed in the initial stage of cutting, and the cutting is carried out by gradually increasing the dicing speed thereafter. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a mesa type semiconductor device, and more particularly to a manufacturing method capable of suppressing chipping and cracking of a glass coating and eliminating pre-cutting during dicing.

  Various techniques for increasing the yield and reliability of the mesa type semiconductor device isolation method have been proposed.

  For example, a technique described in Patent Document 1 is known as a technique relating to high reliability of a mesa semiconductor device. This prior art is a method for manufacturing a semiconductor device in which the inner wall of a mesa groove is coated with glass. After firing the glass film, the glass at the center of the mesa groove is removed by dicing, and then the glass film is fired again, and there is no crack. It is said that a glass coating is obtained.

  Further, as another conventional technique related to high reliability of a mesa type semiconductor device, a technique described in Patent Document 2 is known. In this prior art, two adjacent mesa grooves are provided within a certain width, a convex part is provided in the middle of the two mesa grooves, and the convex part is etched to be lower than the surface of the semiconductor substrate. Thus, the reliability of the semiconductor device is improved and the breakdown voltage is increased so that cracks do not enter the glass during dicing.

Moreover, as a technique described in Patent Documents 3 and 4, a method of pre-cutting a sawing blade with a dummy wafer before dicing is known as a crack prevention during dicing.
JP-A-5-335322 Japanese Unexamined Patent Publication No. 7-2221049 JP-A-5-326700 Japanese Patent Laid-Open No. 11-176772

  However, even if the pre-cut method disclosed in Patent Document 3 and Patent Document 4 is performed, about 1 to 500 lines after the start of dicing when separating a mesa semiconductor device having a glass film at the center of the mesa groove During the dicing, there was a drawback that cracks and chipping occurred.

  The present invention solves the problems of cracks and chipping in the conventional manufacturing method, can achieve high reliability, can eliminate the pre-cut, shorten the lead time, and can realize a low price. An object of the present invention is to provide a method for manufacturing a type semiconductor device.

  In order to solve the above problems, a method for manufacturing a mesa semiconductor device according to the present invention includes a step of covering a groove portion for separating elements with a glass film, and cutting each central portion of the groove with a dicing blade. A method of manufacturing a mesa semiconductor device including a step of dividing, wherein the dicing feed speed of the dicing blade is set to a low speed at an initial stage of cutting, and thereafter the cutting is performed by gradually increasing the speed.

  In the element dividing step, the rotation speed of the blade is 10,000 r. p. m. ˜50000 r. p. m. And the cutting feed rate is preferably 0.1 mm / second to 80 mm / second.

  As described above, according to the present invention, when a mesa-type semiconductor device having a glass coating in a groove portion is separated from the center portion of the mesa groove, cutting is performed by gradually increasing the dicing feed speed of the dicing blade from a low speed. As a result, the occurrence of glass chipping and glass cracking can be suppressed, and extremely high reliability can be realized. Further, the precut of the blade can be reduced, and the lead time can be shortened and the manufacturing cost can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view of a mesa npn bipolar transistor according to an embodiment of the present invention.

  The bipolar transistor includes a collector region 1, a base region 3, and an emitter region 4. A mesa groove 5 is provided around the base region 3 and the emitter region 4 so that a pn junction is exposed, and the surface thereof is a glass film. 6, a base electrode 7, an emitter electrode 8, and a collector electrode 9.

  FIG. 2 is an explanatory diagram of a manufacturing process of the mesa bipolar transistor shown in FIG. 1, and is a schematic sectional view for explaining a dividing process by a dicing method.

  As shown in FIG. 2A, after the mesa groove 5 is covered with the glass film 6 and patterned, the glass film 6 is densified by heat treatment.

  Next, as shown in FIG. 2B, the center of the mesa portion of the semiconductor wafer is separated by a dicing method to obtain a mesa semiconductor device.

  In this step, cutting separation is performed by gradually increasing the feed speed of the dicing blade using a dicing blade that has not been pre-cut.

  For example, the first dicing line to be cut from the 50th line is 0.5 mm / second, the 51st to 100th line is 1.0 mm / second, the 101st line to the 150th line is 1.5 mm / second, 151-200 line 2.0 mm / sec to the eyes, 2.5 mm / sec to the 201st to 250th lines, 3.0 mm / sec to the 251st to 300th lines, 3.5 mm / sec to the 301st to 350th lines, 351 Dicing is performed by increasing the feed speed of the dicing blade stepwise, such as 4.0 mm / second up to 400th line, 4.5 mm / second up to 401-451th line, and 5 mm / second from 451 mm onward. Do. In this case, the rotational speed of the blade is 45000 r. p. m. Dicing was performed.

  In the above process, from the viewpoint of achieving both productivity and suppression of occurrence of cracks and chipping, the rotational speed of the blade is 10,000 rpm. p. m. ˜50000 r. p. m. And the cutting feed rate is preferably 0.1 mm / second to 80 mm / second.

  As described above, according to the present embodiment, an excessive frictional force is generated between the wafer and the blade by performing dicing by initially reducing the blade feed speed without performing pre-cutting. Therefore, cracks and chipping can be greatly reduced. Further, as the dicing is performed, the unevenness of the blade surface is reduced and the friction with the wafer is also reduced. In accordance with this, the feed rate is increased stepwise, thereby preventing a significant decrease in throughput.

  3A and 3B are diagrams showing the relationship between the number of dicing lines and the amount of chipping. FIG. 3A shows a case where processing is performed by a conventional dicing method, FIG. 3B shows a case where processing is performed by the method of the present invention, and FIG. It is the figure which showed the relationship between a line and the chipping amount.

  The conditions of the conventional dicing method were as follows: the blade feed speed was 5 mm / second and the rotational speed was 45000 rpm.

  As can be seen from FIG. 3A, in the conventional method, chipping increases from the start of dicing to the 300th line. This is presumably due to excessive friction between the wafer and the blade.

  On the other hand, according to the dicing method of the present invention, as shown in FIG. 3B, it was confirmed that the chipping amount was small and stable from the start of dicing.

  4 and 5 show actual photographs of chipping that occurs during dicing. FIG. 4 is a photograph of the appearance of the 50th, 200th, and 400th lines when dicing is performed by the conventional method, and cracks and chipping can be observed. On the other hand, FIG. 5 is an appearance photograph when dicing is performed using the above-described present invention, and it can be observed that cracks and chipping are extremely reduced.

  In other words, it was confirmed that the occurrence of glass chipping and glass cracks can be significantly suppressed by cutting the dicing feed speed of the dicing blade gradually from a low speed as in this embodiment.

  The mesa semiconductor device of the present embodiment manufactured as described above can stably obtain 1500 to 2000 V or more as the base-collector reverse direction (VCES) breakdown voltage, and the collector cutoff current (ICES leakage current). Also, the base-collector reverse application (VCES) voltage was 15uA or less at 1630V, and the blocking characteristics were extremely excellent. This is considered to be because the generation of leakage current due to glass chipping and cracks was suppressed.

  In this embodiment, a mesa npn bipolar transistor having a glass film has been described. However, even when applied to other semiconductor devices, the same effect can be obtained with respect to suppression of cracks and chipping. is there.

  The method for manufacturing a mesa semiconductor device according to the present invention is useful as a method for manufacturing a power semiconductor device having a high breakdown voltage.

Sectional drawing of mesa type semiconductor device in an embodiment of the invention Explanatory drawing of element dividing process of mesa type semiconductor device in the embodiment of the present invention It is the figure which showed the relationship between the number of dicing lines and chipping amount, (a) is a figure at the time of processing by the conventional dicing method, (b) is a figure at the time of processing by the method of this invention, (c) is Diagram showing the relationship between dicing line and chipping amount Actual optical micrograph of chipping that occurs when dicing by the conventional method Actual optical micrograph of chipping that occurs when dicing using the method of the present invention

Explanation of symbols

1 N type semiconductor region 2 N ⁺ type semiconductor region 3 P type semiconductor region 4 P ⁺ type semiconductor region 5 Mesa groove 6 Glass coating 7 Base electrode 8 Emitter electrode 9 Collector electrode

Claims (2)

A step of coating a groove for separating elements with a glass film;
A mesa type semiconductor device manufacturing method comprising a step of dividing each element by cutting the groove central portion with a dicing blade,
A method of manufacturing a mesa semiconductor device, wherein the dicing feed speed of the dicing blade is set to a low speed at an initial stage of cutting, and thereafter the speed is gradually increased to perform cutting. In the element dividing step, the rotation speed of the blade is 10,000 r. p. m. ˜50000 r. p. m. The method for manufacturing a mesa semiconductor device according to claim 1, wherein the cutting feed rate is in a range of 0.1 mm / second to 80 mm / second.