JP2005243822A - Thin film transistor, method for manufacturing same circuit thereof, electronic device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin film transistor capable of manufacturing a thin film transistor with good characteristics, the thin film transistor to be manufactured by the method for manufacturing the thin film transistor, a thin film transistor circuit provided with the thin film transistor, an electronic device and an electronic apparatus. <P>SOLUTION: The method for manufacturing the thin film transistor comprises the steps of feeding, onto a substrate formed with a source electrode and a drain electrode, a liquefied material containing an organic semiconductor layer forming material and a first gate insulating layer forming material which are insoluble to each other, and a solvent which can dissolve both the materials to form a liquefied layer 9; and of removing the solvent from in the liquefied layer 9, with the result that a first domain 91' mainly containing the organic semiconductor layer forming material and a second domain 92' mainly containing the first gate insulating layer forming material are isolated from each other in a thickness direction of the liquefied layer 9 to be also solidified, to obtain an organic semiconductor layer and a first gate insulating layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a thin film transistor, a thin film transistor, a thin film transistor circuit, an electronic device, and an electronic apparatus.

In recent years, development of a thin film transistor using an organic material (organic semiconductor material) that exhibits semiconducting electrical conduction has been promoted. This thin film transistor has advantages such as being suitable for reduction in thickness and weight, flexibility, and low material cost, and is expected as a switching element for flexible displays and the like.
Such a thin film transistor includes a top gate structure in which a source electrode and a drain electrode are formed on a substrate, and an organic semiconductor layer, a gate insulating layer, and a gate electrode are stacked in this order on the substrate, and a gate on the substrate. A bottom gate structure in which an electrode, a gate insulating layer, and an organic semiconductor layer are stacked in this order, and a source electrode and a drain electrode are formed on the organic semiconductor layer has been proposed.

By the way, in such a thin film transistor, as a method for forming an organic semiconductor layer or a gate insulating layer, a method based on a solution process in which a solution in which a constituent material of each layer is dissolved in a solvent is applied is known. This solution process has an advantage that a film can be formed in a simple process without using a large-scale apparatus used in a vacuum deposition method or the like.
For example, in order to form an organic semiconductor layer and a gate insulating layer having a top gate structure by this solution process, a solution in which an organic semiconductor material is dissolved is applied to a substrate on which a source electrode and a drain electrode are formed, and is dried. After forming an organic semiconductor layer, a gate insulating layer is formed by applying a solution in which an organic insulating material is dissolved on the organic semiconductor layer and performing drying or the like (see, for example, Patent Document 1). .

In addition, in order to form a gate insulating layer and an organic semiconductor layer having a bottom gate structure, a solution in which an organic insulating material is dissolved is applied to a substrate on which a gate electrode is formed, and dried to perform the gate insulating layer. After the formation, an organic semiconductor layer is formed by applying a solution in which an organic semiconductor material is dissolved on the gate insulating layer and performing drying or the like.
However, when the organic semiconductor layer and the gate insulating layer are formed in this way, depending on the combination of each organic material and solvent, the lower layer (upper layer (upper layer) is formed by the solvent of the solution for forming the upper layer (upper layer)). The lower layer may swell and dissolve.

In order to avoid such an inconvenience, a solvent that does not swell or dissolve the constituent material of the lower layer is used as a solvent of the solution for forming the upper layer.
For example, an aromatic hydrocarbon solvent generally dissolves an organic semiconductor material, but hardly dissolves an organic insulating material. In addition, ketone-based or ether-based oxygen-containing solvents dissolve organic insulating materials but hardly dissolve organic semiconductor materials.
Therefore, by using these solvents as the solvent for the organic semiconductor layer and the solvent for the gate insulating layer, respectively, swelling and dissolution of the lower gate insulating layer or organic semiconductor layer can be prevented.

However, in this method, the solvent that can be used is limited, and therefore, the organic semiconductor material or the organic insulating material is also limited to one that can be dissolved in the solvent. Therefore, the selection range of the material is narrow, and the characteristics of each layer are optimized. There is a problem that it is difficult.
Another method for preventing the lower layer from swelling and dissolving is to form a crosslinked structure in the lower layer and insolubilize it. Specifically, a cross-linking agent and a radical generator are added to the lower layer forming solution together with the constituent material of the lower layer, and a coating film is formed by applying this solution. And a crosslinked structure is formed in this coating film by performing heat processing or ultraviolet irradiation.
However, this method has a problem that the characteristics of the transistor deteriorate due to the influence of the cross-linking agent added to the solution, the unreacted radical generator, and the reaction product.
In particular, in the organic semiconductor layer, when a crosslinked structure is formed, an electron conjugated system that determines characteristics as a semiconductor is destroyed, and thus it is not preferable to form a crosslinked structure.

Special table 2003-518754 gazette

  The present invention provides a thin film transistor manufacturing method capable of manufacturing a thin film transistor having excellent characteristics, a thin film transistor manufactured by the thin film transistor manufacturing method, a thin film transistor circuit including the thin film transistor, an electronic device, and an electronic apparatus. is there.

Such an object is achieved by the present invention described below.
The method of manufacturing a thin film transistor of the present invention includes a source electrode, a drain electrode, a gate electrode, an organic insulator layer that insulates the gate electrode from the source electrode and the drain electrode, and a contact with the organic insulator layer A method of manufacturing a thin film transistor having an organic semiconductor layer,
A first material for forming the organic semiconductor layer on the substrate on which the source electrode and the drain electrode or the gate electrode are formed, and the organic insulator layer that is not compatible with the first material. A first step of forming a liquid layer by supplying a liquid material containing a second material for forming and a solvent capable of dissolving both the first material and the second material;
By removing the solvent from the liquid layer, the first domain mainly including the first material and the second domain mainly including the second material are reduced in thickness of the liquid layer. And a second step of obtaining the organic semiconductor layer and the organic insulator layer by phase separation in the direction and solidification.
Thereby, since the selection range of the first material and the second material is widened, a thin film transistor having excellent characteristics can be manufactured by appropriately setting a combination thereof.

In the method for manufacturing a thin film transistor of the present invention, prior to the first step, one of the organic semiconductor layer and the organic insulator layer on the surface side of the substrate on which the liquid layer is formed is the substrate side. It is preferable to include a step of performing an affinity improvement treatment in which the affinity for the material for forming the layer is higher than the affinity for the material for forming the other layer.
Thereby, the first domain and the second domain can be more reliably separated (vertical phase separation) in the thickness direction of the liquid layer.

In the method for manufacturing a thin film transistor of the present invention, the affinity improving process is preferably a plasma process.
According to the plasma treatment, the affinity improvement treatment can be easily performed.
In the method for manufacturing a thin film transistor of the present invention, it is preferable that the affinity improving process is a chemical modification process for introducing a chemical structure including a part of the compound constituting the first material or the second material.
According to the chemical modification treatment, a more optimal treatment can be performed according to the characteristics of the first material and the second material.

In the method for manufacturing a thin film transistor of the present invention, it is preferable that at least one of the first material and the second material is a polymer material.
Thereby, a 1st domain and a 2nd domain can be phase-separated more reliably.
In the method for manufacturing a thin film transistor of the present invention, it is preferable that the first material is a polymer material and the weight average molecular weight is 4000 to 300,000.
Thereby, a 1st domain and a 2nd domain can be phase-separated more reliably.
In the method for manufacturing a thin film transistor of the present invention, it is preferable that the second material is a polymer material and the weight average molecular weight is 10,000 to 2,000,000.
Thereby, a 1st domain and a 2nd domain can be phase-separated more reliably.

In the method for producing a thin film transistor of the present invention, the solvent is preferably a high boiling point solvent.
This makes it easy to adjust the time required to solidify the liquid layer, and when applying the droplet discharge method as a liquid material supply method, the characteristics (viscosity, etc.) of the liquid material It becomes easy to adjust to a suitable one.

In the thin film transistor manufacturing method of the present invention, the solvent is preferably a low boiling point solvent.
Thereby, it can prevent more reliably that a solvent remains in the organic-semiconductor layer and organic insulator layer which are obtained. As a result, the characteristics of the obtained thin film transistor can be further improved.
In the method for manufacturing a thin film transistor of the present invention, it is preferable that a mixing ratio of the first material and the second material in the liquid material is 3: 1 to 1: 3 by weight.
Thereby, a 1st domain and a 2nd domain can be phase-separated more reliably.

In the method for manufacturing a thin film transistor of the present invention, in the first step, the liquid material is preferably supplied by a droplet discharge method.
According to the appropriate liquid discharge method, the liquid material can be accurately supplied to a predetermined position, and as a result, the organic semiconductor layer and the organic insulator layer having a predetermined shape can be formed with high dimensional accuracy.

In the thin film transistor manufacturing method of the present invention, it is preferable that the time required for solidifying the liquid layer in the second step is 5 seconds or more.
If this time is too short, the liquid layer solidifies before the first domain and the second domain are sufficiently grown, and the first domain and the second domain are separated into layers (vertical). Phase separation) may be difficult.

In the thin film transistor manufacturing method of the present invention, when the average thickness of the liquid layer after solidification is t, in the step 2, the average thickness of the liquid layer is in the range of 1.2 t to 10 t. It is preferable that the contact angle with respect to the surface which forms the said liquid layer of any one of 1 domain or the said 2nd domain is 30 degrees or less.
As a result, the first domain and the second domain can be more reliably subjected to vertical phase separation.

In the thin film transistor manufacturing method of the present invention, in the second step, the solidified liquid layer is preferably subjected to heat treatment.
Thereby, for example, when the first material is composed of a precursor of an organic semiconductor material, the precursor is reacted (formation of unsaturated bond, polymerization reaction, etc.) to be changed into an organic semiconductor material. be able to. In addition, by performing the heat treatment, the solidified first domain and the second domain can be melted or softened again, so that the first domain and the second domain can be more reliably secured. It can be separated (these interfaces are made clearer). As a result, the finally obtained thin film transistor is more excellent in characteristics.

The thin film transistor of the present invention is manufactured by the method for manufacturing a thin film transistor of the present invention.
Thereby, a thin film transistor having excellent characteristics (switching characteristics) can be obtained.
The thin film transistor circuit of the present invention includes the thin film transistor of the present invention.
Thereby, a highly reliable thin film transistor circuit is obtained.
An electronic device according to the present invention includes the thin film transistor circuit according to the present invention.
Thereby, an electronic device with high reliability can be obtained.
An electronic apparatus according to the present invention includes the electronic device according to the present invention.
As a result, a highly reliable electronic device can be obtained.

Hereinafter, a thin film transistor manufacturing method, a thin film transistor, a thin film transistor circuit, an electronic device, and an electronic device according to preferred embodiments of the present invention will be described in detail.
<Thin Film Transistor and Manufacturing Method Thereof>
First, the thin film transistor of the present invention and the manufacturing method thereof will be described.
<< First Configuration of Thin Film Transistor >>
First, the first configuration (first embodiment) of the thin film transistor of the present invention will be described.
FIG. 1 is a longitudinal sectional view showing a thin film transistor having a first configuration. In the following description, the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”.

A thin film transistor 1 shown in FIG. 1 is provided on a substrate 2, and includes a source electrode 3 and a drain electrode 4, an organic semiconductor layer 5, a first gate insulating layer (organic insulator layer) 61, a second electrode The gate insulating layer 62 and the gate electrode 7 are laminated in this order from the substrate 2 side.
Specifically, in the thin film transistor 1, a source electrode 3 and a drain electrode 4 are provided separately on a substrate 2, an organic semiconductor layer 5 is provided in contact with the source electrode 3 and the drain electrode 4, and A first gate insulating layer 61 is provided in contact with the organic semiconductor layer 5. Further, a second gate insulating layer 62 is provided so as to cover the source electrode 3, the drain electrode 4, the organic semiconductor layer 5 and the first gate insulating layer 61, and at least on the second gate insulating layer, A gate electrode 7 is provided so as to overlap with a region between the source electrode 3 and the drain electrode 4.

In the thin film transistor 1, a region between the source electrode 3 and the drain electrode 4 in the organic semiconductor layer 5 is a channel region 51 in which carriers move. Hereinafter, in this channel region 51, the length in the carrier moving direction, that is, the distance between the source electrode 3 and the drain electrode 4 is the channel length L, and the length in the direction orthogonal to the channel length L direction is the channel width W. say.
Such a thin film transistor 1 is a thin film transistor having a structure in which the source electrode 3 and the drain electrode 4 are provided on the substrate 2 side with respect to the gate electrode 7 via the gate insulating layers 61 and 62, that is, a thin film transistor having a top gate structure. .

Hereinafter, each part which comprises the thin-film transistor 1 is demonstrated sequentially.
The substrate 2 supports each layer (each part) constituting the thin film transistor 1. Examples of the substrate 2 include a glass substrate, polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymethyl methacrylate (PMMA), polycarbonate (PC), polyethersulfone (PES), and aromatic polyester (liquid crystal polymer). Or the like, a plastic substrate (resin substrate), a quartz substrate, a silicon substrate, a gallium arsenide substrate, or the like can be used. When the thin film transistor 1 is given flexibility, a resin substrate is selected as the substrate 2.

An underlayer may be provided on the substrate 2. As the underlayer, for example, the purpose of preventing the diffusion of ions from the surface of the substrate 2, the purpose of improving the adhesion (bondability) between the source electrode 3 and the drain electrode 4 and the substrate 2, an organic semiconductor as described later It is provided for the purpose of improving the affinity with the material (first material) for forming the layer 5.
This underlayer can be made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), polyimide, polyamide, a polymer insolubilized by crosslinking, or the like.

On the substrate 2, a source electrode 3 and a drain electrode 4 are juxtaposed at a predetermined distance along the channel length L direction.
Examples of the constituent material of the source electrode 3 and the drain electrode 4 include metal materials such as Pd, Pt, Au, W, Ta, Mo, Al, Cr, Ti, Cu or alloys containing them, and the like. It is preferable to select appropriately according to the carrier moving the region.
For example, in the case of a p-channel thin film transistor in which holes move in the channel region, it is preferable to use Pd, Pt, Au, Ni, Cu, or an alloy containing these metals having a relatively large work function.

In addition to the above metal materials, the constituent materials of the source electrode 3 and the drain electrode 4 include conductive oxides such as ITO, FTO, ATO, SnO ₂ , carbon materials such as carbon black, carbon nanotubes, fullerenes, and polyacetylene. , Polypyrrole, polythiophene such as PEDOT (poly-ethylenedioxythiophene), polyaniline, poly (p-phenylene), poly (p-phenylenevinylene), polyfluorene, polycarbazole, polysilane, or derivatives thereof, etc. These can be used, and one or more of these can be used in combination.
The conductive polymer material is usually used in a state where it is doped with a polymer such as iron chloride, iodine, an inorganic acid, an organic acid, or polystyrene sulfonic acid, and imparted with conductivity.

The average thickness of the source electrode 3 and the drain electrode 4 is not particularly limited, but is preferably about 30 to 300 nm, and more preferably about 50 to 150 nm.
The distance (separation distance) between the source electrode 3 and the drain electrode 4, that is, the channel length L is preferably about 2 to 30 μm, and more preferably about 5 to 20 μm. When the channel length L is made smaller than the lower limit value, an error occurs in the channel length between the obtained thin film transistors 1, and the characteristics (transistor characteristics) may vary. On the other hand, when the channel length L is made larger than the upper limit value, the absolute value of the threshold voltage is increased, the drain current value is decreased, and the characteristics of the thin film transistor 1 may be insufficient.

The channel width W is preferably about 0.1 to 5 mm, and more preferably about 0.5 to 3 mm. If the channel width W is made smaller than the lower limit value, the drain current value becomes small and the characteristics of the thin film transistor 1 may be insufficient. On the other hand, if the channel width W is larger than the upper limit value, the thin film transistor 1 is increased in size and may increase parasitic capacitance and increase leakage current to the gate electrode 7 via the gate insulating layers 61 and 62. is there.
An organic semiconductor layer 5 is provided on the substrate 2 so as to cover between the source electrode 3 and the drain electrode 4 and a part of the source electrode 3 and the drain electrode 4.

The organic semiconductor layer 5 is composed mainly of an organic semiconductor material (an organic material that exhibits semiconducting electrical conduction).
The organic semiconductor layer 5 is preferably oriented so as to be substantially parallel to the channel length L direction at least in the channel region 51. As a result, the carrier mobility in the channel region 51 is high, and as a result, the thin film transistor 1 has a higher operating speed.

  Examples of organic semiconductor materials include naphthalene, anthracene, tetracene, pentacene, hexacene, phthalocyanine, perylene, hydrazone, triphenylmethane, diphenylmethane, stilbene, arylvinyl, pyrazoline, triphenylamine, triarylamine, oligothiophene, phthalocyanine or Low molecular organic semiconductor materials such as these derivatives, poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, polythiophene, polyalkylthiophene, polyhexylthiophene, poly (p-phenylene vinylene), polytinylene vinylene, Polyarylamine, pyrene formaldehyde resin, ethylcarbazole formaldehyde resin, fluorene-bithiophene copolymer, fluorene-ary Examples thereof include high molecular organic semiconductor materials (conjugated polymer materials) such as amine copolymers or derivatives thereof, and one or more of these can be used in combination. It is preferable to use a material mainly composed of a molecular organic semiconductor material (conjugated polymer material). The conjugated polymer material has a particularly high carrier mobility due to its unique electron cloud spread.

Of these, fluorene-bithiophene copolymer, fluorene-arylamine copolymer are used as high-molecular organic semiconductor materials (conjugated polymer materials) because they are not easily oxidized in the air and are stable. It is particularly preferable to use a compound, a polyarylamine or a derivative containing at least one of these derivatives as a main component.
In addition, the organic semiconductor layer 5 composed mainly of a polymer organic semiconductor material can be reduced in thickness and weight, and has excellent flexibility. Therefore, the thin film transistor can be used as a switching element of a flexible display. Suitable for applications.

The average thickness of the organic semiconductor layer 5 is preferably about 1 to 200 nm, and more preferably about 10 to 100 nm.
Note that the organic semiconductor layer 5 is not limited to a structure provided so as to cover the source electrode 3 and the drain electrode 4, and is provided at least in a region (channel region 51) between the source electrode 3 and the drain electrode 4. It only has to be.

A first gate insulating layer 61 is provided on the organic semiconductor layer 5, and a second gate insulating layer 62 is provided so as to cover them.
The gate insulating layers 61 and 62 insulate the gate electrode 7 from the source electrode 3 and the drain electrode 4, respectively.
Each of the gate insulating layers 61 and 62 is preferably mainly composed of an organic insulating material (particularly, an organic polymer material having insulating properties). The gate insulating layers 61 and 62 mainly made of an insulating organic polymer material are easy to form and can also improve the adhesion to the organic semiconductor layer 5.

  Examples of such an organic polymer material having an insulating property include acrylic resins such as polystyrene, polyimide, polyamideimide, polyvinylphenylene, polycarbonate (PC), and polymethyl methacrylate (PMMA), and polytetrafluoroethylene (PTFE). ), Olefin resins such as polyethylene, polypropylene, polyisobutylene, and polybutene, and derivatives of these polymers. Alternatively, two or more kinds can be used in combination.

In particular, since the first gate insulating layer 61 affects the carrier movement performance at the interface of the organic semiconductor layer 5, it is preferable to select a material that is advantageous for improving the carrier movement performance as the constituent material. preferable. In the present invention, the organic insulating material (the second material for forming the first gate insulating layer 61) constituting the first gate insulating layer 61 is the organic semiconductor layer 5 as will be described later. A material that is incompatible with the material (first material) to be used and is soluble in the same solvent as the first material is selected.
Hereinafter, the first material for forming the organic semiconductor layer 5 is referred to as “organic semiconductor layer forming material”, and the second material for forming the first gate insulating layer 61 is “ This is referred to as “first gate insulating layer forming material”.

  As a constituent material of the first gate insulating layer 61 (first gate insulating layer forming material), for example, polystyrene or a polymer having a side chain (for example, an alkyl side chain) in the main chain of polystyrene, a main component of polyvinyl is used. A polymer having a side chain in the chain (for example, an alkyl side chain, a side chain containing cyclohexane, etc.), an acrylic polymer such as polymethyl methacrylate (PMMA), an olefin resin such as polyethylene, polypropylene, or polybutene, or Copolymers containing these are preferred.

  On the other hand, as the constituent material of the second gate insulating layer 62, it is preferable to select a material having a relatively high dielectric constant in consideration of the insulation performance between the source electrode 3, the drain electrode 4, and the gate electrode 7. As such an organic insulating material, for example, a phenolic resin such as polyvinylphenol or a novolac resin, a cyano group-containing resin (a resin containing a cyano group), an epoxy resin, a polyimide, an amide resin, or the like is preferable.

The average thickness of the first gate insulating layer 61 is preferably about 1 to 300 nm, and more preferably about 10 to 100 nm. Further, the thickness (average) of the second gate insulating layer 62 is not particularly limited, but is preferably about 10 to 5000 nm, and more preferably about 100 to 1000 nm.
By making the thicknesses of the first gate insulating layer 61 and the second gate insulating layer 62 within the above ranges, the thin film transistor 1 is prevented from being enlarged (particularly, the thickness is increased). The source electrode 3 and the drain electrode 4 can be reliably insulated from the gate electrode 7.
Note that the second gate insulating layer 62 is not limited to a single layer structure, and may have a multilayer structure.
In addition, as a constituent material of the second gate insulating layer 62, for example, an inorganic insulating material such as SiO ₂ can be used.

A gate electrode 7 is provided on the second gate insulating layer 62.
As the constituent material of the gate electrode 7, the same materials as those mentioned for the source electrode 3 and the drain electrode 4 can be used.
The average thickness of the gate electrode 7 is not particularly limited, but is preferably about 0.1 to 5000 nm, more preferably about 1 to 5000 nm, and still more preferably about 10 to 5000 nm.

In the thin film transistor 1 as described above, the amount of current flowing between the source electrode 3 and the drain electrode 4 is controlled by changing the voltage applied to the gate electrode 7.
That is, in the OFF state in which no voltage is applied to the gate electrode 7, even if a voltage is applied between the source electrode 3 and the drain electrode 4, almost no carriers are present in the organic semiconductor layer 5, so that a very small current Only flows. On the other hand, in the ON state in which a voltage is applied to the gate electrode 7, charge is induced in the portion of the organic semiconductor layer 5 facing the first gate insulating layer 61 (near the interface with the first gate insulating layer 61). The carrier flow path is formed in the channel region 51. When a voltage is applied between the source electrode 3 and the drain electrode 4 in this state, a current flows through the channel region 51.

Such a thin film transistor 1 is manufactured as follows, for example.
Hereinafter, a method for manufacturing the thin film transistor 1 (a first embodiment of a method for manufacturing a thin film transistor of the present invention) will be described.
<< Method for Manufacturing Thin Film Transistor of First Configuration >>
2 to 5 are views for explaining a method of manufacturing the thin film transistor shown in FIG. 1, respectively. FIGS. 2 and 3 are longitudinal sectional views, and FIGS. 4 and 5 are schematic views. In the following description, the upper side in FIGS. 2 to 5 is referred to as “upper” and the lower side is referred to as “lower”.
The method of manufacturing the thin film transistor 1 includes: [A1] source and drain electrode formation step, [A2] surface treatment step, [A3] organic semiconductor layer and first gate insulating layer formation step, and [A4] second A gate insulating layer forming step, and [A5] a gate electrode forming step. Hereinafter, each of these steps will be described sequentially.

[A1] Source and Drain Electrode Formation Step A substrate 2 is prepared as shown in FIG. 2A, and a source electrode 3 and a drain electrode 4 are formed on the substrate 2.
First, as shown in FIG. 2B, a metal film (metal layer) 8 is formed on the substrate 2.
This includes, for example, chemical vapor deposition (CVD) such as plasma CVD, thermal CVD, and laser CVD, vacuum deposition, sputtering (low temperature sputtering), dry plating methods such as ion plating, electrolytic plating, immersion plating, and electroless plating. It can be formed by a wet plating method such as a thermal spraying method, a sol-gel method, a MOD method, or a metal foil bonding.

Next, a resist layer having a shape corresponding to the shape of the source electrode 3 and the drain electrode 4 is formed on the metal film 8 by photolithography. Using this resist layer as a mask, unnecessary portions of the metal film 8 are removed.
For the removal of the metal film 8, for example, one or more of physical etching methods such as plasma etching, reactive ion etching, beam etching, and optically assisted etching, and chemical etching methods such as wet etching are used. Can be used in combination.

Thereafter, by removing the resist layer, the source electrode 3 and the drain electrode 4 are obtained as shown in FIG.
The source electrode 3 and the drain electrode 4 are made of a liquid material such as a colloid liquid (dispersion) containing conductive particles or a liquid (solution or dispersion) containing a conductive polymer, for example. After forming the film by supplying the film, it can be formed by subjecting the film to post-treatment (for example, heating, irradiation with infrared rays, application of ultrasonic waves, etc.) as necessary.

  Examples of methods for supplying the liquid material onto the substrate 2 include dipping, spin coating, casting, micro gravure coating, gravure coating, bar coating, roll coating, wire bar coating, and dip coating. Methods, spray coating methods, screen printing methods, flexographic printing methods, offset printing methods, ink jet methods, microcontact printing methods, and the like, and one or more of these can be used in combination.

[A2] Surface Treatment Step Next, surface treatment is performed on the surface side of the substrate 2 on which the source electrode 3 and the drain electrode 4 are formed (surface side on which a liquid layer 9 described later is formed).
As the surface treatment, the affinity (wetting property) of the surfaces of the substrate 2, the source electrode 3 and the drain electrode 4 to the organic semiconductor layer forming material used in the next step [A3] is the same as that of the first gate insulating layer forming material. A process (affinity improving process) is performed so as to be higher than the affinity.

  Examples of such surface treatment include physical treatment such as oxygen plasma treatment, ammonia plasma treatment, fluorocarbon plasma treatment, various plasma treatments such as sulfur-containing gas plasma treatment, ultraviolet irradiation, and ion implantation (ion doping). And chemical treatment such as chemical modification treatment and thin film formation. These methods are appropriately selected according to the characteristics of the organic semiconductor layer forming material used in the next step [A3].

When the organic semiconductor layer forming material is higher in polarity than the first gate insulating layer forming material, the surface treatment includes, for example, oxygen plasma treatment, ammonia plasma treatment, ozone treatment, deep UV treatment, interface A hydrophilic treatment (lyophilic treatment) such as an adsorption treatment of an activator is preferably selected.
When the hydrophilic treatment is performed, the surfaces of the substrate 2, the source electrode 3 and the drain electrode 4 are hydrophilized. Therefore, the wettability of the organic semiconductor layer forming material with respect to the surfaces is determined by the first gate insulating layer forming material. Can be higher than wettability.

Further, as the surface treatment, a chemical modification treatment is performed in which a chemical structure (building unit) including a part of the compound constituting the organic semiconductor layer forming material is introduced to the surfaces of the substrate 2, the source electrode 3, and the drain electrode 4. Also, the wettability of the organic semiconductor layer forming material to the surface can be made higher than the wettability of the first gate insulating layer forming material.
For example, when the organic semiconductor layer forming material contains a thiophene compound, as shown in FIG. 4 (a), an alkyl chain having a thiophene at the terminal is introduced and a bithiophene compound is contained, as shown in FIG. As shown in b), a chemical modification treatment for introducing an alkyl chain having a bithiophene at its terminal is performed.
Further, when the organic semiconductor layer forming material contains a fluorene compound, as shown in FIG. 4 (c), an alkyl chain having a fluorene terminal is introduced and a triarylamine compound is contained. As shown in 4 (d), a chemical modification treatment is performed to introduce an alkyl chain having triphenylamine (triarylamine) at its terminal.

As a treatment agent (compound) used for these chemical modification treatments, for example, for a surface mainly composed of glass or SiO ₂ , an atomic group to be introduced is formed at one end with trimethylsilane, methylsilane, Those having a silane-containing moiety such as trichlorosilane at the other end can be used, and for the surface mainly composed of Au, Pt, etc., the atomic group to be introduced is at one end and the thiol Can be used at the other end.

Further, as the surface treatment, a thin film mainly composed of a compound of the same type as the compound constituting the organic semiconductor layer forming material (for example, the same compound, a compound containing a part thereof, or a derivative thereof) is formed on the substrate 2, Also by forming on the surfaces of the source electrode 3 and the drain electrode 4, the wettability of the organic semiconductor layer forming material to the surfaces can be made higher than the wettability of the first gate insulating layer forming material.
In this case, the thin film is preferably subjected to a treatment such as a heat treatment or a crosslinking reaction, or the thin film is mainly composed of a compound having a weight average molecular weight of 50000 or more. Thereby, it can prevent suitably that the formed thin film melt | dissolves with the solvent used in next process [A3].

The average thickness of the thin film to be formed is not particularly limited, but is preferably 5 nm or less, and more preferably 2 nm or less. If the thickness of the thin film is too thick, the carrier injection efficiency from the source electrode 3 to the organic semiconductor layer 5 may be impaired depending on the constituent material of the thin film.
Such a thin film can be easily formed by using a coating method such as spin coating.
In addition, the above surface treatment may be performed individually by 1 type, and may be performed combining arbitrary 2 or more types.

[A3] Organic Semiconductor Layer and First Gate Insulating Layer Forming Step Next, as shown in FIG. 3D, on the substrate 2 that has been subjected to surface treatment, between the source electrode 3 and the drain electrode 4 and The organic semiconductor layer 5 and the first gate insulating layer 61 are formed so as to cover a part of each electrode 3, 4.

[A3-1] First, an incompatible organic semiconductor layer forming material (first material), a first gate insulating layer forming material (second material), an organic semiconductor forming material, and a first A liquid material containing a solvent capable of dissolving both of the gate insulating layer forming materials is prepared, and the liquid material is supplied onto the substrate 2 to form the liquid layer 9 (first step).
As the organic semiconductor layer forming material, the organic semiconductor material as described above or a precursor thereof is used. Specifically, conjugated compounds such as oligothiophene, polythiophene, polyalkylthiophene, fluorene-bithiophene copolymer, fluorene-arylamine copolymer, polyarylamine, pentacene precursor molecule (oligomer, polymer) These can be used, and one or more of these can be used in combination. By using these organic semiconductor layer forming materials, the obtained organic semiconductor layer 5 has particularly high carrier mobility.
In addition, since these organic semiconductor layer forming materials have low compatibility with the first gate insulating layer forming material as described above, in the next step [A3-2], 1 can be reliably separated from the gate insulating layer forming material.

  Examples of the solvent include aromatic solvents such as benzene, xylene (dimethylbenzene), trimethylbenzene, tetramethylbenzene, and cyclohexylbenzene, halogenated solvents such as chlorobenzene and bromobenzene, and chloroform. It can be used alone or in combination (as a mixed solvent). Any of these solvents exhibits high solubility in the conjugated compound and the first gate insulating layer forming material.

  The mixing ratio of the organic semiconductor layer forming material and the first gate insulating layer forming material in the liquid material is preferably about 3: 1 to 1: 3 by weight, and 2: 1 to 1: 2. More preferred is the degree. By setting the mixing ratio of the organic semiconductor layer forming material and the first gate insulating layer forming material within the above range, the separation can be more reliably caused in the next step [A3-2]. .

  The total content of the organic semiconductor layer forming material and the first gate insulating layer forming material in the liquid material is preferably about 0.1 to 6% wt / vol, More preferably, it is about 4% wt / vol. If the total content of the organic semiconductor layer forming material and the first gate insulating layer forming material is too small, the proportion of the solvent increases accordingly, so that the solvent is removed in the next step [A3-2]. It takes a long time and may cause a decrease in production efficiency. On the other hand, if the total content of the organic semiconductor layer forming material and the first gate insulating layer forming material is too large, the organic semiconductor layer is formed in the liquid layer (liquid material) 9 in the next step [A3-2]. The forming material and the first gate insulating layer forming material are difficult to move (form a domain), and as a result, it may be difficult to separate them.

  As a method for supplying the liquid material (supply method), the coating method as described above can be used, but it is particularly preferable to use the ink jet method (droplet discharge method). According to the ink jet method (droplet discharge method), a liquid material can be accurately supplied to a predetermined position, and as a result, the organic semiconductor layer 5 and the first gate insulating layer 61 having a predetermined shape are formed with high dimensional accuracy. can do.

[A3-2] Next, by removing the solvent from the liquid material, a first domain mainly including the organic semiconductor layer forming material and a second mainly including the first gate insulating layer forming material are obtained. Are separated from each other in the thickness direction of the surface 90 on which the liquid layer 9 is formed and solidified to obtain the organic semiconductor layer 5 and the first gate insulating layer 61 (second step).
Hereinafter, this process will be described with reference to FIG. FIG. 5 is a schematic view showing a process in which the organic semiconductor layer and the first gate insulating layer are formed.

In FIG. 5, the solvent is removed from the liquid layer 9 (average thickness> 20t) formed by supplying the liquid material onto the substrate 2 (surface 90 on which the liquid layer 9 is formed), and solidified to have an average thickness. The process of forming the solidified layer 99 (the organic semiconductor layer 5 and the first gate insulating layer 61) of t is shown.
Note that the thickness of the liquid layer 9 in the drying process can be optically measured by a change in reflectance or ellipsometry.

As shown in FIG. 5A, immediately after the liquid layer 9 is formed by supplying the liquid material to the surface 90, in the liquid layer 9, the organic semiconductor layer forming material (indicated by a circle in the figure) The first gate insulating layer forming material (indicated by dots in the figure) exhibits a single phase dissolved almost uniformly.
Next, as shown in FIG. 5B, the concentration of the organic semiconductor layer forming material and the first gate in the liquid layer 9 as the solvent is removed from the liquid layer (liquid material) 9. The concentration of the insulating layer forming material gradually increases.

When the average thickness of the liquid layer 9 is in the range of 3t to 20t, the interaction between the compounds (molecules) constituting each material increases, and each material forms a separate phase and separates each other. Starts.
That is, in the matrix phase (phase mainly composed of a solvent) 93, a foam phase (first foam phase) 91 mainly containing an organic semiconductor layer forming material and a first gate insulating layer formation mainly. A large number of foam-like phases (second foam-like phases) 92 containing the working material are generated.
In this embodiment, since the affinity for the surface 90 is higher in the organic semiconductor layer forming material than in the first gate insulating layer forming material, the first foam phase 91 adheres to the surface 90 and the second The foamy phase 92 is suspended in the matrix phase 93.

  Then, as shown in FIG. 5C, when the solvent is further removed from the liquid layer 9 and the average thickness of the liquid layer 9 is in the range of 1.2 t to 10 t, the first foam phase 91 and the first The growth of the two foam phases 92 is promoted, and further, the first foam phases 91 and the second foam phases 92 are fused to each other, thereby mainly including the organic semiconductor layer forming material. A domain 91 ′ and a second domain 92 ′ mainly containing a first gate insulating layer forming material are grown.

At this time, the first domain 91 ′ grows in contact with the surface 90, the second domain 92 ′ grows so as to cover the first domain 91 ′, and the thickness direction of the liquid layer 9 Phase separation (vertical phase separation).
Furthermore, as shown in FIG. 5 (d), the solvent is removed from the liquid layer 9, and the solvent substantially does not exist in the liquid layer 9 (that is, the liquid layer 9 is solidified). A solidified layer 99 (average thickness t) composed of the first solidified layer 991 and the second solidified layer 992 is formed.
Thereafter, the solidified layers 991 and 992 may be subjected to heat treatment by heating, infrared irradiation, or the like, if necessary. Thereby, for example, when the organic semiconductor layer forming material is composed of a precursor of an organic semiconductor material, the precursor is reacted (formation of unsaturated bond, polymerization reaction, etc.) to form an organic semiconductor material. Can be changed.

In addition, by performing heat treatment, the first solidified layer 991 and the second solidified layer 992 can be melted or softened again, whereby the first solidified layer 991 and the second solidified layer 992 are obtained. Can be separated more reliably (these interfaces can be made clearer). As a result, the finally obtained thin film transistor 1 has more excellent characteristics.
The heat treatment conditions vary depending on the purpose of the heat treatment and are not particularly limited, but are preferably about 100 to 400 ° C. × 1 to 30 minutes, more preferably about 150 to 280 ° C. × 5 to 15 minutes.
The first solidified layer 991 constitutes the organic semiconductor layer 5, while the second solidified layer 992 constitutes the first gate insulating layer 61.

Through the above process, as shown in FIG. 3D, the organic semiconductor layer 5 and the first gate insulating layer 61 laminated in contact with the organic semiconductor layer 5 are formed. A channel region 51 is formed between the drain electrode 4 (region corresponding to the gate electrode 7).
In such a process, the method for removing the solvent from the liquid layer (liquid material) 9 includes a method using natural drying, a method using heating by a heater, a method using heating by infrared irradiation, and the like.

  The time required for solidifying the liquid layer 9 (the time until the liquid layer 9 becomes the solidified layer 99) should be long enough for the domain to grow, preferably 5 seconds or more, more preferably 10 seconds or more. If this time is too short, the liquid layer 9 is solidified (the solidified layer 99 is formed) before the domains 91 ′ and 92 ′ are sufficiently grown, and the domains 91 ′ and 92 ′ are separated. It may be difficult to perform (perpendicular phase separation). On the other hand, if the time is too long, not only the productivity is lowered, but the flatness of the completed thin film (solidified layer 99) is often poor.

  This time can be easily adjusted, for example, by using a high boiling point solvent as the solvent. As the high boiling point solvent, for example, those having a boiling point of about 110 to 270 ° C. are preferable, and those having a boiling point of about 140 to 210 ° C. are more preferable. Specifically, xylene, trimethylbenzene, tetramethylbenzene, cyclohexylbenzene or a mixed solvent containing these is preferable.

Note that the use of a high boiling point solvent makes it easy to adjust the characteristics (viscosity, etc.) of the liquid material to those suitable for the ink jet method when the ink jet method is applied as the liquid material supply method. There is also.
When a low boiling point solvent is used as the solvent, for example, the solvent is removed from the liquid layer 9 in the sealed space, and the solvent partial pressure, temperature, etc. in the sealed space at this time are controlled. The time can be adjusted to an appropriate range.

Further, by using a low boiling point solvent, it is possible to more reliably prevent the solvent from remaining in the obtained organic semiconductor layer 5 and the first gate insulating layer 61. As a result, the characteristics of the finally obtained thin film transistor 1 can be further improved.
As a low boiling point solvent, it is preferable that a boiling point is 110 degrees C or less, for example, and it is more preferable that it is about 60-100 degreeC. Specifically, toluene, chloroform, benzene, cyclohexane, methylcyclohexane, methylcyclopentane, cyclohexene, or a mixed solvent containing these is preferable.
Further, in the liquid layer 9, in order to phase-separate the organic semiconductor layer forming material and the first gate insulating layer forming material, their molecular weights are important.
Here, according to the The Flory-Huggins lattice model, the change amount ΔG of free energy accompanying mixing when two kinds of molecules are mixed is expressed by the following equation.

When the change amount ΔG of the free energy is positive, the mixed system is unstable and is likely to cause phase separation. When the change amount ΔG of the free energy is negative, the mixture system is stable and tends to be a single phase. . Therefore, in order to cause phase separation, it is necessary that the change amount ΔG of free energy is positive.
In this equation, n ₁ lnφ ₁ + n ₂ lnφ _{2 on} the right side represents mixed entropy and generally takes a negative value. Therefore, as the absolute value of the mixing entropy is larger, the change amount ΔG of free energy accompanying the mixing increases in the negative direction.

Here, in a compound (molecule) having a large molecular weight, the number of moles per unit volume is small, so n ₁ lnφ ₁ + n ₂ lnφ ₂ becomes a relatively small value, and the mixing entropy of free energy change ΔG The contribution is small.
Further, the interaction parameter x ₁₂ between the molecules reflects the affinity between molecules. If molecules each other are those incompatible with each other, the interaction parameter x ₁₂ generally takes a positive value, the change amount of free energy associated with mixing △ G is increased in the positive direction.

  From this point of view, in the liquid layer 9 made of a liquid material, the first bubble phase 91 mainly containing the organic semiconductor layer forming material and the second bubble mainly containing the first gate insulating layer forming material. In order to phase-separate the phase 92 (free energy change ΔG is a positive value), the organic semiconductor layer forming material and the first gate insulating layer forming material are not compatible with each other. In addition, at least one of these materials is preferably a polymer material. Thereby, the 1st foam phase 91 and the 2nd foam phase 92 can be phase-separated more reliably.

  For example, when the organic semiconductor layer forming material is a polymer material, the weight average molecular weight is preferably about 4,000 to 300,000, and more preferably about 8,000 to 100,000. On the other hand, when the first gate insulating layer forming material is a polymer material, the weight average molecular weight is preferably about 10,000 to 2,000,000, and more preferably about 30,000 to 1500,000.

When both the weight average molecular weight of the organic semiconductor layer forming material and the weight average molecular weight of the first gate insulating layer forming material are less than the lower limit, depending on the conditions for removing the solvent, the first foam phase There is a possibility that phase separation between 91 and the second foamy phase 92 becomes insufficient. On the other hand, those having a weight average molecular weight exceeding the upper limit may be difficult to dissolve in a solvent depending on the type of the solvent.
Further, the first foam phase 91 and the second foam phase 92 are phase-separated and separated into layers in the thickness direction of the liquid layer 9 (vertical phase separation) and the second domain 91 ′ and the second In order to grow into the domain 92 ′, it is preferable that one domain has higher wettability with respect to the surface 90 than the other domain.

In the present embodiment, in the step [2], the surface treatment (affinity improving treatment) is performed, and the affinity (wetting property) to the surface 90 of the organic semiconductor layer forming material is improved. The domain 91 ′ and the second domain 92 ′ can be more reliably subjected to vertical phase separation.
In particular, as shown in FIG. 5C, in the process (domain growth / fusion process) in which the average thickness of the liquid layer 9 is about 1.2 t to 10 t, one domain (in this embodiment, the first The contact angle θ of the domain 91 ′) with respect to the surface 90 is preferably as close to 0 ° as possible. Specifically, the contact angle θ is preferably 30 ° or less, and more preferably 15 ° or less. As a result, the first domain 91 ′ and the second domain 92 ′ can be more reliably subjected to vertical phase separation.

As the contact angle θ approaches 90 °, the first domain 91 ′ and the second domain 92 ′ tend to cause phase separation (in-plane phase separation) in the plane direction. .
Note that the contact angle θ of the first domain 91 ′ with respect to the surface 90 includes the contact angle θ1 and the surface tension γ _{GL1 of} a droplet obtained by dropping a liquid having the same composition as the first domain 91 ′ onto the surface 90, and the second The contact angle θ2 and the surface tension γ _{GL2 of} a droplet in which a liquid having the same composition as the domain 92 ′ is dropped on the surface 90, and the interfacial tension γ _L1L2 or interfacial energy between the first domain 91 ′ and the second domain 92 ′ The density can be measured and can be obtained from the measured value by the following formula.

[A4] Second Gate Insulating Layer Formation Step Next, as shown in FIG. 3E, the second gate is formed on the substrate 2 so as to cover the organic semiconductor layer 5 and the first gate insulating layer 61. An insulating layer 62 is formed.
The second gate insulating layer 62 is made of a liquid material (solution or dispersion) containing a material (insulating material or a precursor thereof) for forming the second gate insulating layer, the organic semiconductor layer 5 and the first gate insulating layer 62. After the film is formed so as to cover the gate insulating layer 61, a film is formed, and if necessary, post-treatment (for example, heating, irradiation of infrared rays, application of ultrasonic waves, etc.) is performed on the film. be able to.
As a method for supplying the liquid material onto the substrate 2, the same method as mentioned in the step [A1] can be used.

As the liquid (solvent or dispersion medium) used for preparing the liquid material, a liquid that does not swell or dissolve the organic semiconductor layer 5 and the first gate insulating layer 61 is preferably used.
Examples of such liquids include water, alcohols such as methanol, ethanol and 1-propanol, ketones such as acetone and methyl ethyl ketone, ethers and esters such as ethyl acetate, and the like. It can be used alone or as a mixed solution.

In addition, when the second gate insulating layer 62 is made of SiO ₂ (inorganic insulating material), for example, it can be formed as follows.
That is, in this case, the second gate insulating layer 62 is formed by supplying a liquid material such as polysilicate, polysiloxane, or polysilazane onto the substrate 2 to form a film, and then forming the film with oxygen and / or water vapor. It can be formed by heating in an atmosphere containing and generating SiO ₂ from the liquid material.
In this case, after a liquid material containing Si alkoxide is supplied onto the substrate 2 to form a film, the film is heated in an atmosphere containing oxygen to generate SiO ₂ from the liquid material (this method is , Also known as the sol-gel method).

[A5] Gate Electrode Formation Step Next, as shown in FIG. 3F, the gate electrode 7 is formed on the second gate insulating layer 62 so as to correspond to the channel region 51.
For example, the gate electrode 7 is formed by supplying a liquid material (solution or dispersion) containing a material (conductive material or a precursor thereof) for forming the gate electrode onto the second gate insulating layer 62. After the coating is formed, it can be formed by subjecting the coating to post-treatment (for example, heating, irradiation with infrared rays, application of ultrasonic waves, etc.) as necessary.

As a method for supplying the liquid material onto the second gate insulating layer 62, a method similar to that described in the step [A1] can be used, but an inkjet method is particularly preferable. According to the inkjet method, the gate electrode 7 having a predetermined shape can be easily and reliably formed.
Through the above steps, the thin film transistor 1 shown in FIG. 1 is obtained.

According to the manufacturing method as described above, the organic semiconductor layer 5 and the upper layer (first gate insulating layer 61) are formed in the same process, so that the organic semiconductor layer 5 is formed into the upper layer (first gate insulating layer). 61) The problem of dissolution / swelling by the solvent or the like does not occur.
In addition, since the organic semiconductor layer forming material and the first gate insulating layer forming material are not compatible with each other and satisfy the condition that they are dissolved in a common solvent, the selection range of materials is wide. The most suitable material can be selected with emphasis on the function of each layer.

Therefore, according to the manufacturing method as described above, the thin film transistor 1 having excellent performance can be easily manufactured.
In the present embodiment, when providing a base layer on the substrate 2, the constituent material of the base layer and the constituent materials of the source electrode 3 and the drain electrode 4 are compatible with the organic semiconductor layer forming material, respectively. By selecting a material having high property (wetting property), the surface treatment step of the step [A2] can be omitted.

<< Second Configuration of Thin Film Transistor >>
Next, a second configuration (second embodiment) of the thin film transistor of the present invention will be described.
FIG. 6 is a longitudinal sectional view showing a thin film transistor having a second configuration. In the following description, the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”.
Hereinafter, the second configuration and the second manufacturing method of the thin film transistor will be described. However, the difference from the first configuration and the difference from the first manufacturing method will be mainly described, and the same matters will be described. Is omitted.

The thin film transistor of the second configuration is the same as the thin film transistor of the first configuration except for the order of the layers constituting the thin film transistor.
That is, the thin film transistor 11 shown in FIG. 6 is provided on the substrate 2 and includes the gate electrode 7, the second gate insulating layer 62, the first gate insulating layer 61, the organic semiconductor layer 5, and the source electrode. 3 and the drain electrode 4 are laminated in this order from the substrate 2 side.

  Specifically, the gate electrode 7 is provided on the substrate 2, and the second gate insulating layer 62 is provided so as to cover the gate electrode 7. Further, a first gate insulating layer 61 and an organic semiconductor layer 5 are provided on the second gate insulating layer 62 so as to overlap the gate electrode 7, and further, the first gate insulating layer 61, the organic semiconductor layer 5, A source electrode 3 and a drain electrode 4 are separately provided at both ends of the laminate. The gate electrode 7 is provided at a position overlapping at least the region between the source electrode 3 and the drain electrode 4.

In the thin film transistor 11, a region between the source electrode 3 and the drain electrode 4 in the organic semiconductor layer 5 is a channel region 51 in which carriers move.
Such a thin film transistor 11 is a thin film transistor having a configuration in which the gate electrode 4 is provided on the substrate 2 side of the source electrode 3 and the drain electrode 4 via the gate insulating layers 61 and 62, that is, a bottom gate thin film transistor. .

The configuration (component material, dimensions, etc.) of each part of the thin film transistor 11 is the same as that of the thin film transistor 1 of the first configuration.
Such a thin film transistor 11 is manufactured as follows, for example.
Hereinafter, a manufacturing method of the thin film transistor 11 (second embodiment of the manufacturing method of the thin film transistor of the present invention) will be described.

<< Method for Producing Second Configuration Thin Film Transistor >>
7 and 8 are views (longitudinal sectional views) for explaining a method of manufacturing the thin film transistor shown in FIG. In the following description, the upper side in FIGS. 7 and 8 is referred to as “upper” and the lower side is referred to as “lower”.
The manufacturing method of the thin film transistor 11 includes: [B1] gate electrode forming step, [B2] second gate insulating layer forming step, [B3] first gate insulating layer and organic semiconductor layer forming step, and [B4] gate. An electrode forming step. Hereinafter, each of these steps will be described sequentially.

[B1] Gate Electrode Formation Step A substrate 2 is prepared as shown in FIG. 7A, and a gate electrode 7 as shown in FIG.
The gate electrode 7 can be formed in the same manner as in the step [A1].

[B2] Second Gate Insulating Layer Formation Step Next, as shown in FIG. 7C, a second gate insulating layer 62 is formed on the substrate 2 so as to cover the gate electrode 7.
The second gate insulating layer 62 can be formed in the same manner as in the step [A4].
In this embodiment, as the constituent material (insulating material) of the second gate insulating layer 62, the affinity (wetting) to the first gate insulating layer forming material is higher than the organic semiconductor layer forming material used in the next step [B3]. Select the one with high characteristics.

  When the above-described materials for forming the first gate insulating layer are used, examples of the constituent material of the second gate insulating layer 62 include olefin resins such as polyethylene, polypropylene, and polybutene, Examples thereof include acrylic resins such as methyl methacrylate (PMMA), polystyrene, and the like, and one or more of these can be used in combination.

Among these, when a polymer is used as the insulating material, it is preferable to use a polymer having a weight average molecular weight of 50000 or more or to form a crosslinked structure. Thereby, it is possible to suitably prevent the second gate insulating layer 62 from being dissolved by the solvent used in the next step [B3].
Instead of forming the second gate insulating layer 62, a surface treatment is performed so that the affinity (wetting property) to the first gate insulating layer forming material is higher than that of the organic semiconductor layer forming material. You may do it.

When the above-described materials for forming the first gate insulating layer are used, the surface treatment includes treatment with an alkyl group-containing coupling agent, hydrocarbon plasma treatment, plasma treatment with an inert gas, organic Examples of the treatment include reducing the polarity, such as washing with a solvent and adsorption treatment of an organic substance.
In the present embodiment, the process in this step [B2] corresponds to an affinity improvement process.

[B3] Step of Forming First Gate Insulating Layer and Organic Semiconductor Layer Next, as shown in FIG. 8D, the first gate is overlaid on the second gate insulating layer 62 so as to overlap the gate electrode 7. The insulating layer 61 and the organic semiconductor layer 5 are formed.
The first gate insulating layer 61 and the organic semiconductor layer 5 can be formed in the same manner as in the step [A3].
In the present embodiment, since the affinity of the second gate insulating layer 62 with the first gate insulating layer forming material is higher than the affinity with the organic semiconductor layer forming material, the second gate insulating layer 62 side The first gate insulating layer 61 is formed, and the organic semiconductor layer 5 is stacked on the first gate insulating layer 61.

[B4] Source and Drain Electrode Forming Step Next, as shown in FIG. 8E, the organic semiconductor layer 5 is provided at both ends of the stacked body of the first gate insulating layer 61 and the organic semiconductor layer 5, respectively. A source electrode 3 and a drain electrode 4 that are in contact with each other are formed.
The source electrode 3 and the drain electrode 4 can be formed in the same manner as in the step [A5].
Through the steps as described above, the thin film transistor 11 shown in FIG. 6 is obtained.
Also by the thin film transistor having the second configuration and the manufacturing method thereof, the same operation and effect as the thin film transistor having the first configuration and the manufacturing method can be obtained.

<Electronic device>
Next, an electrophoretic display device will be described as an example of an electronic device in which an active matrix device including the thin film transistors 1 and 11 as described above is incorporated.
FIG. 9 is a longitudinal sectional view showing an embodiment in which the electronic device of the present invention is applied to an electrophoretic display device, and FIG. 10 is a block diagram showing a configuration of an active matrix device included in the electrophoretic display device shown in FIG. It is.

An electrophoretic display device 20 shown in FIG. 9 includes an active matrix device (a thin film transistor circuit of the present invention) 30 provided on a substrate 50 and an electrophoretic display unit 40 electrically connected to the active matrix device 30. It is configured.
As shown in FIG. 10, the active matrix device 30 includes a plurality of data lines 31 orthogonal to each other, a plurality of scanning lines 32, and a thin film transistor 1 provided near each intersection of the data lines 31 and the scanning lines 32. , 11.
The gate electrodes 7 of the thin film transistors 1 and 11 are connected to the scanning line 32, the source electrode 3 is connected to the data line 31, and the drain electrode 4 is connected to a pixel electrode (individual electrode) 41 described later.

As shown in FIG. 9, the electrophoretic display unit 40 includes a pixel electrode 41, a microcapsule 42, a transparent electrode (common electrode) 43, and a transparent substrate 44 that are sequentially stacked on a substrate 50. Yes.
The microcapsule 42 is fixed between the pixel electrode 41 and the transparent electrode 43 by a binder material 45.

The pixel electrodes 41 are divided so as to be regularly arranged in a matrix, that is, vertically and horizontally.
In each capsule 42, an electrophoretic dispersion liquid 420 including a plurality of types of electrophoretic particles having different characteristics, and in this embodiment, two types of electrophoretic particles 421 and 422 having different charges and colors (hue) are encapsulated. Has been.

In the electrophoretic display device 20, when a selection signal (selection voltage) is supplied to one or a plurality of scanning lines 32, the thin film transistor connected to the scanning line 32 to which the selection signal (selection voltage) is supplied. 1 and 11 are turned ON.
Thereby, the data line 31 and the pixel electrode 41 connected to the thin film transistors 1 and 11 are substantially conducted. At this time, if desired data (voltage) is supplied to the data line 31, this data (voltage) is supplied to the pixel electrode 41.

As a result, an electric field is generated between the pixel electrode 41 and the transparent electrode 43, and the electrophoretic particles 421 and 422 are either one of the electrophoretic particles 421 and 422 depending on the direction and strength of the electric field and the characteristics of the electrophoretic particles 421 and 422. Electrophoresis in the direction of the electrode.
On the other hand, when the supply of the selection signal (selection voltage) to the scanning line 32 is stopped from this state, the thin film transistors 1 and 11 are turned off, and the data line 31 and the pixel electrode 41 connected to the thin film transistors 1 and 11 are not connected. It becomes a non-conductive state.

Therefore, by supplying and stopping the selection signal to the scanning line 32 or by appropriately combining the supply and stop of data to the data line 31, the display surface side (transparent substrate 44 side) of the electrophoretic display device 20 is performed. A desired image (information) can be displayed.
In particular, in the electrophoretic display device 20 of the present embodiment, it is possible to display a multi-tone image by making the colors of the electrophoretic particles 421 and 422 different.

In addition, since the electrophoretic display device 20 of the present embodiment includes the active matrix device 30, the thin film transistors 1 and 11 connected to the specific scanning line 32 can be selectively turned on / off. This problem is unlikely to occur, and the circuit operation can be speeded up, so that high-quality images (information) can be obtained.
In addition, since the electrophoretic display device 20 of the present embodiment operates with a low driving voltage, power saving can be achieved.
Note that the electronic device of the present invention is not limited to the application to the electrophoretic display device 20, and can be applied to a liquid crystal display device, an organic or inorganic EL display device, and the like.

<Electronic equipment>
Such an electrophoretic display device 20 can be incorporated into various electronic devices. Hereinafter, the electronic apparatus of the present invention including the electrophoretic display device 20 will be described.
<< Electronic Paper >>
First, an embodiment when the electronic apparatus of the present invention is applied to electronic paper will be described.
FIG. 11 is a perspective view showing an embodiment when the electronic apparatus of the present invention is applied to electronic paper.
An electronic paper 600 shown in this figure includes a main body 601 composed of a rewritable sheet having the same texture and flexibility as paper, and a display unit 602.
In such an electronic paper 600, the display unit 602 includes the electrophoretic display device 20 as described above.

<< Display >>
Next, an embodiment when the electronic apparatus of the present invention is applied to a display will be described.
12A and 12B are diagrams showing an embodiment in which the electronic apparatus of the present invention is applied to a display. FIG. 12A is a cross-sectional view and FIG. 12B is a plan view.
A display 800 shown in this figure includes a main body 801 and an electronic paper 600 that is detachably attached to the main body 801. The electronic paper 600 has the same configuration as described above, that is, the configuration shown in FIG.

  The main body 801 has an insertion port 805 into which the electronic paper 600 can be inserted on the side (right side in the drawing), and two pairs of conveying rollers 802a and 802b are provided inside. When the electronic paper 600 is inserted into the main body 801 through the insertion port 805, the electronic paper 600 is installed in the main body 801 in a state of being sandwiched between the pair of conveyance rollers 802a and 802b.

Further, a rectangular hole 803 is formed on the display surface side of the main body 801 (the front side in the drawing (b) below), and a transparent glass plate 804 is fitted into the hole 803. Thereby, the electronic paper 600 installed in the main body 801 can be viewed from the outside of the main body 801. That is, in the display 800, the display surface is configured by visually recognizing the electronic paper 600 installed in the main body 801 on the transparent glass plate 804.
In addition, a terminal portion 806 is provided at the leading end portion (left side in the drawing) of the electronic paper 600, and the terminal portion with the electronic paper 600 installed on the main body portion 801 is provided inside the main body portion 801. A socket 807 to which 806 is connected is provided. A controller 808 and an operation unit 809 are electrically connected to the socket 807.

In such a display 800, the electronic paper 600 is detachably installed on the main body 801, and can be carried and used while being detached from the main body 801.
In such a display 800, the electronic paper 600 is configured by the electrophoretic display device 20 as described above.
Note that the electronic apparatus of the present invention is not limited to the application to the above, and for example, a television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, an electronic Examples include newspapers, word processors, personal computers, workstations, videophones, POS terminals, and devices equipped with touch panels. The electrophoretic display device 20 can be applied to the display units of these various electronic devices. is there.

The method for manufacturing a thin film transistor, the thin film transistor, the thin film transistor circuit, the electronic device, and the electronic device of the present invention have been described above, but the present invention is not limited to these.
For example, in the above embodiment, two layers of the first gate insulating layer and the second gate insulating layer are provided, but the second gate insulating layer may be omitted.

Further, the source electrode and the drain electrode may be formed so that both have a comb shape and the teeth mesh with each other.
Moreover, the manufacturing method of the thin-film transistor of this invention can also add the process of 1 or 2 or more arbitrary purposes to the process as mentioned above as needed.
In addition, the structure of each part of the thin film transistor, the electronic device, and the electronic apparatus of the present invention can be replaced with an arbitrary one that can exhibit the same function, or an arbitrary configuration can be added.

Next, specific examples of the present invention will be described.
1. Production of Thin Film Transistor (Example 1)
<1-1> First, a glass substrate having an average thickness of 1 mm was prepared, and a source electrode and a drain electrode made of Au were formed on the glass substrate.
The average thickness of the obtained source and drain electrodes was 100 nm, the distance between the source and drain electrodes (channel length L) was 10 μm, and the channel width W was 1 mm.

<1-2> Next, an oxygen plasma treatment (atmospheric pressure oxygen plasma treatment) was performed under atmospheric pressure on the glass substrate on which the source electrode and the drain electrode were formed. Thereby, surface treatment was performed on the glass substrate.
The conditions of atmospheric pressure oxygen plasma were RF power 0.05 W / cm ² , oxygen gas flow rate 80 sccm, and processing time 150 seconds.

  <1-3> Next, F8T2 (fluorene-bithiophene copolymer, weight average molecular weight 10,000) is 1% wt / vol as the organic semiconductor layer forming material, and polystyrene (weight average) as the first gate insulating layer forming material. A liquid material was prepared by dissolving in 1, 2,4-trimethylbenzene (boiling point 168 ° C.) so that the molecular weight 500000) was 1% wt / vol.

This liquid material was supplied onto a glass substrate that had been surface-treated by an ink jet method (droplet diameter: 25 μm) to form a liquid layer (average thickness 2100 nm).
Thereafter, the liquid layer was naturally dried at 25 ° C. (the solvent was removed) and solidified. As a result, an organic semiconductor layer and a first gate insulating layer (solidified layer) were obtained.
The drying time (time required for solidifying the liquid layer) was 15 seconds, and the average thickness of the solidified layer was 100 nm.

In the drying process of the liquid layer, when the average thickness of the liquid layer reached 800 nm, the contact angle θ of the domain mainly containing F8T2 with respect to the surface of the glass substrate was 12.5 °.
Moreover, the average thickness of the obtained organic-semiconductor layer and the 1st gate insulating layer was 50 nm and 50 nm, respectively.

<1-4> Next, polyvinylphenol (weight average molecular weight 20000) was dissolved in 1-propanol so as to be 5% wt / vol to prepare a liquid material.
This liquid material was supplied by spin coating (2400 rpm) onto a substrate on which the organic semiconductor layer and the first gate insulating layer were formed, and then dried at 60 ° C. for 10 minutes. Thus, a second gate insulating layer was formed.
Note that the thickness of the obtained second gate insulating layer on the first gate insulating layer was 450 nm. That is, the average thickness of the portion that substantially functions as the gate insulating layer was 500 nm.

<1-5> Next, an aqueous dispersion of PEDOT (polyethylenedioxythiophene) is applied to the portion corresponding to the region between the source electrode and the drain electrode on the second gate insulating layer by an inkjet method (liquid And then dried at 80 ° C. for 10 minutes. Thereby, a gate electrode was formed.
In addition, the average thickness of the obtained gate electrode was 100 nm.
Through the above steps, the thin film transistor shown in FIG. 1 was manufactured.

(Example 2)
A thin film transistor was manufactured in the same manner as in Example 1 except for the following.
<2-1> First, the polyimide precursor was dissolved in N-methyl-2-pyrrolidone so as to be 6% wt / vol to prepare a liquid material.
This liquid material was supplied onto a glass substrate by spin coating (2400 rpm), and then heat-treated at 250 ° C. for 30 minutes. Thereby, a polyimide film was formed.
The average thickness of the polyimide film was 400 nm.
Next, a source electrode and a drain electrode made of Au were formed on the polyimide film.

<2-2> Steps similar to those in step <1-2> were omitted.
<2-3> A step similar to the above step <1-3> was performed.
In the drying process of the liquid layer, when the average thickness of the liquid layer reaches 800 nm, the contact angle θ of the domain mainly containing F8T2 with respect to the surface of the glass substrate (polyimide film) is 9.5 °. there were.
<2-4> Steps similar to the above step <1-4> were performed.
<2-5> Steps similar to the above step <1-5> were performed.

(Example 3)
A thin film transistor was manufactured in the same manner as in Example 1 except that in the step <1-3>, the solidified layer was heat-treated at 160 ° C. for 10 minutes.
Example 4
A thin film transistor was manufactured in the same manner as in Example 1 except for the following.
<4-1> First, a polycarbonate substrate having an average thickness of 1 mm was prepared, and a source electrode and a drain electrode made of Au were formed on the polycarbonate substrate.

<4-2> Instead of the atmospheric pressure oxygen plasma treatment, hydrogen sulfide plasma (atmospheric pressure hydrogen sulfide plasma treatment) was performed under atmospheric pressure on the polycarbonate substrate on which the source electrode and the drain electrode were formed. Thereby, the surface treatment was performed on the polycarbonate substrate.
The conditions for the atmospheric pressure hydrogen sulfide plasma treatment were RF power 0.05 W / cm ² , hydrogen sulfide gas flow rate 80 sccm, and treatment time 150 seconds.

<4-3> Next, 1% wt / vol of polyhexylthiophene (weight average molecular weight 20000) as the organic semiconductor layer forming material, and polymethyl methacrylate (weight average molecular weight 70,000) as the first gate insulating layer forming material Were dissolved in chlorobenzene (boiling point: 132 ° C.) to prepare liquid materials so as to be 1% wt / vol.
This liquid material was supplied onto a polycarbonate substrate subjected to surface treatment by an ink jet method (droplet diameter: 25 μm) to form a liquid layer (average thickness 2500 nm).
Thereafter, the liquid layer was naturally dried at 25 ° C. (the solvent was removed) and solidified.
The drying time (time required for solidifying the liquid layer) was 10 seconds, and the average thickness of the solidified layer was 100 nm.
Further, in the drying process of the liquid layer, when the average thickness of the liquid layer reached 800 nm, the contact angle θ of the domain mainly containing polyhexylthiophene with respect to the surface of the polycarbonate substrate was 15 °.
Next, the solidified layer was heat-treated at 180 ° C. for 5 minutes. Thereby, an organic semiconductor layer and a first gate insulating layer were obtained.
In addition, the average thickness of the obtained organic-semiconductor layer and the 1st gate insulating layer was 50 nm and 50 nm, respectively.
<4-4> Steps similar to the above step <1-4> were performed.
<4-5> Steps similar to the above step <1-5> were performed.

(Example 5)
A thin film transistor was manufactured in the same manner as in Example 4 except for the following.
<5-1> A step similar to the above step <4-1> was performed.
<5-2> Next, a liquid material was prepared by dissolving polyphenylamine (weight average molecular weight 60000) in toluene so as to be 0.1% wt / vol.
This liquid material was supplied by spin coating (2400 rpm) onto a polycarbonate substrate on which a source electrode and a drain electrode were formed, and then dried at 150 ° C. for 10 minutes. Thereby, the surface treatment was performed on the polycarbonate substrate.
The average thickness of the obtained polyphenylamine film was 2 nm.

<5-3> Next, 1% wt / vol of polyphenylamine (weight average molecular weight 8000) is used as the organic semiconductor layer forming material, and polystyrene (weight average molecular weight 500000) is 1 as the first gate insulating layer forming material. Liquid materials were prepared by dissolving in o-xylene (boiling point 144 ° C.) so as to be% wt / vol.
This liquid material is supplied onto a polycarbonate substrate having been subjected to surface treatment by an ink jet method (droplet diameter is 25 μm) to form a liquid layer (average thickness of 2500 nm). The mixture was naturally dried (the solvent was removed) and solidified. As a result, an organic semiconductor layer and a first gate insulating layer (solidified layer) were obtained.
The drying time (time required for solidifying the liquid layer) was 10 seconds, and the average thickness of the solidified layer was 100 nm.
Further, in the drying process of the liquid layer, when the average thickness of the liquid layer reaches 800 nm, the contact angle θ of the domain mainly containing polyphenylamine with respect to the surface of the polycarbonate substrate (polyphenylamine film) is 3 It was 5 °.
Moreover, the average thickness of the obtained organic-semiconductor layer and the 1st gate insulating layer was 50 nm and 50 nm, respectively.
<5-4> Steps similar to the above step <4-4> were performed.
<5-5> A gate electrode was formed in the same manner as in the above step <4-5> except that an aqueous dispersion of Ag fine particles was used instead of the aqueous dispersion of PEDOT.

(Example 6)
A thin film transistor was manufactured in the same manner as in Example 5 except for the following.
<6-1> The same step as the above step <5-1> was performed.
<6-2> A step similar to the above step <5-2> was performed.

<6-3> Next, the pentacene precursor is 1% wt / vol as the organic semiconductor layer forming material, and polystyrene (weight average molecular weight 500000) is 1% wt / vol as the first gate insulating layer forming material. As described above, liquid materials were prepared by dissolving in p-xylene (boiling point: 138 ° C.).
This liquid material was supplied onto a polycarbonate substrate subjected to surface treatment by an ink jet method (droplet diameter: 25 μm) to form a liquid layer (average thickness of 2000 nm).
Thereafter, the liquid layer was naturally dried at 25 ° C. (the solvent was removed) and solidified.

The drying time (time required for solidifying the liquid layer) was 10 seconds, and the average thickness of the solidified layer was 100 nm.
In the drying process of the liquid layer, when the average thickness of the liquid layer reaches 800 nm, the contact angle θ of the domain mainly containing the pentacene precursor with respect to the surface of the polycarbonate substrate (polyphenylamine film) is 7 It was 5 °.

Thereby, the solidified layer was heat-treated at 180 ° C. for 20 minutes to change the pentacene precursor to pentacene. Thereby, an organic semiconductor layer and a first gate insulating layer were obtained.
In addition, the average thickness of the obtained organic-semiconductor layer and the 1st gate insulating layer was 50 nm and 50 nm, respectively.

(Example 7)
<7-1> First, a glass substrate having an average thickness of 1 mm was prepared, and a gate electrode made of Au was formed on the glass substrate.
In addition, the average thickness of the obtained gate electrode was 100 nm.
<7-2> Next, a cyanoethyl group-containing cellulose derivative (manufactured by Shin-Etsu Chemical Co., Ltd., “CR-S”) is dissolved in N-methyl-2-pyrrolidone so as to be 5% wt / vol to obtain a liquid material. Prepared.
This liquid material was supplied onto a glass substrate by a spin coating method (2400 rpm) and then dried at 80 ° C. for 10 minutes. Thus, a second gate insulating layer was formed.
Note that the thickness of the obtained second gate insulating layer on the gate electrode was 450 nm.

<7-3> Next, 1% wt / vol of F8T2 (fluorene-bithiophene copolymer, weight average molecular weight 10,000) as the organic semiconductor layer forming material, and polystyrene (weight average) as the first gate insulating layer forming material A liquid material was prepared by dissolving in 1,2,4-trimethylbenzene (boiling point 168 ° C.) so that the molecular weight was 500,000) 1% wt / vol.
This liquid material was supplied onto the second gate insulating layer by an ink jet method (droplet diameter: 25 μm) to form a liquid layer (average thickness 2100 nm).
Thereafter, the liquid layer was naturally dried at 25 ° C. (the solvent was removed) and solidified. As a result, an organic semiconductor layer and a first gate insulating layer (solidified layer) were obtained.

In Example 7, since the second gate insulating layer is made of polyethylene having a low polarity, the first gate insulating layer is formed on the second gate insulating layer, and an organic material is formed on the second gate insulating layer. A semiconductor layer was formed.
The drying time (time required for solidifying the liquid layer) was 15 seconds, and the average thickness of the solidified layer was 100 nm.

In the drying process of the liquid layer, when the average thickness of the liquid layer reaches 800 nm, the contact angle θ of the domain mainly containing polystyrene with respect to the surface of the second gate insulating layer is 10.5 °. there were.
Moreover, the average thickness of the obtained organic-semiconductor layer and the 1st gate insulating layer was 50 nm and 50 nm, respectively. That is, the average thickness of the portion that substantially functions as the gate insulating layer was 500 nm.

<7-4> Next, after supplying an aqueous dispersion of Ag fine particles to both ends of the stacked body of the organic semiconductor layer and the first gate insulating layer by an inkjet method (droplet diameter is 25 μm), Dried at 80 ° C. for 10 minutes. Thereby, a source electrode and a drain electrode were formed.
Through the above process, the thin film transistor shown in FIG. 6 was manufactured.

(Comparative example)
First, a glass substrate having an average thickness of 1 mm was prepared, and a source electrode and a drain electrode made of Au were formed on the glass substrate.
The average thickness of the obtained source and drain electrodes was 100 nm, the distance between the source and drain electrodes (channel length L) was 10 μm, and the channel width W was 1 mm.

Next, an oxygen plasma treatment (atmospheric pressure oxygen plasma treatment) was performed on the glass substrate on which the source electrode and the drain electrode were formed under atmospheric pressure. Thereby, surface treatment was performed on the glass substrate.
The conditions of atmospheric pressure oxygen plasma were RF power 0.05 W / cm ² , oxygen gas flow rate 80 sccm, and processing time 150 seconds.

Next, F8T2 as a material for forming an organic semiconductor layer was dissolved in toluene so as to be 1% wt / vol to prepare a liquid material.
This liquid material was supplied onto a glass substrate that had been surface-treated by a spin coating method (2400 rpm), and then dried at 60 ° C. for 10 minutes. Thereby, an organic semiconductor layer was formed.
In addition, the average thickness of the obtained organic-semiconductor layer was 50 nm.

Next, a liquid material was prepared by dissolving polymethyl methacrylate (PMMA) in butyl acetate to 5% wt / vol.
This liquid material was supplied onto the organic semiconductor layer by a spin coating method (2400 rpm) and then dried at 60 ° C. for 10 minutes. Thereby, a gate insulating layer was formed.
In addition, the average thickness of the obtained gate insulating layer was 50 nm.

Next, an aqueous dispersion of PEDOT (polyethylenedioxythiophene) is supplied to the portion corresponding to the region between the source electrode and the drain electrode on the gate insulating layer by an ink jet method (droplet radius is 25 μm). And then dried at 80 ° C. for 10 minutes. Thereby, a gate electrode was formed.
In addition, the average thickness of the obtained gate electrode was 100 nm.
Through the above steps, a thin film transistor was manufactured.

2. Evaluation Threshold voltage, S value, and carrier mobility were measured for the thin film transistors manufactured in each of the examples and comparative examples.
Here, the threshold voltage is a gate voltage when the value of the approximate expression (relational expression) representing the relationship between the gate voltage and Id ^1/2 (Id: the value of the drain current) is 0, and the drain current Can be regarded as a gate voltage required to start flowing. The S value is a gate voltage value required for the drain current value to increase by one digit.
Therefore, the smaller the absolute value of the threshold voltage, the smaller the S value, and the larger the carrier mobility means that the thin film transistor has better characteristics.
These values are shown in Table 1.

As shown in Table 1, each of the thin film transistors manufactured in each example had a small threshold voltage absolute value and S value, a large carrier mobility value, and excellent characteristics.
On the other hand, the thin film transistor manufactured in the comparative example was inferior in characteristics.

It is a longitudinal cross-sectional view which shows the thin film transistor of a 1st structure. It is a figure for demonstrating the manufacturing method of the thin-film transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the thin-film transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the thin-film transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the thin-film transistor shown in FIG. It is a longitudinal cross-sectional view which shows the thin film transistor of a 2nd structure. It is a figure for demonstrating the manufacturing method of the thin-film transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the thin-film transistor shown in FIG. It is a longitudinal cross-sectional view which shows embodiment of an electrophoretic display apparatus (electronic device). FIG. 10 is a block diagram illustrating a configuration of an active matrix device included in the electrophoretic display device illustrated in FIG. 9. It is a perspective view which shows embodiment of electronic paper (electronic device). It is a figure which shows embodiment of a display (electronic device).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 11 ... Thin-film transistor 2 ... Substrate 3 ... Source electrode 4 ... Drain electrode 5 ... Organic-semiconductor layer 51 ... Channel region 61 ... First gate insulating layer 62 ... Second gate insulating layer 7 ... Gate electrode 8 ... Metal film 9 ... Liquid layer 90 ... Surface 91 ... First foamy phase 91 '... First domain 92 ... Second foamy phase 92' ... Second Domain 93 ... Matrix phase 99 ... Solidified layer 991 ... First solidified layer 992 ... Second solidified layer 20 ... Electrophoretic display device 30 ... Active matrix device 31 ... Data line 32 ... Scanning Line 40 ... Electrophoretic display 41 ... Pixel electrode 42 ... Microcapsule 420 ... Electrophoretic dispersion liquid 421, 422 ... Electrophoretic particles 43 ... Transparent electrode 44 ... Transparent substrate 45 ... Material 50 ... Substrate 600 ... Electronic paper 601 ... Main unit 602 ... Display unit 800 ... Display 801 ... Main unit 802a, 802b ... Conveying roller pair 803 ... Hole 804 ... Transparent glass plate 805 ... ... Insertion slot 806 ... Terminal part 807 ... Socket 808 ... Controller 809 ... Operation part

Claims (18)

Manufacturing a thin film transistor having a source electrode, a drain electrode, a gate electrode, an organic insulator layer that insulates the gate electrode from the source electrode and the drain electrode, and an organic semiconductor layer that contacts the organic insulator layer A way to
A first material for forming the organic semiconductor layer on the substrate on which the source electrode and the drain electrode or the gate electrode are formed, and the organic insulator layer that is not compatible with the first material. A first step of forming a liquid layer by supplying a liquid material containing a second material for forming and a solvent capable of dissolving both the first material and the second material;
By removing the solvent from the liquid layer, the first domain mainly including the first material and the second domain mainly including the second material are reduced in thickness of the liquid layer. A method of manufacturing a thin film transistor, comprising: a second step of obtaining the organic semiconductor layer and the organic insulator layer by causing phase separation in the direction and solidification.   Prior to the first step, a material for forming one of the organic semiconductor layer and the organic insulator layer on the substrate side on the surface side of the substrate on which the liquid layer is formed; The method for producing a thin film transistor according to claim 1, further comprising a step of performing an affinity improving treatment for making the affinity of the substrate higher than that of the material for forming the other layer.   The method for manufacturing a thin film transistor according to claim 2, wherein the affinity improving process is a plasma process.   4. The method of manufacturing a thin film transistor according to claim 3, wherein the affinity improving process is a chemical modification process for introducing a chemical structure including a part of a compound constituting the first material or the second material.   5. The method of manufacturing a thin film transistor according to claim 1, wherein at least one of the first material and the second material is a polymer material.   6. The method of manufacturing a thin film transistor according to claim 5, wherein the first material is a polymer material and has a weight average molecular weight of 4000 to 300,000.   The method for producing a thin film transistor according to claim 5 or 6, wherein the second material is a polymer material, and the weight average molecular weight is 10,000 to 2,000,000.   The method for manufacturing a thin film transistor according to claim 1, wherein the solvent is a high boiling point solvent.   The method for manufacturing a thin film transistor according to claim 1, wherein the solvent is a low boiling point solvent.   10. The method of manufacturing a thin film transistor according to claim 1, wherein a mixing ratio of the first material and the second material in the liquid material is 3: 1 to 1: 3 by weight.   11. The method of manufacturing a thin film transistor according to claim 1, wherein in the first step, the liquid material is supplied by a droplet discharge method.   12. The method of manufacturing a thin film transistor according to claim 1, wherein in the second step, the time required for solidifying the liquid layer is 5 seconds or more.   When the average thickness of the liquid layer after solidification is t, in the step 2, the first domain or the second domain in the range where the average thickness of the liquid layer is 1.2 t to 10 t. The method for producing a thin film transistor according to claim 1, wherein a contact angle with respect to a surface on which any one of the liquid layers is formed is 30 ° or less.   The method for manufacturing a thin film transistor according to claim 1, wherein in the second step, the solidified liquid layer is subjected to heat treatment.   A thin film transistor manufactured by the method for manufacturing a thin film transistor according to claim 1.   A thin film transistor circuit comprising the thin film transistor according to claim 15.   An electronic device comprising the thin film transistor circuit according to claim 16.   An electronic apparatus comprising the electronic device according to claim 17.

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