JP2008147465A - Manufacturing method of transistor, transistor, transistor circuit, electronic device, and electronic instrument - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor excellent in transistor characteristics and weather resistance and with reduced power consumption, to provide a manufacturing method of a transistor capable of easily manufacturing such a transistor, and to provide a transistor circuit, an electronic device and an electronic instrument including the transistor. <P>SOLUTION: A thin film transistor 1 has a source electrode 3 and a drain electrode 4, an organic semiconductor layer 5, a gate insulation layer 6 and a gate electrode 7. In addition, a protective film 8 is provided to approximately entirely cover the gate insulation layer 6. The gate insulation layer 6 among them is formed by plasma-polymerizing a source gas and depositing an obtained polymerized material. A fluorine-based gas is preferably used as the source gas. Such a gate insulation layer 6 is precise and has large density. It can also keep sufficient insulation characteristics when thinned. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a transistor, a transistor, a transistor circuit, an electronic device, and an electronic apparatus.

In recent years, development of a thin film transistor using an organic material (organic semiconductor material) that exhibits semiconducting electrical conduction has been promoted. This thin film transistor has advantages such as being suitable for reduction in thickness and weight, flexibility, and low material cost, and is expected as a switching element for flexible displays and the like.
Such a thin film transistor includes a top gate structure in which a source electrode and a drain electrode and an organic semiconductor layer are formed on a substrate, and a gate insulating layer and a gate electrode are stacked in this order on each portion. A bottom gate structure is proposed in which a gate electrode and a gate insulating layer are laminated in this order, and a source electrode and a drain electrode and an organic semiconductor layer are formed on each of these portions.

By the way, a method of manufacturing a thin film transistor in which the gate insulating layer of such a thin film transistor is formed by a chemical vapor deposition method is disclosed (for example, see Patent Document 1).
In the method described in Patent Document 1, after a film is formed by a vapor phase growth method, the gate insulating layer is obtained by irradiating the film with laser or ultraviolet rays to remove hydrocarbons in the film. However, when the film is irradiated with laser or ultraviolet rays, there is a possibility that the organic semiconductor layer adjacent to the gate insulating layer or the gate electrode may be altered or deteriorated.

In addition, since a film formed by a vacuum evaporation method has a low density, ions in the gate insulating layer easily diffuse into the adjacent organic semiconductor layer. As a result, the off current of the thin film transistor may increase. In particular, during the operation of the thin film transistor, since a voltage is applied to the gate insulating layer, the tendency for ions to diffuse becomes more prominent.
Further, when the density of the gate insulating layer is low, moisture is easily adsorbed and absorbed. For this reason, the insulating characteristics of the gate insulating layer may be degraded, and the gate leakage current may increase.

On the other hand, a solution in which the raw material of the gate insulating layer is dissolved is applied by a method such as a spin coating method or an ink jet method to form a liquid film, and the solvent is removed from the liquid film to obtain the gate insulating layer. Methods are also known. However, since the density of the gate insulating layer formed by this method is low, it is inevitable that ions in the gate insulating layer diffuse into the organic semiconductor layer.
Further, since the thickness of the liquid film is likely to be non-uniform due to the influence of the uneven shape of the base, it is difficult to obtain a gate insulating layer having a uniform thickness.
Furthermore, when a polar solvent is used as the solvent in the solution, the solvent is easily hydrated during the production process. For this reason, there exists a possibility that the insulation characteristic of a gate insulating layer may fall with this water | moisture content.

JP-A-6-124890

  An object of the present invention is to provide a transistor having excellent transistor characteristics and weather resistance and low power consumption, a transistor manufacturing method capable of easily manufacturing such a transistor, a transistor circuit including the transistor, an electronic device, and an electronic apparatus. is there.

The above object is achieved by the following.
A method for manufacturing a transistor of the present invention includes a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer, and a gate insulation that insulates the source electrode and the drain electrode from the gate electrode. A thin film transistor manufacturing method for manufacturing a thin film transistor comprising a layer,
Forming the source electrode and the drain electrode on the substrate;
Forming the organic semiconductor layer at least between the source electrode and the drain electrode;
Forming the gate insulating layer so as to cover the source electrode, the drain electrode, and the organic semiconductor layer;
Forming the gate electrode on the gate insulating layer,
In the step of forming the gate insulating layer, at least a part of the gate insulating layer in the thickness direction is formed by plasma polymerizing a source gas and depositing the obtained polymer.
Accordingly, a thin film transistor having excellent transistor characteristics and weather resistance and low power consumption can be easily manufactured.

A method for manufacturing a transistor of the present invention includes a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer, and a gate insulation that insulates the source electrode and the drain electrode from the gate electrode. A thin film transistor manufacturing method for manufacturing a thin film transistor comprising a layer,
Forming the gate electrode on the substrate;
Forming the gate insulating layer on the gate electrode;
Forming the organic semiconductor layer on the gate insulating layer;
Forming the source electrode and the drain electrode on the organic semiconductor layer,
In the step of forming the gate insulating layer, at least a part of the gate insulating layer in the thickness direction is formed by plasma polymerizing a source gas and depositing the obtained polymer.
Accordingly, a thin film transistor having excellent transistor characteristics and weather resistance and low power consumption can be easily manufactured.

In the method for manufacturing a transistor of the present invention, the source gas is preferably one containing a fluorine-based gas as a main component.
A source gas containing a fluorine-based gas can form a dense polymer containing fluorine atoms by plasma polymerization. This polymer exhibits water repellency due to fluorine atoms and moisture resistance associated with such water repellency. Therefore, by using such a source gas, a gate insulating film capable of suppressing or preventing moisture adsorption / absorption can be easily formed.

In the method for manufacturing a transistor of the present invention, the fluorine-based gas is preferably CHF ₃ .
CHF ₃ can form a denser and higher density polymer by plasma polymerization. Moreover, since the content rate of the fluorine atom in a gas molecule is high, a polymer with higher water repellency can be obtained.

In the transistor manufacturing method of the present invention, it is preferable that the source gas contains a vaporized liquid substance containing fluorine.
Thereby, handling of a raw material becomes easy.
In the method for manufacturing a transistor of the present invention, the liquid material containing fluorine is preferably C ₈ F ₁₈ .
According to C ₈ F _18, because the content of fluorine atom is high, it is possible to form a more excellent water repellency and moisture resistance polymer.

In the method for producing a transistor of the present invention, the organic semiconductor layer is composed of a p-type organic semiconductor material,
In the step of forming the gate insulating layer, at least a portion of the gate insulating layer on the organic semiconductor layer side is formed by plasma polymerizing a source gas containing fluorine and depositing the obtained polymer. Is preferred.
Since fluorine has a very high electronegativity, it is easy to attract electrons. For this reason, when the plasma polymerized film containing fluorine is in contact with the organic semiconductor layer, in addition to the effect of being excellent in water repellency and moisture resistance, the effect of improving the electron mobility in the channel region is also obtained. As a result, transistor characteristics of the thin film transistor can be improved (an increase in operating speed and an increase in on-state current). Such an effect is obtained because the plasma polymerized film is dense and can contain fluorine atoms at a high density.

In the transistor manufacturing method of the present invention, it is preferable to adjust the density of the gate insulating layer by setting a plasma output in the plasma polymerization.
Thereby, the density of the plasma polymerized film, that is, the density of the gate insulating layer can be easily adjusted.
In the transistor manufacturing method of the present invention, it is preferable to adjust the film formation rate of the gate insulating layer by setting at least one of the flow rate and pressure of the source gas in the plasma polymerization.
Thereby, the probability of causing plasma polymerization can be controlled, and as a result, the film formation rate can be easily adjusted. For this reason, the film formation rate can be adjusted to efficiently form a polymer, and the formation efficiency of the plasma polymerization film can be increased.

The transistor of the present invention is manufactured by the method for manufacturing a thin film transistor of the present invention.
Thereby, a highly reliable thin film transistor can be obtained.
The transistor of the present invention includes a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer, and a gate insulating layer that insulates the source electrode, the drain electrode, and the organic semiconductor layer from the gate electrode. A thin film transistor comprising:
At least a part of the gate insulating layer in the thickness direction is formed of a dense plasma polymerized film.
Thus, a thin film transistor having excellent transistor characteristics and weather resistance and low power consumption can be obtained.

In the transistor of the present invention, the organic semiconductor layer is made of a p-type organic semiconductor material,
It is preferable that at least a portion of the gate insulating layer adjacent to the organic semiconductor layer is composed of a plasma polymerization film containing fluorine.
Accordingly, a thin film transistor having excellent water repellency and moisture resistance and particularly high transistor characteristics (the operation speed is particularly fast or the on-current is particularly large) can be obtained.

The transistor of the present invention includes a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer, and a gate insulating layer that insulates the source electrode, the drain electrode, and the organic semiconductor layer from the gate electrode. A thin film transistor comprising:
The density of the gate insulating layer is 1.5 to 2.5 g / cm ³ .
Thus, a thin film transistor having excellent transistor characteristics and weather resistance and low power consumption can be obtained.
In the transistor of the present invention, the gate insulating layer preferably has an average thickness of 10 to 5000 nm.
As a result, the gate leakage current can be made sufficiently small and the gate voltage can be prevented from increasing due to the thickness of the gate insulating layer becoming too thick.

The transistor circuit of the present invention includes the transistor of the present invention.
Thereby, a thin film transistor circuit having high operating characteristics and high reliability can be obtained.
The electronic device of the present invention includes the transistor circuit of the present invention.
Thereby, an electronic device with high operational characteristics and reliability can be obtained.
An electronic apparatus according to the present invention includes the electronic device according to the present invention.
Thereby, an electronic device with high operating characteristics and reliability can be obtained.

Hereinafter, a thin film transistor manufacturing method, a thin film transistor, a thin film transistor circuit, an electronic device, and an electronic apparatus according to the present invention will be described in detail based on preferred embodiments.
<First Embodiment of Active Matrix Device>
First, a first embodiment of an active matrix device (thin film transistor circuit of the present invention) including the thin film transistor of the present invention will be described.

FIG. 1 is a plan view showing a first embodiment of an active matrix device, and FIG. 2 is a sectional view taken along line XX in FIG. In the following description, the upper side in FIG. 2 is referred to as “upper” and the lower side is referred to as “lower”.
The active matrix device 30 shown in FIG. 1 has a plurality of data lines 31 orthogonal to each other, a plurality of scanning lines 32, and the thin film transistor 1 provided in the vicinity of each intersection of the data lines 31 and the scanning lines 32. is doing.

As shown in FIG. 2, each thin film transistor 1 includes a source electrode 3 and a drain electrode 4, an organic semiconductor layer 5, a gate insulating layer 6, and a gate electrode 7.
In the present embodiment, the thin film transistors 1 arranged in a line in the horizontal direction (left and right direction) in FIG. 1 have their gate electrodes 7 formed integrally to form a scanning line 32. One end of the scanning line 32 is connected to a connection electrode 33 provided on the substrate 50. The connection electrode 33 is a connection terminal for connecting to an external electrode.

Further, the source electrode 3 provided in each thin film transistor 1 is connected to the data line 31, and the drain electrode 4 is connected to a pixel electrode (individual electrode) 41 provided in the electrophoretic display unit 40 described later.
Each pixel electrode 41 is arranged in a matrix corresponding to each thin film transistor 1.

Hereinafter, the configuration of the thin film transistor 1 will be described in detail.
In the thin film transistor 1, a source electrode 3 and a drain electrode 4 are provided separately on a substrate 50, and an organic semiconductor layer 5 is provided in contact with the source electrode 3 and the drain electrode 4. A gate insulating layer 6 is provided in contact with the organic semiconductor layer 5. Further, a gate electrode 7 is provided on the gate insulating layer 6 so as to overlap at least a region between the source electrode 3 and the drain electrode 4, and a protective film is provided so as to cover almost the entire surface of the gate insulating layer 6. 8 is provided.

In the thin film transistor 1, a region between the source electrode 3 and the drain electrode 4 in the organic semiconductor layer 5 is a channel region 51 in which carriers move, and most carriers induced in the channel region 51. Moves along the interface between the organic semiconductor layer 5 and the gate insulating layer 6.
Hereinafter, in this channel region 51, the length in the carrier moving direction, that is, the distance between the source electrode 3 and the drain electrode 4 is the channel length L, and the length in the direction orthogonal to the channel length L direction is the channel width W. To tell.

Such a thin film transistor 1 is a thin film transistor having a structure in which the source electrode 3 and the drain electrode 4 are provided on the substrate 50 side with respect to the gate electrode 7 with the gate insulating layer 6 interposed therebetween, that is, a thin film transistor having a top gate structure.
The substrate 50 supports each layer (each part) constituting the thin film transistor 1. The substrate 50 is, for example, a plastic substrate (resin substrate) composed of a glass substrate, polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), aromatic polyester (liquid crystal polymer), or the like. A quartz substrate, a silicon substrate, a gallium arsenide substrate, or the like can be used. When the thin film transistor 1 is given flexibility, a resin substrate is selected as the substrate 50.

An underlayer may be provided on the substrate 50. The underlayer is provided, for example, for the purpose of preventing diffusion of ions from the surface of the substrate 50, or for improving the adhesion (bondability) between the source electrode 3 and drain electrode 4 and the substrate 50.
This underlayer can be made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), polyimide, polyamide, a polymer insolubilized by crosslinking, or the like.

On the substrate 50, the source electrode 3 and the drain electrode 4 are juxtaposed at a predetermined distance along the channel length L direction.
Examples of the constituent material of the source electrode 3 and the drain electrode 4 include metal materials such as Pd, Pt, Au, W, Ta, Mo, Al, Cr, Ti, Cu or alloys containing them, and the like. It is preferable to select appropriately according to the carrier moving the region.
For example, in the case of a p-channel thin film transistor in which holes move in the channel region, it is preferable to use Pd, Pt, Au, Ni, Cu, or an alloy containing these metals having a relatively large work function.

In addition to the above metal materials, the constituent materials of the source electrode 3 and the drain electrode 4 include conductive oxides such as ITO, FTO, ATO, SnO ₂ , carbon materials such as carbon black, carbon nanotubes, fullerenes, and polyacetylene. , Polypyrrole, polythiophene such as PEDOT (poly-ethylenedioxythiophene), polyaniline, poly (p-phenylene), poly (p-phenylenevinylene), polyfluorene, polycarbazole, polysilane, or derivatives thereof, etc. These can be used, and one or more of these can be used in combination.
The conductive polymer material is usually used in a state where it is doped with a polymer such as iron chloride, iodine, an inorganic acid, an organic acid, or polystyrene sulfonic acid, and imparted with conductivity.

The average thickness of the source electrode 3 and the drain electrode 4 is not particularly limited, but is preferably about 30 to 300 nm, and more preferably about 50 to 150 nm.
The distance (separation distance) between the source electrode 3 and the drain electrode 4, that is, the channel length L is preferably about 2 to 30 μm, and more preferably about 5 to 20 μm. When the channel length L is made smaller than the lower limit value, an error occurs in the channel length between the obtained thin film transistors 1, and the characteristics (transistor characteristics) may vary. On the other hand, when the channel length L is made larger than the upper limit value, the absolute value of the threshold voltage is increased, the drain current value is decreased, and the characteristics of the thin film transistor 1 may be insufficient.

Further, the channel width W is preferably about 0.1 to 5 mm, and more preferably about 0.5 to 3 mm. If the channel width W is made smaller than the lower limit value, the drain current value becomes small and the characteristics of the thin film transistor 1 may be insufficient. On the other hand, when the channel width W is larger than the upper limit value, the thin film transistor 1 is increased in size, and parasitic capacitance is increased, and leakage current (gate leakage current) to the gate electrode 7 through the gate insulating layer 6 is increased. There is a risk of inviting.
An organic semiconductor layer 5 is provided on the substrate 50 so as to cover between the source electrode 3 and the drain electrode 4 and a part of the source electrode 3 and the drain electrode 4.

The organic semiconductor layer 5 is composed mainly of an organic semiconductor material (an organic material that exhibits semiconducting electrical conduction).
The organic semiconductor layer 5 is preferably oriented so as to be substantially parallel to the channel length L direction at least in the channel region 51. As a result, the carrier mobility in the channel region 51 is high, and as a result, the thin film transistor 1 has a higher operating speed.

  Examples of the organic semiconductor material include naphthalene, anthracene, tetracene, pentacene, hexacene, phthalocyanine, perylene, hydrazone, triphenylmethane, diphenylmethane, stilbene, arylvinyl, pyrazoline, triphenylamine, triarylamine, oligothiophene, phthalocyanine or Low molecular organic semiconductor materials such as these derivatives, poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, polythiophene, polyalkylthiophene, polyhexylthiophene, poly (p-phenylene vinylene), polytinylene vinylene, Polyarylamine, pyrene formaldehyde resin, ethylcarbazole formaldehyde resin, fluorene-bithiophene copolymer, fluorene-ary Examples thereof include high molecular organic semiconductor materials (conjugated polymer materials) such as amine copolymers or derivatives thereof, and one or more of these can be used in combination. It is preferable to use a material mainly composed of a molecular organic semiconductor material (conjugated polymer material). The conjugated polymer material has a particularly high carrier mobility due to its unique electron cloud spread.

A polymer organic semiconductor material can be formed by a simple method and can be oriented relatively easily. Of these, fluorene-bithiophene copolymer, fluorene-arylamine copolymer are used as high-molecular organic semiconductor materials (conjugated polymer materials) because they are not easily oxidized in the air and are stable. It is particularly preferable to use a compound, a polyarylamine or a derivative containing at least one of these derivatives as a main component.
In addition, the organic semiconductor layer 5 composed mainly of a polymer organic semiconductor material can be reduced in thickness and weight, and has excellent flexibility. Therefore, the thin film transistor can be used as a switching element of a flexible display. Suitable for applications.

The average thickness of the organic semiconductor layer 5 is preferably about 1 to 200 nm, and more preferably about 10 to 100 nm.
Note that the organic semiconductor layer 5 is not limited to a structure provided so as to cover the source electrode 3 and the drain electrode 4, and is provided at least in a region (channel region 51) between the source electrode 3 and the drain electrode 4. It only has to be.

A gate insulating layer 6 is provided on the organic semiconductor layer 5. In the present embodiment, the gate insulating layer 6 is provided so as to cover the source electrode 3, the drain electrode 4, and the organic semiconductor layer 5.
This gate insulating layer 6 insulates the gate electrode 7 from the source electrode 3 and the drain electrode 4.

The gate insulating layer 6 is composed of a plasma polymerization film. As will be described in detail later, this plasma polymerized film is formed by plasma polymerizing a raw material gas and depositing the obtained polymer.
According to such a plasma polymerized film, a dense and dense gate insulating layer 6 can be obtained.

By the way, generally, a trace amount of ions exists in a layer (film) formed by any method. Conventionally, ions in the gate insulating layer have diffused into the organic semiconductor layer, thereby affecting the carrier mobility in the channel region. For this reason, the off current of the thin film transistor 1 increases due to the ions.
On the other hand, in the present invention, since the gate insulating layer 6 is composed of a dense and high-density plasma polymerized film, the ions are difficult to diffuse into the organic semiconductor layer 5 adjacent to the gate insulating layer 6. For this reason, it is possible to prevent the off current of the thin film transistor 1 from increasing. As a result, the power consumption of the thin film transistor 1 can be reduced.

  Moreover, since the gate insulating layer 6 made of a plasma polymerized film is dense, the insulating characteristics are high. For this reason, an increase in gate leakage current can be prevented even if the thickness is reduced. Therefore, the threshold voltage (Vth) can be reduced by reducing the thickness of the gate insulating layer 6. As a result, the gate voltage can be set low, and further power saving of the thin film transistor 1 can be achieved.

Moreover, when the density of the gate insulating layer 6 is high, it becomes difficult to adsorb and absorb moisture. For this reason, it can prevent that the insulation characteristic of the gate insulating layer 6 falls by this water | moisture content. In other words, even when the thin film transistor 1 is operated in an environment in which the amount of moisture changes, the thin film transistor 1 that can operate stably while maintaining certain transistor characteristics can be obtained.
Note that the off-state current refers to a current that flows between the source electrode and the drain electrode when the gate voltage is zero.

Such density of the gate insulating layer 6 is preferably from 1.5~2.5g / cm ³ or so, and more preferably 1.8~2.2g / cm ³ order. When the density of the gate insulating layer 6 is large as in the above range, ions in the gate insulating layer 6 are particularly difficult to diffuse into the organic semiconductor layer 5. For this reason, it can prevent especially reliably that the OFF current of the thin-film transistor 1 increases.

Furthermore, the gate insulating layer 6 having a high density as described above exhibits the effect of suppressing or preventing moisture adsorption / absorption more reliably. For this reason, it can prevent more reliably that the insulation characteristic of the gate insulating layer 6 falls by this water | moisture content.
In addition, although the density of the gate insulating layer 6 may exceed the said upper limit, a more excellent effect cannot be expected.

  The gate insulating layer 6 can be composed of, for example, a fluorine-based, hydrocarbon-based, organic silicon-based plasma polymerized film, etc., but is particularly preferably composed mainly of a fluorine-based plasma polymerized film. Thereby, the gate insulating layer 6 exhibits water repellency due to fluorine atoms and moisture resistance associated with the water repellency. For this reason, in the gate insulating layer 6, the effect of suppressing or preventing moisture adsorption / absorption becomes more remarkable. And the thin-film transistor 1 excellent in especially weather resistance can be obtained.

The average thickness of the gate insulating layer 6 is preferably about 10 to 5000 nm, and more preferably about 100 to 1000 nm. If the thickness of the gate insulating layer 6 is within the above range, the gate leakage current can be made sufficiently small, and the gate insulating layer 6 can be prevented from becoming too thick to increase the gate voltage. .
Note that when the average thickness of the gate insulating layer 6 is less than the lower limit, the gate leakage current increases, and the power consumption of the thin film transistor 1 may be significantly increased.

On the other hand, when the average thickness of the gate insulating layer 6 exceeds the upper limit, it is necessary to remarkably increase the gate voltage. For this reason, the power consumption of the thin film transistor 1 may be significantly increased.
Note that the gate insulating layer 6 may have a single layer structure, but may also have a stacked body in which a plurality of layers are stacked.

A gate electrode 7 is provided on the gate insulating layer 6.
As the constituent material of the gate electrode 7, the same materials as those mentioned for the source electrode 3 and the drain electrode 4 can be used.
The average thickness of the gate electrode 7 is not particularly limited, but is preferably about 0.1 to 5000 nm, more preferably about 1 to 5000 nm, and still more preferably about 10 to 5000 nm.

A protective film 8 is provided on the gate insulating layer 6 so as to cover almost the entire surface thereof.
The protective film 8 mechanically protects each thin film transistor 1 and, for example, when the active matrix device 30 is applied to an electrophoretic display device 20 as described later, an electrophoretic dispersion liquid enclosed in a microcapsule 42. Even when 420 (lipophilic liquid) flows out to the outside for some reason, it has a function of preventing diffusion to the thin film transistor 1 side.

Examples of the constituent material of the protective film 8 include organic materials such as polyvinyl alcohol, ethylene-vinyl alcohol copolymer, vinyl chloride-vinyl alcohol copolymer and vinyl acetate-vinyl alcohol copolymer, SiO 2 An inorganic material such as ₂ can be used.
The average thickness of the protective film 8 is not particularly limited, but is preferably about 100 to 5000 nm, and more preferably 300 to 3000 nm. Thereby, the protective film 8 can fully exhibit its function.
The protective film 8 may be provided as necessary and may be omitted.

In such a thin film transistor 1, the amount of current flowing between the source electrode 3 and the drain electrode 4 is controlled by changing the voltage applied to the gate electrode 7.
That is, in the OFF state in which no voltage is applied to the gate electrode 7, even if a voltage is applied between the source electrode 3 and the drain electrode 4, almost no carriers are present in the organic semiconductor layer 5, so that a very small current Only flows. On the other hand, in the ON state in which a voltage is applied to the gate electrode 7, movable charges (carriers) are induced in the portion of the organic semiconductor layer 5 facing the gate insulating layer 6, and a flow path is formed in the channel region 51. When a voltage is applied between the source electrode 3 and the drain electrode 4 in this state, a current flows through the channel region 51.

<Method for Manufacturing Active Matrix Device According to First Embodiment>
Next, a method for manufacturing the active matrix device shown in FIG. 1 (a method for manufacturing a thin film transistor of the present invention) will be described.
3 and 4 are diagrams (longitudinal sectional views) for explaining a method of manufacturing the active matrix device shown in FIGS. 1 and 2, respectively, and FIG. 5 is a schematic diagram showing the configuration of the plasma polymerization apparatus. In the following description, the upper side in FIGS. 3 and 4 is referred to as “upper” and the lower side is referred to as “lower”.
The manufacturing method of the active matrix device 30 includes: [1] electrode (excluding gate electrode) and wiring forming step, [2] organic semiconductor layer forming step, [3] gate insulating layer forming step, and [4] gate electrode. Forming step and [5] protective film forming step. Hereinafter, each of these steps will be described sequentially.

[1] Electrode and Wiring Formation Step A substrate 50 is prepared as shown in FIG. 3A, and the source electrode 3, the drain electrode 4, the pixel electrode 41, the data line 31, and the connection electrode 33 are provided on the substrate 50. Form.
As shown in FIG. 3B, first, a metal film (metal layer) 9 is formed on the substrate 50.
This includes, for example, chemical vapor deposition (CVD) such as plasma CVD, thermal CVD, and laser CVD, vacuum deposition, sputtering (low temperature sputtering), dry plating methods such as ion plating, electrolytic plating, immersion plating, and electroless plating. It can be formed by a wet plating method such as a thermal spraying method, a sol-gel method, a MOD method, or a metal foil bonding.

A resist layer having a shape corresponding to the shapes of the source electrode 3, the drain electrode 4, the pixel electrode 41, the data line 31, and the connection electrode 33 is formed on the metal film 9 by photolithography. Using this resist layer as a mask, unnecessary portions of the metal film 9 are removed.
For the removal of the metal film 9, for example, one or more of physical etching methods such as plasma etching, reactive ion etching, beam etching, and light-assisted etching, and chemical etching methods such as wet etching are used. Can be used in combination.
Then, by removing the resist layer, the source electrode 3, the drain electrode 4, the pixel electrode 41, the data line 31, and the connection electrode 33 are obtained as shown in FIG.

  The source electrode 3, the drain electrode 4, the pixel electrode 41, the data line 31, and the connection electrode 33 are, for example, a colloid liquid (dispersion liquid) containing conductive particles and a liquid containing a conductive polymer, respectively. After a liquid material such as (solution or dispersion) is supplied onto the substrate 50 to form a film, the film is post-treated as necessary (for example, heating, infrared irradiation, application of ultrasonic waves, etc.) It can also be formed by applying.

  Examples of a method for supplying the liquid material onto the substrate 50 include a dipping method, a spin coating method, a casting method, a micro gravure coating method, a gravure coating method, a bar coating method, a roll coating method, a wire bar coating method, and a dip coating. Methods, spray coating methods, screen printing methods, flexographic printing methods, offset printing methods, ink jet methods, microcontact printing methods, and the like, and one or more of these can be used in combination.

Among these, it is particularly preferable to use an ink jet method (droplet discharge method). According to the ink jet method (droplet discharge method), the source electrode 3, the drain electrode 4, the pixel electrode 41, the data line 31, and the connection electrode 33 can be formed easily and with high dimensional accuracy.
The surface of the substrate 50 is preferably preliminarily subjected to oxygen plasma treatment. Thereby, the adhesiveness of each electrode 3 and 4 and the board | substrate 50 improves.

[2] Organic Semiconductor Layer Forming Step Next, as shown in FIG. 3D, on the substrate 50 on which the source electrode 3 and the drain electrode 4 are formed, between the source electrode 3 and the drain electrode 4 and each electrode The organic semiconductor layer 5 is formed so as to cover a part of 3 and 4.
At this time, a channel region 51 is formed between the source electrode 3 and the drain electrode 4 (region corresponding to the gate electrode 7).

For example, when the organic semiconductor layer 5 is composed of an organic polymer material, the organic semiconductor layer 5 covers the source electrode 3 and the drain electrode 4 on the substrate 50 with a liquid material containing the organic polymer material or a precursor thereof. Thus, the film can be formed by subjecting the film to post-treatment (eg, heating, irradiation with infrared rays, application of ultrasonic waves, etc.) as necessary.
As a method for supplying the liquid material onto the substrate 50, the same method as mentioned in the step [1] can be used.

The formation region of the organic semiconductor layer 5 is not limited to the illustrated configuration, and the organic semiconductor layer 5 may be formed only in a region (channel region 51) between the source electrode 3 and the drain electrode 4. Accordingly, when a plurality of thin film transistors 1 (elements) are arranged side by side on the same substrate, leakage current and crosstalk between the elements are suppressed by independently forming the organic semiconductor layer 5 of each element. Can do. Moreover, the usage-amount of organic-semiconductor material can be reduced and manufacturing cost can also be reduced.
Further, when the organic semiconductor layer 5 is formed only in the channel region 51, the ink jet method (droplet discharge method) is particularly suitable in that it can be performed without contact. Moreover, the resolution required for manufacturing the thin film transistor 1 is also 5 to 100 μm, which is suitable for the resolution of the ink jet method.

[3] Gate Insulating Layer Formation Step Next, as shown in FIG. 4 (e), the gate insulating layer 6 is formed on the organic semiconductor layer 5.
The gate insulating layer 6 can be formed, for example, by a plasma polymerization method using the plasma polymerization apparatus 100 shown in FIG.
A plasma polymerization apparatus 100 shown in FIG. 5 includes a vacuum chamber 120 to which a vacuum pump 110 is connected, and an electrode 130 and a stage 140 are provided in the vacuum chamber 120.

The electrode 130 is attached to the upper portion of the vacuum chamber 120 via an insulator 121 and is connected to a high frequency power supply 150 disposed outside the vacuum chamber 120. The high frequency power supply 150 outputs high frequency power.
The output (plasma output) of the high frequency power is preferably about 5 to 500 W, and more preferably about 10 to 100 W.
Moreover, the frequency of high frequency electric power is not specifically limited, For example, it can be set to 13.56 MHz which is a general industrial frequency.

The stage 140 on which the substrate 50 on which the electrodes 3 and 4 and the organic semiconductor layer 5 are formed is placed, and is disposed below the vacuum chamber 120 so as to face the electrode 130. The stage 140 is provided with a temperature adjustment mechanism that adjusts the temperature of the substrate 50.
In addition, a gas supply pipe 160 and a raw material supply pipe 170 are connected to the vacuum chamber 120.

A gas supply source 180 is connected to the gas supply pipe 160 via a flow rate control valve 161. By opening / closing the flow control valve 161, the flow rate of the gas supplied to the vacuum chamber 120 is adjusted.
Examples of the additive gas supplied from the gas supply source 180 include argon, helium, nitrogen, and the like. Among these, argon is preferably used.

A raw material container 190 that stores a raw material gas is connected to the raw material supply pipe 170 via a flow rate control valve 171. A heater 191 is installed in the lower part of the raw material container 190. When the raw material in the raw material container 190 is a liquid material, the liquid material can be heated and vaporized by the heater 191 to be gaseous.
The source gas is sucked by the negative pressure in the vacuum chamber 120 and supplied to the vacuum chamber 120 through the source supply pipe 170. The flow rate of the source gas supplied to the vacuum chamber 120 is controlled by opening / closing the flow rate control valve 171.

Next, a method for forming the gate insulating layer 6 using the plasma polymerization apparatus 100 shown in FIG. 5 will be described.
[3-1] First, the substrate 50 on which the electrodes 3 and 4 and the organic semiconductor layer 5 are formed is placed on the stage 140 in the vacuum chamber 120.

[3-2] Next, the pressure in the vacuum chamber 120 is reduced to a set value by operating the pump 110.
The pressure in the vacuum chamber 120 due to this reduced pressure is preferably 1 Torr (1.3 × 10 ⁻⁴ MPa) or less, and preferably 1 × 10 ⁻⁴ Torr (1.3 × 10 ⁻⁸ MPa) or less. More preferred.
Next, by adjusting the temperature adjustment mechanism of the stage 140, the temperature of the substrate 50 is set so that the plasma polymerization reaction of the source gas is promoted.
At this time, the temperature of the substrate 50 is preferably 25 ° C. or higher, more preferably about 25 to 100 ° C.

Next, the additive gas is supplied from the gas supply pipe 160 and the raw material gas is supplied from the raw material supply pipe 170 into the vacuum chamber 120.
The flow rate of the additive gas is preferably about 10 to 500 sccm.
On the other hand, the flow rate of the source gas is preferably about 1 to 100 sccm, and more preferably about 30 to 70 sccm.
The pressure in the vacuum chamber 120 after the supply of the source gas is preferably about 0.01 to 1 Torr (1.3 × 10 ^{−6 to} 1.3 × 10 ⁻⁴ MPa), More preferably, it is about 0.5 Torr (1.3 × 10 ^{−5 to} 6.7 × 10 ⁻⁵ MPa).

  [3-3] Next, high frequency power is applied to the electrode 130 by the high frequency power source 150. Thereby, argon plasma is generated in the vacuum chamber 120. The source gas is activated by the electron impact excitation of the argon plasma to cause a polymerization reaction, and a polymer is deposited on the organic semiconductor layer 5. As a result, a gate insulating layer 6 made of a plasma polymerization film is formed on the organic semiconductor layer 5.

Examples of the source gas supplied into the vacuum chamber 120 include CHF ₃ (trifluoromethane), C ₂ F ₄ (tetrafluoroethylene), C ₂ F ₆ (hexafluoroethane), and C ₄ F ₈ (octafluorocyclobutane). ), A hydrocarbon gas such as C ₂ H ₄ (ethylene), C ₃ H ₆ (propylene), C ₈ H ₈ (styrene), C ₆ H ₁₈ OSi ₂ (hexamethyldisiloxane) ), An organic silicon-based gas such as C ₈ H ₂₄ O ₂ Si ₃ (octamethyltrisiloxane), or a mixed gas thereof.

  Among these, as the source gas, a gas mainly containing a fluorine-based gas is preferable. A source gas containing a fluorine-based gas can form a dense polymer containing fluorine atoms by plasma polymerization. This polymer exhibits water repellency due to fluorine atoms and moisture resistance associated with such water repellency. Therefore, by using such a source gas, the gate insulating layer 6 that can suppress or prevent moisture adsorption / absorption can be easily formed.

Of the fluorine-based gases, it is particularly preferable to use CHF ₃ . This fluorine-based gas can form a denser and denser polymer by plasma polymerization. Furthermore, since the content of fluorine atoms in the gas molecules is high, a polymer with higher water repellency can be obtained.
In addition, the source gas used in the present invention may be mainly composed of a vaporized liquid material (vaporized material) containing fluorine. Thereby, handling of a raw material becomes easy.

Examples of such a liquid substance containing fluorine include C ₈ F ₁₈ (octadecafluorooctane), C ₆ F ₆ (hexafluorobenzene), C ₆ H ₃ F ₃ (trifluorobenzene), and C ₆ H. Examples thereof include ₂ F ₄ (tetrafluorobenzene) or a mixture thereof, and C ₈ F ₁₈ is particularly preferable. According to this liquid substance, since the fluorine atom content is high, a polymer having more excellent water repellency and moisture resistance can be formed.

The time for applying the high-frequency power (polymer formation time) is preferably about 10 to 60 minutes, and more preferably about 20 to 30 minutes.
In particular, when the organic semiconductor layer 5 is made of a p-type organic semiconductor material, at least a portion of the gate insulating layer 6 adjacent to the organic semiconductor layer 5 (an adjacent portion of the semiconductor layer) is a fluorine-based plasma. It is preferable that it is composed of a polymerized film. Since fluorine has a very high electronegativity, it is easy to attract electrons. In the organic semiconductor in contact with fluorine, electrons are extracted by fluorine and hole carriers are generated. For this reason, since the plasma polymerization film containing fluorine is in contact with the organic semiconductor layer 5, in addition to the above-described effects, an effect that more hole carriers are generated in the channel region 51 is also obtained. As a result, the transistor characteristics of the thin film transistor 1 can be improved (an increase in operating speed and an increase in on-current). Such an effect is obtained because the plasma polymerized film is dense and can contain fluorine atoms at a high density.

In this case, the entire gate insulating layer 6 may be composed of a fluorine-based plasma polymerized film, but the portion other than the semiconductor layer adjacent portion may be composed of a layer not containing fluorine. The fluorine-free layer is preferably formed by plasma polymerization, but may be formed by other forming methods such as a vapor phase film forming method and a liquid phase film forming method.
Here, the portion of the gate insulating layer 6 adjacent to the semiconductor layer is composed of a fluorine-based plasma polymerized film, and the portion of the gate insulating layer 6 other than the portion adjacent to the semiconductor layer is composed of a hydrocarbon-based plasma polymerized film. If so, the type of the source gas may be switched during the plasma polymerization.
That is, first, plasma polymerization is performed as described above using a fluorine-based gas. Then, after the plasma polymerization film having a predetermined thickness is formed, the type of the raw material gas is switched to the hydrocarbon gas, and the plasma polymerization is similarly performed. In this way, a laminated body in which two layers having different compositions are laminated can be easily obtained in spite of a single film formation process.

  On the other hand, when the organic semiconductor layer 5 is made of an n-type organic semiconductor material, at least a portion (semiconductor layer adjacent portion) adjacent to the organic semiconductor layer 5 in the gate insulating layer 6 is a layer not containing fluorine. It is preferable that the portion other than the portion adjacent to the semiconductor layer is made of a fluorine-based plasma polymerized film. In an n-type organic semiconductor material, since electrons are carriers, when fluorine with high electronegativity is present in the vicinity of the channel region 51, holes generated by the electron extraction effect of fluorine capture the electrons that are carriers. As a result, transistor characteristics may be degraded. Therefore, when the semiconductor layer adjacent portion is formed of a layer that does not contain fluorine, capture of electrons by fluorine can be prevented, and deterioration of transistor characteristics can be prevented.

Further, since the portion other than the adjacent portion of the semiconductor layer is made of a fluorine-based plasma polymerized film, the above-described effects of improving the density of the gate insulating layer 6 and imparting water repellency and moisture resistance are combined. It is demonstrated.
In this case, the fluorine-free layer is preferably formed by plasma polymerization, but may be formed by other forming methods.
Further, as described above, the gate insulating layer 6 as described above can be easily formed by a method such as switching the type of the source gas during the plasma polymerization.

[3-4] In addition, after forming a polymer film in this way to obtain a plasma polymerized film, the plasma polymerized film may be subjected to a heat treatment (annealing process). Thereby, the denseness of a plasma polymerization film | membrane can be improved. As a result, diffusion of ions from the gate insulating layer 6 to the organic semiconductor layer 5 and adsorption / absorption of moisture in the gate insulating layer 6 can be more reliably suppressed or prevented.
This heat treatment is preferably performed in an inert gas atmosphere such as a nitrogen atmosphere at about 100 to 450 ° C. for about 1 to 10 minutes, more preferably about 150 to 230 ° C. for about 1 to 3 minutes.

In addition, during the plasma polymerization as described above, the film formation rate of the resulting polymer (plasma polymerization film) can be adjusted by appropriately setting at least one of the flow rate and pressure of the source gas.
Specifically, for example, the film formation rate can be increased by increasing the flow rate of the source gas within the aforementioned range. The film forming speed can also be increased by increasing the pressure (partial pressure) of the raw material gas during plasma polymerization.

By setting the flow rate and pressure of the source gas in this way, the probability of plasma polymerization can be controlled, and as a result, the film formation rate can be easily adjusted. For this reason, the film formation rate can be adjusted to efficiently form a polymer, and the formation efficiency of the plasma polymerization film can be increased.
The film formation speed adjusted in this way is not particularly limited, but is preferably adjusted to about 3 to 70 nm / min, more preferably about 5 to 30 nm / min. If the film formation rate is within the above range, a polymer can be obtained particularly efficiently.

On the other hand, if the output of high-frequency power (plasma output) is appropriately set, the density of the obtained polymer, that is, the plasma polymerized film can be adjusted.
For example, by increasing the plasma output within the above range, the density of the obtained plasma polymerized film can be increased.
Thereby, when the gas molecule of source gas and plasma contact, the plasma energy provided to a gas molecule can be adjusted, and the polymerization degree of a plasma polymerization film | membrane can be controlled. Therefore, the density of the plasma polymerized film can be easily adjusted by appropriately setting the plasma output.
Furthermore, by setting the configuration of the plasma polymerization apparatus 100 (for example, the distance between the electrode 130 and the stage 140), the film formation speed, the density of the plasma polymerization film, and the like can be adjusted.
As described above, the gate insulating layer 6 is obtained.

[4] Scanning Line (Gate Electrode) Formation Step Next, as shown in FIG. 4 (f), the scanning line 32 (gate electrode 7) is formed on the gate insulating layer 6.
The scanning line 32 can be formed in the same manner as the source electrode 3 and the drain electrode 4.

That is, after the liquid material as described above is supplied in a substantially straight line so as to form the gate electrodes 7 of the thin film transistors 1 arranged in a line, a film is formed. The scanning line 32 can be formed by performing post-processing (for example, heating, infrared irradiation, application of ultrasonic waves, etc.).
In addition, it is particularly preferable to use an ink jet method for supplying the liquid material. According to the ink jet method, the liquid material can be supplied with high precision corresponding to the scanning lines 32. Thereby, the scanning line 32 can be formed with high dimensional accuracy.

[5] Protective Film Formation Step Next, as shown in FIG. 4G, the protective film 8 is formed so as to cover almost the entire surface of the gate insulating layer 6.
The protective film 8 is formed by supplying a liquid material containing an organic polymer material or a precursor thereof onto the gate insulating layer 6 to form a film, and then performing post-processing (for example, heating) on the film as necessary. , Irradiation with infrared rays, application of ultrasonic waves, etc.).

In this case, as a method for supplying the liquid material onto the gate insulating layer 6, the same method as described in the step [1] can be used.
In this case, the concentration (content) of the organic polymer material in the liquid material is preferably 3% wt / vol or less, more preferably about 0.5 to 2% wt / vol. . When the concentration of the organic polymer material is higher than the above range, the viscosity and spinnability of the liquid material are increased, and the supply (application) operation of the liquid material may become unstable.

Through the steps described above, the active matrix device 30 shown in FIGS. 1 and 2 is obtained.
In such an active matrix device 30, since the gate insulating layer 6 is dense and has a high density, diffusion of ions in the gate insulating layer 6 into the organic semiconductor layer 5 is suppressed or prevented. Accordingly, an increase in off current of the thin film transistor 1 and thus the active matrix device 30 can be prevented, and power consumption can be reduced.
Further, even if such a gate insulating layer 6 is made thin, an increase in gate leakage current is prevented. For this reason, the threshold voltage can also be reduced while keeping the off-state current low. As a result, the gate voltage can be reduced and the power consumption of the thin film transistor 1 (active matrix device 30) can be further reduced.

<Second Embodiment of Active Matrix Device>
Next, a second embodiment of an active matrix device (thin film transistor circuit of the present invention) including the thin film transistor of the present invention will be described.
FIG. 6 is a longitudinal sectional view showing a second embodiment of the active matrix device. In the following description, the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”.

Hereinafter, the active matrix device and the manufacturing method thereof according to the second embodiment will be described. However, the differences from the active matrix device and the manufacturing method according to the first embodiment will be mainly described, and the same matters will be described. The description is omitted.
The active matrix device 30 according to the second embodiment is the same as the active matrix device 30 according to the first embodiment except that the stacking order of the respective parts constituting each thin film transistor 1 is different.

Each thin film transistor 1 in the active matrix device 30 shown in FIG. 6 includes a gate electrode 7, a gate insulating layer 6, a source electrode 3 and a drain electrode 4, an organic semiconductor layer 5, and a protective film 8 in this order. It is configured by stacking from the 50th side.
That is, each thin film transistor 1 is a thin film transistor having a configuration in which the gate 7 electrode is provided on the substrate 50 side with respect to the source electrode 3 and the drain electrode 4 via the gate insulating layer 6, that is, a bottom gate thin film transistor.

Specifically, in the thin film transistor 1, the gate electrode 7 is provided on the substrate 50, and the gate insulating layer 6 is provided so as to cover the gate electrode 7. On the gate insulating layer 6, the source electrode 3 and the drain electrode 4 are provided separately with a region corresponding to the gate electrode 7 as a gap. An organic semiconductor layer 5 is provided so as to cover the gap between the source electrode 3 and the drain electrode 4 and part of these electrodes 3 and 4.
A protective film 8 is provided so as to cover the organic semiconductor layer 5 and the electrodes 3 and 4.

Such an active matrix device 30 includes: [4] gate electrode forming step, [3] gate insulating layer forming step, [1] electrode and wiring forming step in the manufacturing method of the active matrix device 30 according to the first embodiment, [2] The organic semiconductor layer forming step and [5] protective film forming step can be performed by performing in this order.
The active matrix device 30 and the manufacturing method thereof according to the second embodiment as described above can provide the same operations and effects as those of the active matrix device 30 and the manufacturing method thereof according to the first embodiment.

<Electronic device>
Next, an electrophoretic display device will be described as an example of an electronic device (an electronic device of the present invention) including the active matrix device 30 as described above.
FIG. 7 is a longitudinal sectional view showing an embodiment when the electronic device of the present invention is applied to an electrophoretic display device.

The electrophoretic display device 20 shown in FIG. 7 includes an active matrix device 30 provided on a substrate 50 and an electrophoretic display unit 40 electrically connected to the active matrix device 30.
As shown in FIG. 7, the electrophoretic display unit 40 includes a pixel electrode 41, a microcapsule 42, a transparent electrode (common electrode) 43, and a transparent substrate 44 that are sequentially stacked on a substrate 50. Yes.
The microcapsule 42 is fixed between the pixel electrode 41 and the transparent electrode 43 by a binder material 45.

The pixel electrodes 41 are divided so as to be regularly arranged in a matrix, that is, vertically and horizontally.
In each capsule 42, an electrophoretic dispersion liquid 420 including a plurality of types of electrophoretic particles having different characteristics, and in this embodiment, two types of electrophoretic particles 421 and 422 having different charges and colors (hue) are encapsulated. Has been.

In the electrophoretic display device 20, when a selection signal (selection voltage) is supplied to one or a plurality of scanning lines 32, the thin film transistor connected to the scanning line 32 to which the selection signal (selection voltage) is supplied. 1 is turned on.
Thereby, the data line 31 and the pixel electrode 41 connected to the thin film transistor 1 are substantially conducted. At this time, if desired data (voltage) is supplied to the data line 31, this data (voltage) is supplied to the pixel electrode 41.
As a result, an electric field is generated between the pixel electrode 41 and the transparent electrode 43, and the electrophoretic particles 421 and 422 are either one of the electrophoretic particles 421 and 422 depending on the direction and strength of the electric field and the characteristics of the electrophoretic particles 421 and 422. Electrophoresis in the direction of the electrode.

On the other hand, when the supply of the selection signal (selection voltage) to the scanning line 32 is stopped from this state, the thin film transistor 1 is turned off, and the data line 31 and the pixel electrode 41 connected to the thin film transistor 1 are in a non-conductive state. Become.
Therefore, by supplying and stopping the selection signal to the scanning line 32 or by appropriately combining the supply and stop of data to the data line 31, the display surface side (transparent substrate 44 side) of the electrophoretic display device 20 is performed. A desired image (information) can be displayed.
In particular, in the electrophoretic display device 20 according to the present embodiment, it is possible to display a multi-tone image by changing the colors of the electrophoretic particles 421 and 422.

In addition, since the electrophoretic display device 20 according to the present embodiment includes the active matrix device 30, the thin film transistor 1 connected to the specific scanning line 32 can be selectively turned on / off. Since problems are unlikely to occur and circuit operation can be speeded up, high-quality images (information) can be obtained.
In addition, since the electrophoretic display device 20 according to the present embodiment operates with a low driving voltage, power saving can be achieved. In particular, since the thin film transistor 1 included in the active matrix device 30 has a small off-state current, power consumption during standby (non-operation) can be reduced.
Note that the electronic device of the present invention is not limited to the application to the electrophoretic display device 20, and can be applied to a liquid crystal display device, an organic or inorganic EL display device, and the like.

<Electronic equipment>
Such an electrophoretic display device 20 can be incorporated into various electronic devices. Hereinafter, the electronic apparatus of the present invention including the electrophoretic display device 20 will be described.
<< Electronic Paper >>
First, an embodiment when the electronic apparatus of the present invention is applied to electronic paper will be described.
FIG. 8 is a perspective view showing an embodiment when the electronic apparatus of the present invention is applied to electronic paper.
An electronic paper 600 shown in this figure includes a main body 601 composed of a rewritable sheet having the same texture and flexibility as paper, and a display unit 602.
In such an electronic paper 600, the display unit 602 includes the electrophoretic display device 20 as described above.

<< Display >>
Next, an embodiment when the electronic apparatus of the present invention is applied to a display will be described.
9A and 9B are diagrams showing an embodiment in which the electronic apparatus of the invention is applied to a display, in which FIG. 9A is a cross-sectional view and FIG. 9B is a plan view.
A display 800 shown in this figure includes a main body 801 and an electronic paper 600 that is detachably provided to the main body 801. The electronic paper 600 has the same configuration as described above, that is, the configuration shown in FIG.

  The main body 801 has an insertion port 805 into which the electronic paper 600 can be inserted on the side (right side in the drawing), and two pairs of conveying rollers 802a and 802b are provided inside. When the electronic paper 600 is inserted into the main body 801 through the insertion port 805, the electronic paper 600 is installed in the main body 801 in a state of being sandwiched between the pair of conveyance rollers 802a and 802b.

  Further, a rectangular hole 803 is formed on the display surface side of the main body 801 (the front side in the drawing (b) below), and a transparent glass plate 804 is fitted into the hole 803. Thereby, the electronic paper 600 installed in the main body 801 can be viewed from the outside of the main body 801. That is, in the display 800, the display surface is configured by visually recognizing the electronic paper 600 installed in the main body 801 on the transparent glass plate 804.

In addition, a terminal portion 806 is provided at the leading end portion (left side in the drawing) of the electronic paper 600, and the terminal portion with the electronic paper 600 installed on the main body portion 801 is provided inside the main body portion 801. A socket 807 to which 806 is connected is provided. A controller 808 and an operation unit 809 are electrically connected to the socket 807.
In such a display 800, the electronic paper 600 is detachably installed on the main body 801, and can be carried and used while being detached from the main body 801.
In such a display 800, the electronic paper 600 is configured by the electrophoretic display device 20 as described above.

  Note that the electronic apparatus of the present invention is not limited to the application to the above, and for example, a television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, an electronic Examples include newspapers, word processors, personal computers, workstations, videophones, POS terminals, and devices equipped with touch panels. The electrophoretic display device 20 can be applied to the display units of these various electronic devices. is there.

The method for manufacturing a thin film transistor, the thin film transistor, the thin film transistor circuit, the electronic device, and the electronic device of the present invention have been described above, but the present invention is not limited to these.
For example, the configuration of each part of the thin film transistor, the thin film transistor circuit, the electronic device, and the electronic apparatus of the present invention can be replaced with an arbitrary one that can exhibit the same function, or an arbitrary configuration can be added. it can.
Moreover, in the manufacturing method of the thin-film transistor of this invention, arbitrary processes can also be added as needed.

Next, specific examples of the present invention will be described.
1. Production of display device (Example 1)
First, a glass substrate having an average thickness of 1 mm was prepared and washed with water (cleaning liquid). Note that the glass substrate was previously subjected to oxygen plasma treatment.
Next, a source electrode and a drain electrode were formed by vapor-depositing Au on the substrate.
Next, a trimethylbenzene solution in which F8T2 (fluorene-bithiophene copolymer) is dissolved is applied by a spin coating method so as to cover the source electrode and the drain electrode, and then the liquid film is dried. did. Thereby, an organic semiconductor layer having an average thickness of 30 nm was formed. Note that F8T2 is a p-type organic semiconductor material.

Next, the glass substrate on which the source electrode, the drain electrode, and the organic semiconductor layer were formed was placed on the stage in the vacuum chamber shown in FIG.
Then, after reducing the pressure in the vacuum chamber to 9 × 10 ⁻⁵ Torr (1.2 × 10 ⁻⁸ MPa), argon gas (addition gas) and CHF ₃ gas (raw material gas) are introduced into the vacuum chamber, Plasma polymerization of CHF ₃ was performed under the conditions described above to obtain a plasma polymerization film.

<Conditions for plasma polymerization>
・ Gas pressure: 0.2 Torr (2.7 × 10 ⁻⁵ MPa)
・ Gas flow rate: 50sccm
・ Plasma output: 25W
・ High frequency power frequency: 13.56 MHz
・ Processing time: 6 minutes ・ Deposition rate: 8 nm / min
Thus, a gate insulating layer having an average thickness of 50 nm was formed on the organic semiconductor layer.
Next, Au was vapor-deposited on a portion of the gate insulating layer corresponding to a region between the source electrode and the drain electrode, thereby forming a gate electrode.
Thus, a thin film transistor was obtained.

(Example 2)
A thin film transistor was obtained in the same manner as in Example 1 except that the CHF ₃ gas was changed to C ₂ F ₆ gas.
(Example 3)
A thin film transistor was manufactured in the same manner as in Example 1 except that a gas obtained by vaporizing C ₈ F ₁₈ was used instead of the CHF ₃ gas.

Example 4
A thin film transistor was manufactured in the same manner as in Example 1 except that the plasma output during plasma polymerization was changed to 10 W.
(Example 5)
A thin film transistor was manufactured in the same manner as in Example 1 except that the flow rate of CHF ₃ gas was set to 100 sccm.
The film formation rate during plasma polymerization was 12 nm / min.
(Example 6)
A thin film transistor was manufactured in the same manner as in Example 1 except that the atmospheric pressure during the plasma polymerization was changed to 0.4 Torr (5.3 × 10 ⁻⁵ MPa).
The film formation rate during plasma polymerization was 15 nm / min.

(Example 7)
A thin film transistor was manufactured in the same manner as in Example 1 except that the gate insulating layer was formed as follows.
First, a plasma polymerized film was formed in the same manner as in Example 1 using C ₂ H ₄ (ethylene) gas as a source gas. In addition, the processing time of plasma polymerization was 3 minutes.
Next, the raw material gas was changed to CHF ₃ gas, and a plasma polymerization film was similarly formed. The plasma polymerization treatment time was 3 minutes. Thereby, a gate insulating layer having an average thickness of 50 nm was formed on the organic semiconductor layer.
(Example 8)
A thin film transistor was manufactured in the same manner as in Example 7 except that an organic semiconductor layer composed of fluorinated copper phthalocyanine was formed by vapor deposition. Note that fluorinated copper phthalocyanine is an n-type organic semiconductor material.

(Comparative Example 1)
A thin film transistor was manufactured in the same manner as in Example 1 except that the gate insulating layer was formed by the following method.
First, the 1-propanol solution which melt | dissolved polyvinylphenol (PVP) was apply | coated on the glass substrate in which the source electrode, the drain electrode, and the organic-semiconductor layer were formed with the spin coat method, and the liquid film was formed.
Next, this liquid film was dried to form a gate insulating layer having an average thickness of 100 nm.
(Comparative Example 2)
A thin film transistor was manufactured in the same manner as in Comparative Example 1 except that an organic semiconductor layer composed of fluorinated copper phthalocyanine was formed in the same manner as in Example 8.

2. Evaluation 2.1 Evaluation of Density of Gate Insulating Layer The density of the gate insulating layer was measured for each thin film transistor obtained in each example and each comparative example.
In addition, the density was measured by the X-ray reflectivity measuring method (GIXR).
The measurement results are shown in Table 1. Note that the density of the gate insulating layer in each thin film transistor was a relative value when the density of the gate insulating layer in the thin film transistor obtained in each comparative example was 1.

2.2 Evaluation of off-state current About the thin-film transistor obtained in each Example and each comparative example, off-current was measured, respectively, and evaluated according to the following criteria.
◎: Off current is very small ○: Off current is slightly large, but there is no practical problem △: Off current is slightly large, but can be used depending on the application ×: Off current is very large and practicality is poor Note that the off-current was measured immediately after the manufacture of each thin film transistor and after being left for 30 days.
In addition, the environment in which each thin film transistor is left is as follows: air temperature 23 ° C., humidity 70% H. It was.
The evaluation results are shown in Table 1.

2.3 Evaluation of Carrier Mobility Regarding the thin film transistors obtained in the respective examples and comparative examples, the carrier movement in the channel region was measured and evaluated according to the following criteria.
A: Very high carrier mobility B: Slightly high carrier mobility B: Slightly low carrier mobility X: Very low carrier mobility Table 1 shows the evaluation results.

As is clear from Table 1, the density of the gate insulating layer included in the thin film transistor obtained in each example was higher than that of the gate insulating layer included in the thin film transistor obtained in the comparative example.
In addition, the thin film transistor obtained in each example had a lower off current than the thin film transistor obtained in the comparative example. In particular, in Examples 1, 3, 5, 6, and 8, the tendency was remarkable over a long period of time. This tendency is presumed to be due to the particularly high density of the gate insulating layers of Examples 1, 3, 5, 6, and 8.
On the other hand, Example 8 had higher carrier mobility than the thin film transistor of Comparative Example 2 using an n-type organic semiconductor layer.

1 is a plan view showing a first embodiment of an active matrix device. It is the XX sectional view taken on the line in FIG. It is a figure for demonstrating the manufacturing method of an active matrix apparatus. It is a figure for demonstrating the manufacturing method of an active matrix apparatus. It is a schematic diagram which shows the structure of a plasma polymerization apparatus. It is a longitudinal cross-sectional view which shows 2nd Embodiment of an active matrix apparatus. It is a longitudinal cross-sectional view which shows embodiment of an electrophoretic display apparatus. It is a perspective view which shows embodiment of electronic paper. It is a figure which shows embodiment of a display.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Thin film transistor 3 ... Source electrode 4 ... Drain electrode 5 ... Organic-semiconductor layer 51 ... Channel region 6 ... Gate insulating layer 7 ... Gate electrode 8 ... Protective film 9 ... Metal film 20 ... Electricity Electrophoretic display device 30... Active matrix device 31... Data line 32... Scanning line 33 .. connection electrode 40... Electrophoretic display section 41. 422 ... Electrophoretic particles 43 ... Transparent electrode 44 ... Transparent substrate 45 ... Binder material 50 ... Substrate 100 ... Plasma polymerization apparatus 110 ... Vacuum pump 120 ... Vacuum chamber 121 ... Insulator 130 ... Electrode 140... Stage 150 .. High frequency power supply 160... Gas supply pipe 161, 171. ... Raw material supply pipe 180 ... Gas supply source 190 ... Raw material container 191 ... Heater 600 ... Electronic paper 601 ... Main body 602 ... Display unit 800 ... Display 801 ... Main body 802a, 802b ... Conveying roller Pair 803 ... Hole 804 ... Transparent glass plate 805 ... Insertion slot 806 ... Terminal part 807 ... Socket 808 ... Controller 809 ... Operation part

Claims (17)

A thin film transistor for manufacturing a thin film transistor provided on a substrate and comprising a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer, and a gate insulating layer that insulates the source electrode and the drain electrode from the gate electrode A manufacturing method of
Forming the source electrode and the drain electrode on the substrate;
Forming the organic semiconductor layer at least between the source electrode and the drain electrode;
Forming the gate insulating layer so as to cover the source electrode, the drain electrode, and the organic semiconductor layer;
Forming the gate electrode on the gate insulating layer,
In the step of forming the gate insulating layer, at least a part of the gate insulating layer in the thickness direction is formed by plasma polymerizing a source gas and depositing the obtained polymer. Production method. A thin film transistor for manufacturing a thin film transistor provided on a substrate and comprising a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer, and a gate insulating layer that insulates the source electrode and the drain electrode from the gate electrode A manufacturing method of
Forming the gate electrode on the substrate;
Forming the gate insulating layer on the gate electrode;
Forming the organic semiconductor layer on the gate insulating layer;
Forming the source electrode and the drain electrode on the organic semiconductor layer,
In the step of forming the gate insulating layer, at least a part of the gate insulating layer in the thickness direction is formed by plasma polymerizing a source gas and depositing the obtained polymer. Production method.   The method of manufacturing a transistor according to claim 1, wherein the source gas contains a fluorine-based gas as a main component. The method for manufacturing a transistor according to claim ₃ , wherein the fluorine-based gas is CHF ₃ .   3. The method of manufacturing a transistor according to claim 1, wherein the source gas includes a vaporized liquid substance containing fluorine. The method for manufacturing a transistor according to claim 5, wherein the fluorine-containing liquid material is C ₈ F ₁₈ . The organic semiconductor layer is composed of a p-type organic semiconductor material,
In the step of forming the gate insulating layer, at least a portion of the gate insulating layer on the organic semiconductor layer side is formed by plasma polymerizing a source gas containing fluorine and depositing the obtained polymer. Item 7. A method for producing a transistor according to any one of Items 1 to 6.   The transistor manufacturing method according to claim 1, wherein the density of the gate insulating layer is adjusted by setting a plasma output in the plasma polymerization.   9. The method for manufacturing a transistor according to claim 1, wherein a film formation rate of the gate insulating layer is adjusted by setting at least one of a flow rate and a pressure of the source gas in the plasma polymerization.   A transistor manufactured by the method for manufacturing a thin film transistor according to claim 1. A thin film transistor comprising a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer, and a gate insulating layer that insulates the source electrode, the drain electrode, and the organic semiconductor layer from the gate electrode,
A transistor characterized in that at least a part of the gate insulating layer in the thickness direction is formed of a dense plasma polymerized film. The organic semiconductor layer is composed of a p-type organic semiconductor material,
The transistor according to claim 11, wherein at least a portion of the gate insulating layer adjacent to the organic semiconductor layer is formed of a plasma polymerization film containing fluorine. A thin film transistor comprising a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer, and a gate insulating layer that insulates the source electrode, the drain electrode, and the organic semiconductor layer from the gate electrode,
The density of the said gate insulating layer is 1.5-2.5 g / cm < ³ >, The transistor characterized by the above-mentioned.   The transistor according to claim 10, wherein the gate insulating layer has an average thickness of 10 to 5000 nm.   A transistor circuit comprising the transistor according to claim 10.   An electronic device comprising the transistor circuit according to claim 15.   An electronic apparatus comprising the electronic device according to claim 16.

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