JP2005241885A - Method for creating cam data for electronic circuit board, cad/cam system for electronic circuit board, and method for producing electronic circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for creating CAM data for an electronic circuit board by which CAD data which reflect the opening shape of a recognition mark for alignment in a solder resist layer can be appropriately and efficiently converted to CAM data of an exposure mask for photolithography for forming the openings. <P>SOLUTION: In order to form openings of a recognition mark for alignment of a substrate in a solder resist layer by a photolithography process using a photosensitive resin, the mask pattern of the recognition mark in a mask pattern for the openings is corrected so that the opening shape of the recognition mark reflected in CAD data has two segments which intersect each other in a concave shape on the opening side and that an etching margin for the segments becomes larger with the intersection of the segments as a correction reference point, as it becomes more distant from the correction reference point , and conversion as CAM data is performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electronic circuit board CAM data creation method, an electronic circuit board CAD / CAM system, and an electronic circuit board manufacturing method.

JP 2000-276505 A

  Semiconductor chips such as ICs and microprocessors have been rapidly integrated in recent years, so that the number of terminals at the input / output section of the chip is also increasing significantly. As a result, the number of wiring parts in electronic circuit boards for connecting such chips has also increased rapidly, and a multilayer type in which a multilayer wiring part is formed through an insulating layer such as a polymer material or ceramic. The number of package substrates is increasing. Recently, in order to efficiently design such an electronic circuit board, a design system using a computer drawing process, a so-called CAD (Computer Aided Design) system has been used (Patent Document 1). This opens a drawing screen on the display device, and displays circuit elements such as wiring parts, surface conductor patterns for grounding or power supply, vias connecting different wiring layers, or pads and lands forming wiring terminal parts, as CAD. As a data, a board design drawing is obtained by drawing on a drawing layer using an input device such as a mouse.

  By the way, in the conventional CAD system, the position, shape or dimension of the board element inputted on the board design drawing is inputted as information on the completed board to the last, and therefore cannot be directly used in the manufacturing process of the electronic circuit board. There is. For example, wiring parts, lands, pads, or surface conductor patterns are formed by printing and baking a conductor pattern on a ceramic green sheet using a conductor paste and firing, in the case of an organic substrate. A conductive pattern is formed by etching a thin metal layer using photolithography. In addition, regarding vias, drilling or laser drilling of ceramic green sheets is used for ceramic substrates, and drilling or laser drilling is used for organic substrates. It is formed by.

  By the way, CAD data (dimensions, shapes, formation positions in a substrate, etc.) of each substrate element included in the design drawing is design information input while imagining a product substrate. On the other hand, what is required when actually manufacturing a board using the design drawing is manufacturing graphic information corresponding to each board element, and there is a large deviation from CAD data which is design information of the product board. In this case, the CAD data of the substrate element cannot be directly used for substrate manufacture.

  For example, in a ceramic substrate, the dimensions of circuit board elements such as wiring patterns and vias indicated by CAD data are given as dimensions after firing. However, when a substrate is manufactured using a ceramic green sheet, what is necessary in the process is It is a dimension before firing and needs to be converted into graphic information for production in consideration of firing shrinkage and the like. If the shrinkage during firing is uniform, the conversion operation is relatively simple, but actually, the conversion conditions of CAD data differ depending on the formation state of each circuit board element. Also, in the case of an organic substrate, when forming a conductor pattern or a via by photolithography, it is necessary to consider individual conversion conditions because the etching conditions differ depending on the formation state of each circuit board element. In any case, since the CAD system for electronic circuit boards has various forms of conversion of CAD data to graphic information for manufacturing, the CAM (Computer Aided Manufacturing) of the manufacturing process is compared with a CAD system for machining such as a machining center. ) Is far behind in the current situation. Therefore, field engineers often have to convert CAD data into graphic information for manufacturing by manual calculation, and it has been difficult to avoid a decrease in manufacturing efficiency and a prolonged delivery date.

  In addition, when an electronic component such as an IC is mounted on a substrate in a flip chip format, it is necessary to form a solder bump pattern on the land formed on the electronic substrate using a solder paste. Solder bumps are formed by reflow treatment after a bump pattern is formed by cream solder printing application using a paste application mask, which suppresses solder wetting and spreading to the substrate during reflow. Therefore, a solder resist layer is formed on the outermost surface of the substrate. An opening is formed in the solder resist layer in a shape corresponding to the bump formation position, and a solder bump is formed on the solder land exposed in the opening. The solder resist layer is made of a photosensitive resin, and a photolithography process is employed to form the opening. Specifically, an exposure mask having an opening formation pattern is superimposed on the photosensitive resin layer and exposed to cure the resin other than the opening planned portion, while the uncured resin in the opening planned portion is etched away with a solvent or the like. And open.

  By the way, usually, on an electronic circuit board, an alignment mark or fiducial mark (Fiducial Mark) for alignment used for mounting a surface mounting component such as a semiconductor chip on the board (hereinafter collectively referred to as alignment mark). Mark (also referred to as Alignment Mark). This alignment mark consists of a conductor layer formed on the solder resist layer, and is completely exposed from the opening of the solder resist layer. As described above, the alignment mark is formed as a part of the opening of the solder resist layer by a photolithography process. However, the etching solution also removes the resin that forms the alignment mark opening during etching, and an accurate alignment mark opening shape is not formed. As a result, in the process of mounting components on the substrate, etc. There was a problem that the position of the camera could not be aligned correctly.

  An object of the present invention is to appropriately and efficiently convert CAD data reflecting an alignment mark figure formed on a solder resist layer into CAM data including an exposure mask for photolithography for forming the alignment mark. Another object of the present invention is to provide an electronic circuit board CAM data creation method, an electronic circuit board CAD / CAM system used therefor, and an electronic circuit board manufacturing method using the electronic circuit board CAD / CAM system.

Means for Solving the Problems and Effects of the Invention

In the electronic circuit board CAM data creation method of the present invention, in the electronic circuit board in which conductor layers and dielectric layers are alternately laminated, the opening of the solder resist layer formed on the main surface of the electronic circuit board is formed by CAD. Create as data,
In order to form the opening of the solder resist layer by a photolithography process using a photosensitive resin, the opening of the solder resist layer reflected in the CAD data is used as the opening mask pattern of the exposure mask for photolithography as CAM data. As well as conversion
The opening shape of the recognition mark of the substrate formed in the surface of the solder resist layer has two line segments intersecting the concave shape on the opening side, and the intersection of these line segments is a correction reference point. The mask pattern of the recognition mark in the opening mask pattern is corrected so that the etching allowance for the line segment becomes wider as the distance from the correction reference point is increased.

The CAD / CAM system of the present invention is a CAD / CAM system for designing and manufacturing an electronic circuit board in which conductor layers and dielectric layers are alternately laminated.
A drawing layer setting means for setting a plurality of drawing layers corresponding to the conductor layer and the dielectric layer to be formed on the electronic circuit board;
Of the board elements constituting the electronic circuit board, those predetermined as the drawing object are used as the drawing object elements, and the CAD data for specifying the design dimensions, shapes, and arrangement positions of the drawing object elements is drawn in the drawing. CAD data input means for inputting on the layer;
The manufacturing process of the corresponding element of the manufacturing target element itself or the manufacturing jig of the manufacturing target element, with the drawing target element or an additional element formed on the electronic circuit board in a form associated with the drawing target element as the manufacturing target element CAM data conversion means for creating CAM data specifying the above dimensions, shape, and arrangement position by conversion from the CAD data;
CAM data output means for outputting the CAM data,
The manufacturing target element is an opening of a solder resist layer formed on the main surface of the electronic circuit board, and the opening of the solder resist layer is input and created as the CAD data by CAD data input means.
The CAM data conversion means uses an opening mask pattern of an exposure mask for photolithography to form the opening of the solder resist layer reflected in the CAD data in order to form the opening of the solder resist layer by a photolithography process using a photosensitive resin. And the opening shape of the recognition mark of the substrate formed in the plane of the solder resist layer has two line segments that intersect the concave shape on the opening side, The intersection pattern of the line segments is used as a correction reference point, and the mask pattern of the recognition mark in the opening mask pattern is corrected so that the etching allowance for the line segment becomes wider as the distance from the correction reference point increases. .

  A board element of an electronic circuit board is a circuit constituent unit on a board structure built in a conductor layer or an insulating layer. In the conductor layer, in addition to the wiring portion, a ground conductor, a power supply conductor, a specially shaped wiring portion, a surface conductor pattern that forms a capacitor electrode, and terminal portions such as pads and lands are formed as substrate elements. In addition, vias that electrically connect different conductor layers are formed as substrate elements in the insulating layer. In addition, a solder land used as a base of a solder bump used for flip chip bonding or the like can be formed as a substrate element on the conductor layer located on the outermost surface side of the substrate. In this case, a solder bump formed later on the solder land is one of the substrate elements. Further, when the insulating layer formed on the outermost surface of the substrate is a solder resist layer covering the periphery of the solder land, an opening formed in the solder resist layer, for example, a solder opening for exposing the solder land is also a substrate element. one of.

  In addition, all of the board elements may not be drawn by CAD. For example, while a solder land (or solder opening) is used as a drawing target element, a solder bump formed in a subsequent process on the solder land may not be drawn particularly on CAD. In this case, solder lands and solder openings are elements to be drawn, and the solder bumps are additional elements formed on the electronic circuit board in a form associated with the elements to be drawn. The board element to be manufactured in the board manufacturing process, that is, the manufacturing target element is the above-mentioned drawing target element, and when solder bumps are handled as additional elements, the combination of the drawing target element and the additional elements is It is an element to be manufactured.

  The CAD data of the opening formed in the solder resist layer is the opening of the solder resist layer reflected in the CAD data when the alignment mark is formed in the solder resist layer by a photolithography process using a photosensitive resin in the substrate manufacturing process. It is necessary to convert the inner diameter into CAM data composed of the outer diameter of the opening mask pattern of the exposure mask for photolithography. There are two types of photosensitive resins: one that suppresses curing of the exposed portion (hereinafter referred to as “positive type”) and one that promotes curing of the exposed portion (hereinafter referred to as “negative type”). There are two types. In particular, when it is desired to form a small-diameter opening, it is advantageous to use a positive type resin rather than using a negative type resin whose opening mask pattern to be transferred is more likely to be crushed than the wraparound of light during exposure. Many. When such a positive type resin is used, the exposure mask is formed such that the opening mask pattern is a light transmitting portion and the background portion of the opening mask pattern is a light shielding portion. .

  When forming a solder resist layer using a positive photosensitive resin, as shown in FIG. 14, when the exposure mask 62 is overlaid on the uncured solder resist layer (8 ′) and exposed, the solder resist layer (8 In (1), a portion immediately below the opening mask pattern (62a) serving as a light transmitting portion is exposed to light, and curing is suppressed. Accordingly, after the unexposed portion (8'c) is cured at room temperature or at a suitably elevated curing temperature, the exposed portion (8'a) is etched with a solvent or the like to form the opening (8a). A solder resist layer (8) is obtained.

However, in the case of an alignment mark having a triangular opening shape as shown in FIG. 19A, the shape after exposure / etching becomes a shape as shown by a broken line in FIG. This is because the arrival time of the etchant is shorter at the side than at the apex of the triangle, and as a result, the side is exposed to the etchant longer than the apex. It has been found from the results of the study by the present inventors that ΔD ₁ between the opening mask pattern and the actual opening shape increases as the distance increases. In the present invention, CAM data is created from CAD data so that ΔD ₁ is zero.

  In the CAD / CAM system for an electronic circuit board according to the present invention, the CAM data creation means is configured such that the opening shape of the recognition mark (that is, the alignment mark) of the board formed in the surface of the solder resist layer is on the opening side. The opening mask pattern has two line segments intersecting the concave shape, and the intersection of the line segments is used as a correction reference point, and the etching allowance for the line segment becomes wider as the distance from the correction reference point increases. Correct the mask pattern of the recognition mark. Thereby, the CAD data of the substrate element reflecting the shape of the alignment mark to be obtained is converted into appropriate CAM data (that is, the opening shape of the opening mask used for forming the alignment mark) from which the alignment mark according to the design value is obtained. Conversion can be performed reliably and efficiently.

  In addition, the CAM data creation means of the present invention, when the opening shape of the recognition mark (that is, the alignment mark) of the substrate formed in the plane of the solder resist layer is a triangle, the etching allowance is provided at each side of the triangle. The mask pattern of the recognition mark in the opening mask pattern can be corrected so that the width becomes wider as the distance from each vertex increases. Also by this correction, CAD data of the substrate element reflecting the shape of the alignment mark to be obtained can be reliably and efficiently converted into appropriate CAM data from which an alignment mark as designed can be obtained.

  Furthermore, the CAM data creation means according to the present invention, when the opening shape of the recognition mark (that is, the alignment mark) of the substrate formed in the surface of the solder resist layer is a cross shape, on the opening side of the cross shape. The mask pattern of the recognition mark in the opening mask pattern is corrected so that the etching allowance for the line segment forming the concave vertex becomes wider as the distance from the concave vertex increases, and the cross-shaped opening side The mask pattern of the recognition mark in the opening mask pattern can be corrected so that the etching allowance for the line segment forming the convex vertex becomes wider as the convex vertex is approached. Also by this correction, CAD data of the substrate element reflecting the shape of the alignment mark to be obtained can be reliably and efficiently converted into appropriate CAM data from which an alignment mark as designed can be obtained.

  Next, when the computer program of the present invention is installed in a computer, the computer is caused to function as each means constituting the CAD / CAM system for an electronic circuit board of the present invention. As a result, the CAD / CAM system of the present invention can be easily realized on a computer. The computer program is recorded on a computer-readable recording medium such as an optical recording medium (CD-ROM, DVD, etc.) or a magneto-optical recording medium (MO, etc.), and is read by a dedicated reader. The program can be installed on a fixed storage device (for example, a hard disk drive) provided on the computer side, or the whole or a part of the program can be downloaded from a host computer through an electric communication line such as the Internet. Can be installed.

The electronic circuit board manufacturing method of the present invention uses the CAD / CAM system for electronic circuit boards of the present invention to input the drawing target elements necessary for the electronic circuit board to be obtained as CAD data on the drawing layer. An electronic circuit board design process for creating electronic circuit board design information as a set of CAD data,
An electronic circuit board manufacturing process for manufacturing an electronic circuit board using the output contents of the CAM data output means of the CAM data created by the CAM data creation means based on the CAD data,
In the electronic circuit board manufacturing process, an exposure mask having an opening mask pattern specified by the CAM data is created based on the CAM data created by the CAM data creating means, and the exposure mask is used on the electronic circuit board. A photolithography process for forming a solder resist layer having an opening to be obtained is performed.

  According to the electronic circuit board manufacturing method of the present invention, a solder resist layer having an alignment mark with an accurate shape can be obtained easily and reliably by using the CAD / CAM system for an electronic circuit board of the present invention. Therefore, it is possible to reliably align the board, and to reduce problems when mounting components on the board.

  The object of easily and surely obtaining a solder resist layer having an alignment mark of an accurate shape is realized by using a CAD / CAM system for an electronic circuit board provided with the CAM data creation means of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to examples shown in the drawings.
FIG. 2 is a block diagram showing an overall configuration of an embodiment of a CAD / CAM system 100 for electronic circuit boards (hereinafter also simply referred to as a CAD / CAM system) according to the present invention. The CAD / CAM system 100 includes a computer main body 112 including a CPU 103, a ROM 104, a RAM 105, an input / output interface 102, and the like. As peripheral devices, input means such as a keyboard 106 or a mouse 107, a CD-ROM drive 108, or a flexible The whole is constructed as a computer system to which a recording medium reading means such as a disk drive 109, a hard disk drive (hereinafter referred to as HDD) 110, a monitor 113 connected via a monitor control unit 111, a printer 114, etc. are connected. Yes.

  The CPU 103 is a main component of a drawing layer setting unit, a CAD data input unit, a CAM data conversion unit, and a CAM data output unit. The keyboard 106 or the mouse 107 is the main part of the CAD data input means together with the CPU 103. Further, the input / output interface 102 is a CAM data output means for outputting CAM data converted and created by the CAM data conversion means based on the CAD data, in addition to a drawing output means for printing out the design drawing of the electronic circuit board that has been drawn. Function as.

  The HDD 110 stores an operating system program (hereinafter referred to as OS) 161 and an application program (hereinafter referred to as application) 162. The application 162 is a computer program for realizing the functions of the CAD / CAM system 100, and operates on the OS 161 in the form of using the application work memory 152 as a work area. This is stored in a computer-readable state on, for example, the CD-ROM 120 and installed in a predetermined storage area on the HDD 110. Further, the HDD 110 includes a data file (CAD data file) 163 of a created drawing, a CAM data file 164 converted and generated based on the data file, and a correction used when converting CAD data into CAM data. A correction data file 165 including a table (conversion table) is stored. On the other hand, the RAM 105 is provided with a work memory 151 of the OS 161 and a work memory 152 of an application.

  FIG. 1 shows a cross-sectional structure of an example of an electronic circuit board to which the CAD / CAM system 100 is applied (this electronic circuit board 1 is configured as an organic substrate, but the present invention is not limited thereto). It can also be applied to ceramic substrates). That is, the electronic circuit board 1 is formed on both surfaces of a plate-shaped core material 2 made of a heat-resistant resin plate (for example, a bismaleimide-triazine resin plate) or a fiber reinforced resin plate (for example, a glass fiber reinforced epoxy resin). The core conductor layers M1 and M11 are formed in a predetermined pattern, respectively. These core conductor layers M1 and M11 are formed as surface conductor patterns that cover most of the surface of the core material 2, and are used as a power supply layer or a ground layer. On the other hand, the core material 2 is formed with a through-hole 12 drilled by a drill or the like, and a through-hole conductor 30 is formed on the inner wall surface thereof to make the core conductor layers M1 and M11 conductive. The through hole 12 is filled with a resin filling material 31 such as an epoxy resin.

  In addition, first via layers (insulating layers or build-up layers) V1 and V11 made of the photosensitive resin composition 6 are formed on the core conductor layers M1 and M11, respectively. Further, first wiring conductor layers M2 and M12 each having a wiring portion 7 are formed on the surface by Cu plating. The core conductor layers M1 and M11 and the first wiring conductor layers M2 and M12 are interconnected by vias 34, respectively. Similarly, second via layers (insulating layers or build-up layers) V2 and V12 using the photosensitive resin composition 6 are formed on the first wiring conductor layers M2 and M12, respectively. Second wiring conductor layers M3 and M13 are formed on the surfaces by Cu plating, respectively. The first wiring conductor layers M2 and M12 and the second wiring conductor layers M3 and M13 are connected to each other through vias 34, respectively. As shown in FIG. 7, the via 34 is opposite to the via hole 34h, the via conductor 34s provided on the inner peripheral surface thereof, the via pad 34p provided to be electrically connected to the via conductor 34s on the bottom surface side, and the via pad 34p. A via land 34l projecting outward from the peripheral edge of the opening of the via conductor 34h on the side.

  Next, returning to FIG. 1, a surface wiring conductor layer M <b> 3 is formed on the second via layer V <b> 2 on the first main surface side of the core material 2, and is electrically connected to a plurality of solder lands 10 and a part thereof. A wiring portion 7 is provided. These solder lands 10 are arranged in a square shape at the substantially central portion of the substrate by electroless Ni-P plating and Au plating, and together with the solder bumps 11 formed thereon, refer to the chip mounting portion (see the drawing screen 40 in FIG. 4). ) Is formed. Note that the surface of the dielectric layer 6 (second via layer V2) on which the solder lands 10 are disposed is used as a bump reference plane CP used as a reference for the solder bump height.

  On the other hand, a back surface wiring conductor layer M13 is formed on the second via layer V12 on the second main surface side of the core material 2. The back surface wiring conductor layer M13 is formed with a plurality of lands 17 for connecting the substrate 1 to a main substrate such as a motherboard in a known connection form such as a ball grid array (BGA) or a pin grid array (PGA). ing. Solder resist layers 8 and 18 (SR1, SR11) made of a photosensitive resin composition are formed on the front surface wiring conductor layer M3 and the back surface wiring conductor layer M13, respectively. In order to expose the solder lands 10, the solder resist layer 8 on the surface side is formed with openings 8 a corresponding to the solder lands 10 in a one-to-one manner, and is connected to the solder lands 10 inside thereof. Solder bumps 11 are arranged.

  On the other hand, in addition to the solder lands 10, metal pads 10 ′ such as logo marks, alignment marks, or direction confirmation marks (that is, alignment marks) are formed on the surface wiring conductor layer M <b> 3. The metal pad 10 ′ is a pad-on via in which a hollow via 34 ′ formed in the buildup layer V <b> 2 (dielectric layer) immediately below is open to the pad main surface. The metal pad 10 ′ configured as a pad-on-via is integrated with a via conductor 34 s that fills the inner surface of the via hole 34 h and does not fill the interior. An opening formed in the solder resist layer 8 corresponding to the pad-on via is a first type opening 8a '. In the present embodiment, the metal pads 10 and 10 ′ are both formed as SMD (Surface-Mounted Device) pads, and the second type opening 8a and the first type opening 8a ′ are both. It has an inner diameter smaller than the outer diameter of the metal pads 10, 10 ', and is arranged so that the inner peripheral edge of the opening of the solder resist layer 8 overlaps the outer peripheral edge of the metal pads 10, 10'.

  Here, the solder resist layers 8 and 18 can be manufactured as follows. That is, a photosensitive resin film formed from a photosensitive resin composition varnish is laminated (bonded), and an exposure mask (for example, a glass mask) having a pattern corresponding to the opening 8a (in the case of a solder resist layer) is overlaid. To expose. When a positive photosensitive resin is used, curing of the resin is suppressed in the exposed portion corresponding to the opening 8a, while the unexposed background portion remains without being suppressed. Therefore, if the exposed portion where curing is suppressed is dissolved in a solvent and removed by etching, the opening 8a can be easily formed with a desired pattern (so-called photovia process). The via layers V1, V11, V2, and V12 are formed by a photo via process or laser beam drilling.

  When forming a solder resist layer using a positive photosensitive resin, as shown in FIG. 14, when an exposure mask 62 is superimposed on an uncured photosensitive resin film 8 ′ and exposed, the photosensitive resin film 8 ′. In this case, the portion immediately below the opening mask pattern 62a, which is a translucent portion, is exposed to light, and curing is suppressed. Therefore, after the unexposed portion 8'c is cured at room temperature or at an appropriately elevated curing temperature, the exposed portion 8'a is etched with a solvent or the like, so that the solder resist layer 8 having the openings 8a is formed. can get.

Hereinafter, the operation of the CAD / CAM system 100 will be described in detail.
When the application program 162 of FIG. 2 is activated, a drawing screen 40 is displayed on the monitor 113 (FIG. 2) as shown in FIG. The application program 162 according to the present embodiment is constructed as draw graphic software as in the known CAD system, and is operated on the drawing screen 40 by operating the mouse 107 (hereinafter referred to as the element of the electronic circuit board 1). The drawing operation is advanced while individually inputting the graphic of FIG. In this embodiment, when the drawing screen 40 for a new drawing is launched, the drawing screen 40 corresponds to the main surface outline of the board to be designed / drawn based on the display data separately stored in the HDD 110 or the like. A quadrilateral reference region 51 and a graphic of a substrate element (in this embodiment, pads 53 and 55) that are normally formed on the substrate surface are displayed as default element graphics. In this case, a default element data storage unit for storing the default element data in association with the product number is provided in the HDD 110, for example, and the product number is input by the keyboard 106 (or a soft button click on the screen by the mouse 107). If the default element data to be read is read out and displayed on the drawing screen, it is convenient because a figure such as the wiring portion 54 can be drawn and input immediately on a standardly formed board element.

  Here, the substrate to be designed is a package substrate or the like in which a plurality of wiring layers are stacked via an insulating layer. Then, a plurality of drawing layers corresponding to the wiring layer to be formed are set on the drawing screen 40. These drawing layers (hereinafter also simply referred to as layers) cannot be visually discriminated because they overlap in FIG. In addition, the figure written in each layer is overlaid on the drawing screen 40, but other figures can be displayed by displaying only the figure on a specific layer or changing the color, brightness, shading, fill pattern, etc. The display state can be different from the figure on the layer.

  FIG. 16 is a flowchart showing the flow of the drawing process. First, in S1, a layer to which an element is to be written is selected. This layer selection can be performed, for example, by clicking a soft button (not shown) for layer selection displayed on the screen with the mouse 107 (FIG. 2). The graphic elements that can be input are the above-described elements and via graphic elements for connecting elements between different layers. In S2 and S8, which one is selected is determined by command input. This command input can also be performed by a mouse click of a soft button (not shown) for selecting element input or via input.

  If element input is selected, the process proceeds from S2 to S3, and element drawing is performed. When drawing an element, a drawing tool is prepared for each type of element to be drawn, such as wiring drawing, pad, land, or surface conductor pattern drawing, as in known CAD system software. A drawing tool can also be selected by a mouse click of a drawing tool selection button (not shown) formed as a soft button on the screen. Then, when a desired drawing tool is selected, as shown in FIG. 4, a mouse click or drag (move the mouse while holding down the mouse button) while moving the pointer P indicating the drawing position by operating the mouse. Draw elements while combining operations. FIG. 4 shows a state in which the figure of the wiring portion 54 that connects the pads 53 and 55 has been drawn as an element.

  As shown in FIG. 6, every time one element is drawn, the element description data, which is graphic data, is associated with the element specifying data (for example, element code) and the layer specifying data (for example, layer number), It is stored in the drawing data memory 152g of FIG. For example, as shown in FIG. 5, the element description data defines the shape, size, and drawing position of the elements OB11, OB12, OB13, OB14, etc. on a coordinate plane set on the screen 40 (FIG. 4). Vector data, function data, or coordinates of specific reference points, and dimension defining data such as radius and length. For example, the element OB11 is described as surface data defining a surface area inside the outline by specifying the outer diameter contour (outline), and has a predetermined orientation (for example, the reference point A11 (x0, y0)) The outline of the element is drawn by connecting the vectors in the order of A11 (x1, y1), A11 (x2, y2), A11 (x3, y3), and A11 (x0, y0) while rotating clockwise. In this case, it is represented as a data set of coordinates of the end point position of each vector. The same applies to the element OB12. A circular element OB13 representing a pad, land, or the like is represented as a data set of its center coordinates C13 and radius r13. Further, for example, an element OB14 which is a figure of the wiring portion having a constant width W can be expressed as a data set of the coordinates of the starting position B14 (x0, y0) and the end position B14 (x1, y1) and the line width W14. it can. In FIG. 5, the four elements OB11, OB12, OB13, and OB14 are all drawn on the same layer (M1).

  On the other hand, when the via input is selected in FIG. 16, the process proceeds to S9 and the via input process is performed. As shown in FIG. 7, the via 34 connects the wiring portions M1 and M2 of different wiring layers. In this embodiment, the graphic of the via 34 is input in units of via layers. Vias that span the via layer are input in the form of stacked vias in which a plurality of vias are stacked. Therefore, by designating a via layer to which a via is to be input, one unit via can be input. When three or more via layers are provided and a via that spans three or more via layers is input, an intermediate layer via is automatically generated by specifying a via start layer and a via end layer. It may be. The via graphic data (which is also one of the board elements) includes, as shown in FIG. 8, via position data and layer specific information (via formation layer VLY ##) corresponding to the via layer. Are stored in the drawing data memory 152g in association with via specifying data (for example, via code).

  Returning to FIG. 16, when the element is drawn, the process proceeds to S4, and as shown in FIG. 9, the input element that partially overlaps (that is, is connected) with the input element OB12 in the same layer. It is determined whether or not OB11 exists. If No, the process further proceeds to S5, and as shown in FIG. 11, it is determined whether or not the element OB12 is not connected to another element OB31 by inter-layer connection through the via VA11. If this is also No, the process proceeds to S6, where the element OB12 is set as a wiring net figure, for example, only the element specifying information is stored in the wiring net data registration memory 152i (FIG. 3) in the drawing data memory 152g. Number) and write it as new net data and register it.

  Also, in the case of Yes in S4 (see FIG. 9) or S5 (see FIG. 11) in FIG. 16, the process proceeds to S7, in which the element is incorporated into the registered wiring net figure to which the element to be connected belongs, ie, a new The process of adding the element specifying data of the element drawn in (5) to the corresponding net data in the wiring net data registration memory 152i is performed (S4 → S7). In the case of connection by via, the via specifying data is also added to the net specifying information (S5 → S7). Thus, as shown in FIG. 3, in the wiring net data registration memory 152i, each net specifying information net1, net2,... And element specifying data OB11, OB12,. Net data in which the data VA11, VA12,... Are associated with each other is stored.

  On the other hand, as shown in FIG. 10, when elements overlapping between different layers occur, the element specifying data is not added to the net data of the overlapping destination. However, in S10 of FIG. 16, if a wiring net figure connected to each other by a newly input via graphic is generated, the process proceeds to S11, and the net data of those wiring net figures are merged. Is re-registered as net data of one wiring net figure. In this case, the net specific information may be left as one corresponding to one of the wiring net figures before integration, and the other may be deleted and treated as a missing number. You may make it provide net specific information.

  When the drawing operation is to be ended after repeating the drawing input of the elements and vias as described above, the process proceeds from S12 to S13, and the graphic data stored in the drawing data memory 152g, that is, the drawing data, A file name is given together with the net data in the wiring net data registration memory 152i, and it is written and saved in the drawing data file 163 of the HDD 110 (FIG. 2).

  Next, as shown in FIG. 12, correction layers LX1, LX2,... Are set in correspondence with the drawing layers LY1, LY2, and stored in the form of a correction area reference table 72, respectively. In each correction layer, correction area specifying data for specifying an area outline is input. The correction area describes the correction area as surface data on the correction layer LX1, and is provided with a correction area ID (B11, B12,...) And area type specifying data (J11, J12,...). Yes. As shown in FIG. 13, to each element (including via) on the drawing layer, which correction area of the corresponding correction layer belongs is associated on the data via, for example, a correction area ID. . As shown in FIG. 15, the content of the correction information for converting the CAD data of each element into CAM data is determined for each type of correction area.

  The CAD data of each element (drawing target element) created as described above is converted into CAM data. The CAM data is a dimension of a manufacturing target element including an element or an additional element (for example, a solder bump formed on a solder land constituting the element) formed on the electronic circuit board 1 in a form associated with the element. Manufacturing of jigs (eg, masks for exposing via patterns and wiring patterns, solder paste coating masks used for forming solder bumps, etc.) for manufacturing the elements to be manufactured, shapes and arrangement positions This is graphic data for specifying the size, shape, and arrangement position of the part corresponding to the target element.

  FIG. 17 is a flowchart illustrating an example of processing for converting CAD data into CAM data. In S51, the CAM data of the paste application mask, specifically, the data describing the size and arrangement position of the opening for filling the solder paste formed in the paste application mask is created. The graphic data of the solder bump itself is not created in the above drawing process, and therefore there is no layer to which the solder bump belongs or CAD data that directly describes the solder bump. Therefore, the data of the element associated with the solder bump, that is, the CAD data of the solder land created on the surface-side wiring conductor layer M3 layer, or the CAD of the solder opening 8a created on the solder resist layer 8 layer. Using the data, CAM data of the opening for filling the solder paste is created.

  After S52, conversion processing for each layer of the CAD data file is performed. In the process of FIG. 17, the element CAD data of each layer of FIG. 1 is automatically and sequentially converted to CAM data. However, only the CAD data of the necessary elements is selected for each process, and the CAM data is selected. You may make it convert. Hereinafter, each step will be described. First, in S52, the first layer is selected. If the layer is a solder resist layer (S53; Yes), the process proceeds to S59 to create CAM data for the solder resist layer. Specifically, graphic data representing the design size (or shape) and formation position of the opening for solder filling (FIG. 1: reference numeral 8a) and the pattern of the opening are transferred to the photosensitive resin composition film. Therefore, the data is converted into graphic data representing dimensions (or shapes) and formation positions of corresponding portions on the exposure mask (a light-shielding portion in the case of a negative composition, and an exposure portion in the case of a positive composition).

  If the selected layer is a conductor layer (S54; Yes), the process proceeds to S58 to create CAM data for the conductor layer. Specifically, graphic data representing the design dimensions (or shape) and formation position of the wiring portion, pad, land, or surface conductor pattern is patterned by matching the plating resist layer with the wiring portion or surface conductor pattern. Therefore, figure data representing dimensions (or shapes) and formation positions of corresponding portions on an exposure mask for photolithography (a light shielding portion when using a negative photoresist, an exposure portion when using a positive photoresist) Convert. Further, if the selected layer is a via layer (S55; Yes), the process proceeds to S56, and CAM data for the via layer is created. Specifically, the graphic data representing the design dimension (or shape) and formation position of the via to be formed, the corresponding part on the exposure mask for photolithography (the build-up layer, the negative photosensitive resin composition film) Is converted to graphic data representing the size (or shape) and formation position of the light-shielding portion on the mask when formed using, and the exposed portion on the mask when formed using a positive photosensitive resin composition film. . Note that via drilling can be performed by laser beam drilling instead of the photo via process. In this case, the laser beam is based on the design dimensions (or shape) of the via to be formed and the graphic data representing the formation position. What is necessary is just to convert into laser beam specific information, such as intensity | strength, a beam diameter, or a focus depth, and the CAM data containing the irradiation position information of a laser beam.

  If the layer is not any of the above, the layer is skipped as a layer in which CAD data does not exist. The above processing is executed while changing layers one after another in the flow of S60, S61 → S53, and the processing ends when the CAM data conversion processing is completed for all layers. Note that the conversion table used when converting the CAD data of each element into the CAM data is the one stored in the correction data file 165 of FIG.

  FIG. 18 is a flowchart showing details of the alignment mark CAM data creation processing. This is executed in the solder resist layer CAM data creation process (S59) of the CAM data creation process of FIG. The CAM data in this case is an opening mask pattern of an exposure mask. In this embodiment, the CAM data is created by converting an alignment mark formed on the solder resist layer 8 as CAD data from the CAD data.

  First, the presence or absence of library data is checked. If there is no library data (S101; No), the process is terminated. If there is library data (S101; Yes), the library data is read (S102), and it is checked whether the library data is an alignment mark. If it is not an alignment mark (S103; No), the process returns to S101 to check for the presence of the next library data.

  If the read library data is an alignment mark (S103; Yes), a coordinate value on the side for correcting each side of the figure is obtained. For example, when the alignment mark is a triangle indicated by a broken line in FIG. 20A, first, in order to obtain a correction value for the side AB, the coordinate value of the point X on the side AB is set (S104). The point X is a coordinate value when, for example, the side AB is equally divided into ten, and the coordinate value of the first point is the coordinate value of the vertex A. There are no particular restrictions on the method and number of points X selected on the side AB.

  For point X, the length from the starting point (vertex A in FIG. 20A) is obtained, and the ratio of the obtained length to the side (side AB in FIG. 20A) is calculated (S105). A correction coefficient is obtained based on this ratio. A correction coefficient (conversion coefficient) γ for converting the alignment mark shape into an opening mask pattern is stored in the correction data file 165 in the form of the correction table 75 shown in FIG. ing. As shown in FIGS. 22B to 22D, the correction table 75 has a correction curve corresponding to the shape of the figure, that is, the form of the vertices at both ends of each side. The selection is made according to the shape. In this case, a correction table having the correction curve shown in FIG. 22B is selected (S106).

A correction value ζ is calculated from the correction coefficient γ calculated from the selected correction table (S107). The correction value ζ is, for example,
ζ = γ × (length of line segment AX / length of side AB) + c
It can be expressed as Note that c is a constant. In this correction, the correction values at both ends (vertices) of the line segment (side AB) are minimized, and the correction is increased as the distance from the vertex increases. The point where the correction value becomes maximum differs depending on the shape of the triangle.

  When the correction value ζ is calculated, it is offset inward (opening side) by the correction value ζ. That is, taking point X in FIG. 20A as an example, the point moves to the inside of the triangle ABC in a direction perpendicular to the side AB, and the moved point is stored (S108).

  Thereafter, the coordinate value of the next point is set to the point X (S109). When the set coordinate value is not the end point (vertex B) (S110; No), the process returns to S104 and the correction value calculation process is performed (S105 to S109). When the set coordinate value is the end point (vertex B) (S110; Yes), curve approximation by a known least square method or the like is performed based on the coordinate value after movement for each point on the side AB obtained in S108, The obtained coordinate value data of the curve AB is stored as CAM data (S111). Thereafter, correction for the next side (ie, side BC) is performed (S112; No). When correction processing has been performed for all sides (S112; Yes), the process returns to S101 to check for the presence of the next library data.

  When creating a cross-shaped alignment mark as shown by the broken line in FIG. 21A, the vertices B, E, H, and K that are convex toward the opening are exposed to the etching solution. Is longer than other vertices or line segments. Therefore, it is necessary to take a larger etching allowance than other portions of the cross shape. Therefore, the line segment (side) including the vertices B, E, H, and K needs to be corrected differently from the case of the triangle as shown in FIG. That is, the sides CD, FG, IJ, LA use the correction table having the correction curve shown in FIG. 22B, and the sides AB, DE, GH, JK use the correction table having the correction curve shown in FIG. The sides BC, EF, HI, and KL are corrected using the correction table having the correction curve shown in FIG.

Selection of these correction tables is performed in S106 of the flowchart of FIG. The shapes of the angles of the vertices at both ends of the sides of the polygon are classified into the following three types.
(1) The angles of the vertices at both ends are smaller than 180 degrees.
(2) The angle of the vertex at the start point is smaller than 180 degrees, and the angle of the vertex at the end point is larger than 180 degrees.
(3) The angle of the vertex at the start point is larger than 180 degrees, and the angle of the vertex at the end point is smaller than 180 degrees.
The correction curve corresponding to the above (1) is FIG. 22B, the correction curve corresponding to the above (2) is FIG. 22C, and the correction curve corresponding to the above (3) is FIG. 22D. In S105, the shape of the angle of the vertexes at both ends of each side is checked, and a correction table having a correction curve corresponding to the shape is selected.

  Further, when the state (2) and the state (3) are continuous, a correction blank area is generated as shown by the hatched portion in FIG. In this case, when the correction table (2) (FIG. 22C) is used and the correction point is the end point (vertex B) of the line segment (side AB) (FIG. 18; S111), the end point ( Draw an arc whose center is vertex B) and whose radius is the correction value ζ of the end point (vertex B) to the position where it passes through the end point (vertex B) and intersects with the line perpendicular to the next line segment (side BC). Etching allowance.

  The CAM data created as described above is output from the input / output interface 102 of FIG. 2 as necessary, and is used for manufacturing the electronic circuit board 1. For example, the inner diameter of the opening of the paste application mask is output to a mask making apparatus (for example, a laser drilling apparatus) when the paste application mask is made. On the processing apparatus side, in accordance with the data of the inner diameter and the forming position of the opening indicated by the CAM data, the opening is sequentially drilled in a material such as a metal plate to create a paste coating mask. In addition, the outer diameter of the opening mask pattern of the photolithography exposure mask of the solder resist layer is output to a device for producing the exposure mask (for example, a photoengraving device). On the apparatus side, an exposure mask is created in accordance with the data of the opening mask pattern outer diameter and the formation position indicated by the CAM data.

  In the example of FIG. 20A, an exposure mask as shown by a solid line diagram is created, and an alignment mark forming a triangle ABC as shown by a solid line part in FIG. 20B is formed by etching the exposure mask performed in a photolithography process. It is formed. In the example of FIG. 21A, an exposure mask having a shape as shown by a solid line diagram is prepared, and a cross shape as shown by a solid line part in FIG. 21B is obtained by etching the exposure mask performed in a photolithography process. An alignment mark having a desired shape is formed.

  Although the embodiments of the present invention have been described above, these are merely examples, and the present invention is not limited to these embodiments, and the knowledge of those skilled in the art can be used without departing from the spirit of the claims. Various modifications based on this are possible.

Sectional drawing which shows an example of an electronic circuit board. The block diagram which shows the electrical constitution of the CAD / CAM system for electronic circuit boards of this invention. A map showing the contents of the wiring net data registration memory. Explanatory drawing of the operation process on the drawing screen in the CAD / CAM system for electronic circuit boards of this invention. Conceptual diagram of the element. The conceptual diagram of the CAD data of an element. Conceptual diagram of via shape. The conceptual diagram of CAD data of a via figure. The 1st explanatory view of the overlapping connection state of an element. The 2nd explanatory view of the overlapping connection state of an element. Explanatory drawing of the via connection state of an element. The conceptual diagram which shows an example of a correction area reference table. The conceptual diagram which shows an example of a correction area / element correspondence table. The figure which shows typically an example of the opening formation process of a soldering resist layer. The schematic diagram which shows an example of the correction table for correction coefficients classified by area. The flowchart which shows the flow of a drawing process. The flowchart which shows the flow of a CAM data creation process. The flowchart which shows the flow of an alignment mark correction process. The figure which shows the state when not performing the alignment mark correction | amendment in a triangle. The figure which shows the state at the time of performing the alignment mark correction | amendment in a triangle. The figure which shows the state at the time of performing alignment mark correction | amendment in a cross. The figure which shows an example of the correction table of an alignment mark.

Explanation of symbols

101 CAD / CAM system for electronic circuit board 102 Input / output interface (CAM data output means)
103 CPU (plotting layer setting means, CAD data input means, CAM data conversion means, CAM data output means)
105 RAM
106 Keyboard (CAD data input means)
107 Mouse (CAD data input means)
108 CD-ROM drive 110 Hard disk drive (correction table storage means)
112 Computer body 120 CD-ROM (recording medium on which a computer program is recorded)

Claims (3)

In an electronic circuit board in which conductor layers and dielectric layers are alternately laminated, an opening of a solder resist layer formed on the main surface of the electronic circuit board is created as CAD data,
In order to form the opening of the solder resist layer by a photolithography process using a photosensitive resin, the opening of the solder resist layer reflected in the CAD data is used as an opening mask pattern of an exposure mask for photolithography. While converting as data,
The opening shape of the recognition mark of the substrate formed in the plane of the solder resist layer has two line segments intersecting the concave shape on the opening side, and the intersection of these line segments is used as a correction reference point. A method of creating CAM data for an electronic circuit board, wherein the mask pattern of the recognition mark in the opening mask pattern is corrected so that the etching allowance for the line segment becomes wider as the distance from the correction reference point is increased. A CAD / CAM system for designing and manufacturing an electronic circuit board in which conductor layers and dielectric layers are alternately laminated,
A drawing layer setting means for setting a plurality of drawing layers corresponding to the conductor layer and the dielectric layer to be formed on the electronic circuit board;
Among the board elements constituting the electronic circuit board, those predetermined as drawing objects are used as drawing object elements, and CAD data for specifying the design dimensions, shapes, and arrangement positions of the drawing object elements, CAD data input means for inputting on the drawing layer;
An additional element formed on the electronic circuit board in a form associated with the drawing target element or the drawing target element as a manufacturing target element, the manufacturing target element itself or a corresponding part of a manufacturing jig of the manufacturing target element, CAM data conversion means for creating CAM data that specifies dimensions, shapes, and arrangement positions in the manufacturing process by conversion from the CAD data;
CAM data output means for outputting the CAM data,
The manufacturing target element is an opening of a solder resist layer formed on the main surface of the electronic circuit board, and the CAD data input means inputs and creates the opening of the solder resist layer as the CAD data.
The CAM data conversion means forms the opening of the solder resist layer by a photolithography process using a photosensitive resin, and opens the opening of the solder resist layer reflected in the CAD data by using an exposure mask for photolithography. Two lines that are converted into CAM data into an opening mask pattern and the opening shape of the recognition mark of the substrate formed in the surface of the solder resist layer intersects the concave shape on the opening side. And a mask pattern of the recognition mark in the mask pattern for opening so that the etching allowance for the line segment becomes wider as the distance from the correction reference point is increased. A CAD / CAM system for an electronic circuit board characterized by correcting the above. The design information of the electronic circuit board is obtained by inputting a drawing target element necessary for the electronic circuit board to be obtained as the CAD data on the drawing layer using the CAD / CAM system for an electronic circuit board according to claim 2. An electronic circuit board design process for creating the CAD data as a set of CAD data;
An electronic circuit board manufacturing step of manufacturing the electronic circuit board using the output content of the CAM data output means of the CAM data created by the CAM data creation means based on the CAD data,
In the electronic circuit board manufacturing process, the exposure mask having an opening mask pattern specified by the CAM data is created based on the CAM data created by the CAM data creation means, and the electronic mask is used using the exposure mask. A method of manufacturing an electronic circuit board, comprising performing a photolithography step of forming a solder resist layer having the opening to be obtained on a circuit board.

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