JP2005236307A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance reliability in the connection of an electrode, and to protect the surface of an integrated circuit. <P>SOLUTION: A semiconductor integrated circuit board 100 with a main surface having a semiconductor integrated circuit and a pedestal 104a comprising insulator, such as polyimide resin formed on the main surface of the board 100 are formed on the main surface of the board 100, are connected to the semiconductor integrated circuit, face a conductor 105 having an extended portion extended on the upper surface of the pedestal 104a and the main surface of the board 100, and a connecting substrate 300 that is connected to the extended portion of the conductor 105 on the upper surface of the pedestal 104a is provided. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to an electrode structure on a semiconductor integrated circuit and a mounting structure of the semiconductor integrated circuit substrate on a connection substrate.

  Conventionally, as a structure for mounting a semiconductor integrated circuit board on a connection board, a tape carrier package, a chip on board, a chip on glass, etc. There was a structure. In the above mounting structure, usually, a sealing resin is filled between the semiconductor integrated circuit substrate and the connection substrate. Further, the electrode structure and the electrode connection structure of the semiconductor integrated circuit substrate in the mounting structure described above include a bump connection structure using bump electrodes. Metal bump electrodes such as gold (Au) bump electrodes and solder bump electrodes made of an alloy of lead (Pb) and tin (Sn) (hereinafter referred to as Pb-Sn) are mainly used as the bump electrodes. It was.

  The conventional metal bump electrode is susceptible to plastic deformation, and in the case of an alloy such as Pb-Sn, it is liable to be broken from the crystal interface, so the difference in thermal expansion coefficient between the semiconductor integrated circuit substrate and the connection substrate, Alternatively, thermal fatigue is likely to occur due to thermal stress caused by the difference in thermal expansion coefficient between the sealing resin and the bump electrode itself, which may cause electrode destruction. In addition, in the process of plating the bump electrode material on the semiconductor integrated circuit and the process of etching the plated metal, the semiconductor integrated circuit trimming circuit and the like are adversely affected on the portion not covered with the surface protective film. There was a case. Thus, the connection reliability of the conventional electrode structure (bump electrode) is not satisfactory, and the conventional electrode forming process cannot sufficiently protect the surface of the semiconductor integrated circuit.

  The present invention solves such a conventional problem, and an object of the present invention is to provide a semiconductor device having high electrode connection reliability. It is another object of the present invention to provide a semiconductor device capable of protecting the surface of a semiconductor integrated circuit after the electrode forming step.

In order to achieve the above object, the semiconductor device of the present invention provides:
A semiconductor substrate having a main surface with a semiconductor integrated circuit;
A base made of a resin formed on the main surface of the semiconductor substrate and having a first surface facing the main surface of the semiconductor substrate and a second surface facing the first surface;
A first portion disposed on the main surface of the semiconductor substrate and connected to the semiconductor integrated circuit; a central portion extending from the first portion; and the second portion of the pedestal extending from the central portion. A conductive layer having a second portion disposed on the surface of
And a connection substrate disposed facing the main surface of the semiconductor substrate and connected to the second portion of the conductive layer.

Another semiconductor device of the present invention is
A semiconductor substrate having a main surface with a semiconductor integrated circuit;
A base made of resin formed on the main surface of the semiconductor substrate;
A conductive layer formed on the main surface of the semiconductor substrate, connected to the semiconductor integrated circuit and having an extending portion extending on the upper surface of the pedestal;
A connection substrate facing the main surface of the semiconductor substrate and connected to the extended portion of the conductive layer on the upper surface of the pedestal.

  As described above, according to the semiconductor device of the present invention, the base made of resin is provided, the conductive layer connected to the semiconductor integrated circuit is provided on the base, and the connection substrate is connected to the conductive layer on the base. In addition to protecting the surface of the semiconductor integrated circuit, plastic deformation of the pedestal due to thermal stress is less likely to occur, and electrode breakdown due to thermal fatigue can be prevented, so that the electrode connection reliability can be improved. effective.

First Embodiment FIGS. 1A and 1B are diagrams showing an electrode structure in a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a top view, and FIG. 1B is a cross section taken along line AA 'in FIG. FIG. In FIG. 1, a semiconductor integrated circuit having a wiring 101, a surface protective film 102, and a wiring lead-out portion 103 is formed on a semiconductor integrated circuit substrate 100. The wiring 101 is usually made of aluminum (Al) or an alloy in which silicon (Si) or copper (Cu) is added to Al. The surface protective film 102 is a protective film that covers the surface of the semiconductor integrated circuit, and is usually made of a silicon oxide film (SiO ₂ film), a silicon nitride film (Si _x N _y film), or the like. The wiring lead-out part 103 is an opening formed in the surface protective film 102 to expose the wiring 101. The wiring lead-out part 103 may be formed in a pad forming part of the wiring 101 (a part wider than the lead-out part) like a bonding pad, or in the lead-out part of the wiring 101 like a via hole. May be.

  On the semiconductor integrated circuit, electrodes having pedestal portions 104a and 104b having different heights, a conductor 105, and an opening 106 are formed. Both pedestals 104a and 104b are made of an insulator. Here, a polyimide resin is used as the material of the insulator. The top surface 104b-a of the pedestal part 104b is formed to be lower by ΔT than the top surface 104a-a of the pedestal part 104a. The upper surface shape of the pedestal portion 104a is not limited to a quadrangle as shown in FIG.

  The opening 106 is provided in an insulator that becomes the pedestals 104 a and 104 b in order to expose the wiring 101. Therefore, the opening 106 is formed in a region including the wiring lead-out portion 103. In FIG. 1, the opening 106 is formed so as to surround the pedestal 104 a, and the pedestals 104 a and 104 b are separated by the opening 106. However, the opening 106 may be anything that exposes the wiring 101 and is not limited to a shape surrounding the pedestal 104a. Further, the pedestal portions 104a and 104b only need to have different heights, and need not be separated.

  The conductor 105 is formed on the opening 106 including the surface of the wiring 101 and the insulator so as to reach the top surface 104a-a of the pedestal 104a from the surface of the wiring 101. That is, the conductor 105 leads the wiring 101 to the top surface 104a-a of the pedestal portion 104a. In FIG. 1, the conductor 105 has a structure that completely covers the surface of the pedestal portion 104a, but there may be a portion where the conductor 105 is not formed on the side surface of the pedestal portion 104a. The conductor 105 has a single layer structure or a laminated structure made of a metal layer or an alloy layer. The metal material or alloy material is selected in consideration of the connection process with the connection substrate. As the conductor 105, for example, a single layer configuration including an Au layer, a Cu layer, or a Pb—Sn layer, or a two-layer structure of an Au layer and a nickel (Ni) layer (hereinafter referred to as a Ni / Au layer), or There are a two-layer structure of an Au layer and an alloy layer of titanium (Ti) and tungsten (W) (hereinafter referred to as a Ti—W / Au layer).

  The higher pedestal part 104a, the conductor 105, and the opening part 106 constitute an electrode part 107 for connection to the connection substrate. In addition, the lower pedestal portion 104 b constitutes a surface protection portion 108 that protects the surface of the semiconductor integrated circuit circuit 100. The higher pedestal portion 104a may be the highest pedestal portion, and the lower pedestal portion 104b may be composed of a plurality of pedestal portions having different heights. That is, a plurality of pedestal portions having three or more heights may be formed including the highest pedestal portion on which the conductor is formed.

  FIG. 2 is a sectional structural view showing an electrode forming process of the semiconductor device of the first embodiment shown in FIG. First, as shown in FIG. 2A, an insulating layer 204 to be pedestals 104a and 104b is formed on the semiconductor integrated circuit substrate 100 on which the wiring 101, the surface protective film 102, and the wiring lead-out portion 103 are formed. A step of forming an opening 106 for exposing the wiring 101 in the insulating layer 204 is performed. Thereby, the base part 104a is formed. Here, a curable insulating resin is used as the insulating layer 204, and the above-described insulating resin is applied onto the semiconductor integrated circuit substrate 100, the openings 106 are formed in the insulating resin, and the insulating resin is cured. . Here, a polyimide resin is used as the curable insulating resin. That is, a polyimide resin is applied to a wafer, which is the semiconductor integrated circuit substrate 100, by spin coating to form the opening 106, and then the wafer is baked at about 350 [° C.] to cure the polyimide resin. Let

  Next, as illustrated in FIGS. 2B and 2C, a conductive film 205 to be a conductor 105 is formed over the insulating layer 204 in which the opening 106 is formed, and the insulating layer 204 is formed from the surface of the wiring 101 in the opening 106. The step of patterning the conductive film 205 is carried out leaving the portion reaching the predetermined surface region (the top surface 104a-a of the pedestal portion 104a). Thereby, the conductor 105 is formed. Here, a Cu film is used as the conductive film 205, a Cu film is formed on the insulating layer 204 by sputtering or the like, a photoresist 207 is patterned on the Cu film, and an acid or the like is used using the photoresist 207 as an etching mask. The conductive film 205 is patterned by the wet etching method used.

  Finally, as shown in FIG. 2D, the portion of the insulating layer 204 where the conductor 105 is not formed (the portion that becomes the pedestal portion 104b) is more than the portion where the conductive film 105 is formed (the pedestal portion 104a). A step of cutting the surface of the portion of the insulating layer 204 where the conductor 105 is not formed by a predetermined thickness is performed so as to be lowered. Thereby, the base part 104b whose top surface 104b-a is lower than the top surface 104a-a of the base part 104a is formed. Through the above steps, the electrode shown in FIG. 1 is formed on the semiconductor integrated circuit substrate 100. Thereafter, the semiconductor integrated circuit board 100 is mounted on the connection board. In the electrode shown in FIG. 1, the conductor 105 formed on the top surface 104 a-a of the base portion 104 a of the electrode portion 107 is connected to the connection substrate. The pedestal part 104b (surface protection part 108 in FIG. 1) does not contact the connection substrate, and a sealing resin is filled between the pedestal part 104b and the connection substrate, for example.

  FIG. 3 is a cross-sectional view showing the structure around the connection portion between the electrode and the connection substrate in the semiconductor device of the first embodiment. (1) Bonds the electrode portion 107 to the lead 301 of the connection substrate such as a tape carrier. (2) shows the case where the electrode part 107 is bonded to the wiring 302 of the connection substrate 300. In FIG. 3A, the conductor 105 of the connection portion is bonded to the lead 301 of the connection substrate by, for example, a thermocompression bonding method. In FIG. 3B, the conductor 105 of the connection portion is bonded to the wiring 302 of the connection substrate 300 by, for example, the reflow method.

  As described above, according to the first embodiment, the entire surface of the semiconductor integrated circuit is covered with the pedestals 104a and 104b made of an insulator, so that the surface of the semiconductor integrated circuit (especially when the electrodes are formed or the electrodes are bonded) The portion where the surface protective film 102 is not formed) can be protected. Further, by forming the top surface 104a-a of the pedestal portion 104a on which the conductor 105 is formed higher than the top surface 104b-a of the pedestal portion 104b by ΔT, the conductor 105 on the pedestal portion 104a can be easily formed on the connection board. Can be bonded. In addition, by forming the electrode portion 107 by a pedestal portion 104a made of an insulator such as a polyimide resin having a higher elastic limit than a metal and having a polymer structure instead of a crystal structure, it is possible to cope with stress and thermal stress during bonding. Thus, the electrode portion 107 remains elastically deformed without being plastically deformed, and electrode destruction due to thermal fatigue can be prevented, so that the electrode connection reliability can be improved. Further, the conductor 105 on the pedestal portion 104a and the wiring 101 are spatially separated by the height of the pedestal portion 104, and metal diffusion at the connection surface between the conductor 105 and the wiring 101 is caused even when the thermocompression bonding method is used. Since electrode deterioration does not occur, the diffusion preventing metal layer necessary for the conventional metal bump electrode becomes unnecessary. Further, since the pedestal part 104a may be formed not only on the wiring lead-out part 103 but also on the surface protective film 102, the upper surface shape and size of the electrode connection part (the top surface 104a of the pedestal 104). -A) can be freely set regardless of the shape and size of the upper surface of the wiring lead-out portion 103.

Second Embodiment FIGS. 4A and 4B are diagrams showing an electrode structure in a semiconductor device according to a second embodiment of the present invention, where FIG. 4A is a top view and FIG. 4B is a cross section taken along line AA 'in FIG. FIG. In FIG. 4, the same components as those in FIG. The electrode structure of the second embodiment shown in FIG. 4 is the same as the electrode structure of the first embodiment shown in FIG. 1 except that the pedestal parts 104a and 104b having different heights are pedestal parts 404a and 404b having different heights. The conductor 105 is a conductor 405 and the opening 106 is an opening 406. The material of the pedestal portions 404a and 404b is the same as that of the pedestal portions 104a and 104b, and here is polyimide resin. The material of the conductor 405 is the same as that of the conductor 105. Similarly to the first embodiment, the top surface 404b-a of the pedestal portion 404b is formed to be lower by ΔT than the top surface 404a-a of the pedestal portion 404a.

  In the electrode structure of the second embodiment shown in FIG. 4, the higher pedestal portion 404a and the lower pedestal portion 404b are integrally formed without being separated by the opening, and this integrally formed pedestal portion 404a. The surface of the pedestal 404b is not completely covered with the conductor 405, and a part thereof is exposed. The conductor 405 is not formed on the top surface 404b-a of the lower pedestal portion 404b, nor is it formed on the side surface 404a-b on the boundary side with the pedestal portion 404b of the higher pedestal portion 404a. . The opening 406 does not surround the pedestal 404a like the opening 106 in FIG. The higher pedestal 404a, the conductor 405, and the opening 406 constitute an electrode portion 407 for connection to the connection substrate. Further, the lower pedestal portion 404 a constitutes a surface protection portion 408 that protects the surface of the semiconductor integrated circuit circuit 100.

  FIG. 5 is a process sectional view showing an electrode forming process of the semiconductor device of the second embodiment shown in FIG. In FIG. 5, the same components as those in FIG. 2 are denoted by the same reference numerals. First, as shown in FIG. 5A, a step of forming an insulating layer 204 to be pedestals 404a and 404b on a semiconductor integrated circuit substrate 100 and forming an opening 406 for exposing the wiring 101 to the insulating layer 204. To implement. For example, as in FIG. 2A, a curable polyimide resin is used as the insulating layer 204, and the polyimide resin is cured after forming the opening 406.

  Next, as illustrated in FIGS. 5B and 5C, a conductive film 205 to be a conductor 405 is formed over the insulating layer 204 in which the opening 406 is formed, and the insulating layer 204 is formed from the surface of the wiring 101 in the opening 406. The step of patterning the conductive film 205 is performed, leaving the portion reaching the predetermined surface region (the region where the pedestal portion 404a is to be formed), and the conductor 405 is formed. For example, as in FIGS. 2B and 2C, a Cu film is used as the conductive film 205, and the conductive film 205 is patterned using the photoresist 207 as an etching mask.

  Finally, as shown in FIG. 5 (4), the portion of the insulating layer 204 where the conductor 405 is not formed (the portion that becomes the pedestal portion 404b) is the portion where the conductor 405 is formed (the portion that becomes the pedestal portion 404a). The surface of the portion of the insulating layer 204 where the conductor 405 is not formed is shaved by a predetermined thickness so that the pedestals 404a and 404b having a single structure are formed. The electrodes shown in FIG. 4 are formed on the semiconductor integrated circuit substrate 100 through the above steps.

  FIG. 6 is a cross-sectional view showing the structure around the connection portion between the electrode and the connection substrate in the semiconductor device of the second embodiment. (1) Bonds the electrode portion 407 to the lead 301 of the connection substrate such as a tape carrier. (2) shows a case where the electrode portion 407 is bonded to the wiring 302 of the connection substrate 300. The conductor 405 on the top surface of the electrode portion 407 is bonded to the lead 301 (FIG. 6 (1)) or the wiring 302 (FIG. 6 (2)) of the connection substrate by a thermocompression bonding method or a reflow method.

  As described above, according to the second embodiment, the surfaces of the integrally formed pedestals 404a and 404b are not completely covered with the conductor 405, and a part thereof is exposed. In this case, it is easy to release strain caused by elastic deformation, and gas generated from the pedestal 404a is easily released due to the thermal history after the electrode forming process, so that the conductor 405 is less likely to be broken. It can be further increased.

  In FIG. 2, even if the surface of the pedestal 404a having the higher conductor is completely covered, the same effect as described above can be obtained as long as the pedestal 404a and the pedestal 404b are integrally formed. Further, even if the higher pedestal 104a and the lower pedestal 104b are separated as shown in FIG. 1, the same effect as described above can be obtained as long as a part of the surface of the pedestal 104a is exposed.

Third Embodiment FIG. 7 is a sectional view showing an electrode structure in a semiconductor device according to a third embodiment of the present invention. In FIG. 7, the same components as those in FIG. 1 or FIG. The electrode structure of the third embodiment shown in FIG. 7 is the same as the electrode structure of the second embodiment shown in FIG. 4 on the semiconductor integrated circuit substrate 100 in which the wiring 101 is formed and the surface protective film 102 is not formed. Further, pedestal portions 404a and 404b having different heights, a conductor 405, and an opening 406 are formed. The electrode structure of the third embodiment is characterized in that the pedestals 404a and 404b, particularly the lower pedestal 404b, is a surface protective film of a semiconductor integrated circuit. The structure around the connection portion between the electrode and the connection substrate in the semiconductor device of the third embodiment is the same as that of the second embodiment shown in FIG.

  FIG. 8 is a process sectional view showing an electrode forming process of the semiconductor device of the third embodiment shown in FIG. In FIG. 8, the same components as those in FIG. 2 or FIG. First, as shown in FIG. 8A, the insulating layer 204 to be the pedestals 404a and 404b is formed on the semiconductor integrated circuit substrate 100 on which the wiring 101 has been formed and the surface protective film is not formed thereon. Then, a step of forming an opening 406 in the insulating layer 204 is performed. For example, as in FIG. 5A, a curable polyimide resin is used as the insulating layer 204, and the polyimide resin is cured after forming the opening 406.

  Next, as shown in FIG. 8B, a conductive film to be a conductor 405 is formed on the insulating layer 204 in which the opening 406 is formed, and a process of patterning the conductive film is performed. Form. For example, as in FIGS. 5 (2) to (4), a Cu film is used as the conductive film, and the conductive film is patterned using a photoresist as an etching mask. Finally, a step of scraping the surface of the portion of the insulating layer 204 where the conductor 405 is not formed by a predetermined thickness is performed to form the pedestals 404a and 404b having a single structure. Through the above steps, the electrode shown in FIG. 7 is formed on the semiconductor integrated circuit substrate 100 on which the surface protective film is not formed.

  As described above, according to the third embodiment, the insulating layer 204 serving as the pedestal 404a of the electrode portion 407 and the pedestal 404b of the surface protection portion 408, particularly the insulating layer 204 serving as the pedestal 404b, serves as the surface protective film of the semiconductor integrated circuit. Therefore, it is not necessary to form a separate surface protective film, so that the manufacturing process of the semiconductor device is simplified and the manufacturing cost can be reduced.

Fourth Embodiment FIG. 9 is a cross-sectional view showing a step of forming an insulating layer and an opening in an electrode formation step of a semiconductor device according to a fourth embodiment of the present invention. In FIG. 9, the same components as those in FIG. 2 or FIG. The electrode structure of the semiconductor device of the fourth embodiment is the same as that of the semiconductor device of the second embodiment. The electrode formation process of the fourth embodiment is substantially the same as the electrode formation process of the second embodiment shown in FIG. However, in the electrode forming step of the fourth embodiment, a photosensitive insulating resin is used as the insulating layer in the step of forming the insulating layer and the opening (the step shown in FIG. 5A). The opening is formed by a lithography technique.

  First, as shown in FIG. 9 (1), a curable photosensitive insulating resin 504 to be the pedestals 404a and 404b is formed on the semiconductor integrated circuit substrate 100, and an opening formation scheduled region of the photosensitive insulating resin 504 is formed. To expose. Here, a photosensitive polyimide resin is used as the photosensitive insulating resin 504. A photosensitive polyimide resin is applied to a wafer which is the semiconductor integrated circuit substrate 100 by a spin coating method, and exposure light 501 including the photosensitive wavelength of the polyimide resin is applied. Irradiate the region where the opening is to be formed.

  Next, as shown in FIG. 9B, the exposed photosensitive insulating resin 504 is immersed in a developing solution and developed to remove the photosensitive portion, thereby forming an opening 406 of the photosensitive insulating resin 504. Next, the photosensitive insulating resin 504 (polyimide resin) is cured by subjecting the wafer to a baking process of about 350 [° C.]. The subsequent steps are the same as the steps shown in (2) to (4) of FIG.

  As described above, according to the fourth embodiment, the photosensitive insulating resin 504 is used as the insulating layer to be the pedestal portions 404a and 404b, and the opening 406 is formed in the photosensitive insulating resin 504 by the lithography technique. As compared with the case of using a simple processing technique, the opening 406 can be formed accurately and finely and efficiently.

  Note that the opening forming step of the fourth embodiment can be applied to the semiconductor device of the first or third embodiment.

Fifth Embodiment FIG. 10 is a cross-sectional view showing a step of forming an insulating layer and an opening in an electrode formation step of a semiconductor device according to a fifth embodiment of the present invention. In FIG. 10, the same components as those in FIG. 2 or FIG. The electrode structure of the semiconductor device of the fifth embodiment is the same as that of the semiconductor device of the second embodiment. The electrode formation process of the fifth embodiment is substantially the same as the electrode formation process of the second embodiment shown in FIG. However, in the electrode forming process of the fifth embodiment, in the process of forming the insulating layer and the opening (the process shown in FIG. 5A), the opening is formed in the insulating resin that is the insulating layer by a laser processing technique. It is characterized by doing.

  First, as shown in FIG. 10A, a curable insulating resin 604 to be the pedestals 404a and 404b is formed on the semiconductor integrated circuit substrate 100, and a laser beam 601 is formed in the opening formation planned region of the insulating resin 604. Then, the insulating resin in the region where the opening is to be formed is baked and removed. Here, a polyimide resin is used as the insulating resin 604.

  Next, as shown in FIG. 10 (2), the insulating resin 604 having the opening 406 formed therein is baked at about 350 [° C.] to cure the insulating resin 604. The subsequent steps are the same as the steps shown in (2) to (4) of FIG.

  As described above, according to the fifth embodiment, the insulating resin 604 is used as the insulating layer to be the pedestals 404a and 404b, and the opening 406 is formed in the insulating resin 604 by the laser processing technique, thereby providing a mechanical processing technique. As compared with the case of using, etc., the opening 406 can be formed accurately and finely and efficiently.

  Note that the opening forming step of the fifth embodiment can be applied to the semiconductor device of the first or third embodiment.

Sixth Embodiment FIG. 11 is a cross-sectional view showing a process of removing an insulating layer in an electrode forming process of a semiconductor device according to a sixth embodiment of the present invention. In FIG. 11, the same components as those in FIG. 2 or FIG. The electrode structure of the semiconductor device of the sixth embodiment is the same as that of the semiconductor device of the second embodiment. The electrode formation process of the sixth embodiment is substantially the same as the electrode formation process of the second embodiment shown in FIG. However, in the electrode forming step of the fifth embodiment, in the step of cutting the insulating layer (step shown in FIG. 5 (4)), the insulating resin that is the insulating layer is etched by the plasma etching technique using the conductor 405 as a mask. It is characterized by.

As shown in FIG. 11A, a semiconductor integrated circuit substrate 100 in which a curable insulating resin 604 to be pedestals 404a and 404b is formed, an opening 406 is formed in the insulating resin 604, and a conductor 405 is further formed. On the other hand, plasma etching is performed using an etching gas 701 containing oxygen (O ₂ ) as a main component. A polyimide resin is used as the insulating resin 604. Since the conductor 405 is not etched by the plasma of the etching gas 701 and the polyimide resin is etched by the above plasma, the surface of the insulating resin 604 that becomes the pedestal portion 404b is selectively etched using the conductor 405 as an etching mask.

  By etching the surface of the insulating resin 604 to be the pedestal portion 404b by ΔT by the above-described plasma etching, the pedestal portion 404b is formed as shown in FIG.

As described above, according to the sixth embodiment, the pedestal 404b is formed by using the insulating resin 604 (polyimide resin) as the insulating layer and forming the pedestal 404b by the plasma etching technique using the etching gas mainly containing O _2. Thus, the etching depth ΔT of the insulating resin 604 can be controlled accurately and easily to an arbitrary value.

  Note that the insulating layer etching step of the sixth embodiment can be applied to the semiconductor device of the first, third, fourth, or fifth embodiment.

Seventh Embodiment FIG. 12 is a sectional view showing an electrode structure in a semiconductor device according to a seventh embodiment of the present invention. In FIG. 12, the same components as those in FIG. 1 or FIG. The electrode structure of the seventh embodiment shown in FIG. 12 is the same as the electrode structure of the second embodiment shown in FIG. 4 except that the semiconductor integrated circuit substrate 100 on which the wiring 101, the surface protective film 102, and the trimming wiring 501 are formed. On top, pedestal portions 404a and 404b having different heights, conductors 405, and openings 406 are formed. The surface protective film 102 and the trimming wiring 801 constitute a trimming pad portion 802.

  The electrode structure of the seventh embodiment is characterized in that trimming based on the result of an electrical test, that is, a trimming pad portion 802 that has undergone processing of the trimming wiring 801 is covered with pedestals 404a and 404b. Is.

  FIG. 13 is a cross-sectional view showing a trimming step and an opening forming step in the electrode forming step of the semiconductor device of the seventh embodiment shown in FIG. In FIG. 13, the same components as those in FIG. 2 or FIG. The electrode forming process of the seventh embodiment is substantially the same as the electrode forming process of the second embodiment shown in FIG. However, in the electrode forming process of the seventh embodiment, the trimming process shown in FIG. 13 (1) is performed before the processes shown in FIGS. 5 (1) to (4), and the opening forming process is performed. An opening is formed so as to expose any wiring other than the trimming wiring, and the trimming pad is covered with an insulating layer.

  First, as shown in FIG. 13A, an electrical test is performed on the semiconductor integrated circuit of the semiconductor integrated circuit substrate 100 in which the wiring 101, the surface protection film 102, and the trimming wiring 801 have been formed. Based on the above, the trimming wiring 801 is processed. That is, the trimming wiring 801 exposed to the trimming pad portion 802 is cut as necessary.

  Next, as shown in FIG. 13B, an insulating layer 204 to be a pedestal 404a is formed on the semiconductor integrated circuit substrate that has been subjected to the electrical test and trimming described above, and an opening 406 is formed in the insulating layer 204. A forming step is performed. For example, as in FIG. 5A, a curable polyimide resin is used as the insulating layer 204, and the polyimide resin is cured after forming the opening 406. At this time, the opening 406 is formed in a region excluding the region where the trimming pad portion 802 is formed, and the trimming pad portion 802 remains covered with the insulating layer 204. The subsequent steps not shown in the figure are the same as those shown in FIGS.

  As described above, according to the seventh embodiment, the trimming wiring 801 of the trimming pad portion 802, which is not preferably exposed after the end of the trimming step, is formed after the opening forming step by the insulating layer 204 serving as a pedestal portion. By covering, it is possible to prevent the trimming wiring 801 from being influenced by each process after the end of the trimming process, in particular, the formation of the conductive film and the patterning process, and the processing state of the trimming wiring 801 at the trimming process. Can be maintained.

Eighth Embodiment FIG. 14 is a sectional view showing an electrode structure in a semiconductor device according to an eighth embodiment of the present invention. In FIG. 14, the same components as those in FIG. 1 or FIG. In the electrode structure of the eighth embodiment, the bump electrode 901 is provided on the conductor 405 formed on the top surface 405a-a of the pedestal 405a in the electrode structure of the second embodiment shown in FIG. It is characterized by. As the material of the bump electrode 901, a high melting point metal such as Au or Cu may be used, or a low melting point metal such as Pb—Sn (solder) or indium (Ιn) may be used.

  The higher pedestal portion 404 a, the conductor 405, the opening 406, and the bump electrode 901 constitute an electrode portion 907, and the lower pedestal portion 104 a constitutes a surface protection portion 408. If the height of the bump electrode 901 is H, the connecting portion 907 is higher than the connecting portion 407 of the second embodiment shown in FIG. In addition, the electrode formation process of 8th Embodiment implements the formation process of the bump electrode 901, after implementing the electrode formation process of the said 2nd Embodiment shown in FIG. 5, for example.

  FIG. 15 is a cross-sectional view showing a structure around the connection portion between the electrode and the connection substrate in the semiconductor device according to the eighth embodiment. FIG. 15 shows bonding of the electrode portion 907 to the lead 301 of the connection substrate such as a tape carrier. (2) shows the case where the electrode portion 907 is bonded to the wiring 302 of the connection substrate 300. The bump electrode 907 of the electrode portion 907 is bonded to the lead 301 (FIG. 15 (1)) or the wiring 302 (FIG. 15 (2)) of the connection substrate by a thermocompression bonding method or a reflow method.

  As described above, according to the eighth embodiment, by providing the bump electrode 901 on the base 405a made of the insulating layer via the conductor 405, the electrode portion from the surface of the semiconductor integrated circuit can be compared with the case where the bump electrode 901 is not provided. Since the height to the connection surface with the lead 301 or the wiring 302 of 907 is increased, distortion due to thermal stress can be easily absorbed, and connection reliability can be further increased. Further, when solder is used as the bump electrode 901, a self-alignment effect can be expected even when the connection position is slightly shifted when connecting to the connection substrate.

Ninth Embodiment FIG. 16 is a cross-sectional view showing the structure of a semiconductor device according to a ninth embodiment of the present invention. In the semiconductor device shown in FIG. 16, the semiconductor integrated circuit substrate 1000 is mounted face-down on the connection substrate 300, that is, the semiconductor integrated circuit formation surface is opposed to the connection substrate 300, and a sealing resin 1001 is filled therebetween. is there. As the sealing resin 1001, for example, a polyimide resin is used. The surface of the semiconductor integrated circuit substrate 1000 has an electrode 1007 in which a conductor 1005 is formed on a pedestal 1004 made of an insulating layer. The insulating layer is, for example, polyimide resin, and the electrode 1007 is, for example, the electrode of the first embodiment shown in FIG. The semiconductor device of the ninth embodiment is characterized in that the sealing resin 1001 and the pedestal 1004 are made of the same material (for example, polyimide resin).

  In a semiconductor device having a face-down connection structure using a conventional metal bump electrode and a sealing resin made of a polymer resin, the bump electrode expands as the sealing resin expands due to a difference in thermal expansion coefficient between the bump electrode and the sealing resin. Such a thermal stress may occur, and the bump electrode may be destroyed by thermal fatigue. However, if the sealing resin 1001 and the pedestal 1004 of the electrode 1007 are the same material as in the semiconductor device of the ninth embodiment, there is no difference in thermal expansion coefficient between them, and the electrode 1007 is destroyed. Never happen.

  As described above, according to the ninth embodiment, the sealing resin 1001 and the pedestal 1004 are formed of the same material, and the thermal expansion coefficients of the sealing resin 1001 and the pedestal 1004 are the same, thereby making the electrode 1007 have a thermal fatigue. Therefore, it is possible to improve the connection reliability of the electrodes.

It is sectional drawing which shows the electrode structure in the semiconductor device of the 1st Embodiment of this invention. It is a cross-section figure showing an electrode formation process of a semiconductor device of a 1st embodiment of the present invention. It is sectional drawing which shows the structure of the connection part periphery of the electrode and connection board in the semiconductor device of the 1st Embodiment of this invention. It is sectional drawing which shows the electrode structure of the semiconductor device of the 2nd Embodiment of this invention. It is sectional structure drawing which shows the electrode formation process of the semiconductor device of the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the connection part periphery of the electrode and connection board in the semiconductor device of the 2nd Embodiment of this invention. It is sectional drawing which shows the electrode structure of the semiconductor device of the 3rd Embodiment of this invention. It is sectional structure drawing which shows the electrode formation process of the semiconductor device of the 3rd Embodiment of this invention. It is sectional structure drawing which shows the electrode formation process of the semiconductor device of the 4th Embodiment of this invention. It is sectional structure drawing which shows the electrode formation process of the semiconductor device of the 5th Embodiment of this invention. It is sectional structure drawing which shows the electrode formation process of the semiconductor device of the 6th Embodiment of this invention. It is sectional drawing which shows the electrode structure of the semiconductor device of the 7th Embodiment of this invention. It is sectional structure drawing which shows the electrode formation process of the semiconductor device of the 7th Embodiment of this invention. It is sectional drawing which shows the electrode structure of the semiconductor device of the 8th Embodiment of this invention. It is sectional drawing which shows the structure of the connection part periphery of the electrode and connection board in the semiconductor device of the 8th Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the 9th Embodiment of this invention.

Explanation of symbols

  100, 1000 semiconductor integrated circuit board, 101 wiring, 104a, 104b, 404a, 404b, 1004 pedestal, 104a-a, 104b-a, 404a-a, 404b-a pedestal top, 105, 405, 1005 conductor, 106, 406 opening, 204 insulating layer, 205 conductive film, 300 connection substrate, 504 photosensitive insulating resin, 604 insulating resin, 801 trimming wiring, 901 bump electrode, 1001 sealing resin.

Claims (10)

A semiconductor substrate having a main surface with a semiconductor integrated circuit;
A base made of a resin formed on the main surface of the semiconductor substrate and having a first surface facing the main surface of the semiconductor substrate and a second surface facing the first surface;
A first portion disposed on the main surface of the semiconductor substrate and connected to the semiconductor integrated circuit; a central portion extending from the first portion; and the second portion of the pedestal extending from the central portion. A conductive layer having a second portion disposed on the surface of
A semiconductor device comprising: a connection substrate disposed facing the main surface of the semiconductor substrate and connected to the second portion of the conductive layer.   The semiconductor device according to claim 1, wherein the conductive layer and the pedestal form an electrode.   The second portion of the conductive layer includes a third surface disposed on the second surface of the pedestal, and a fourth surface facing the third surface and connected to the connection substrate. The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 1, wherein the second portion of the conductive layer is connected to a conductive line of the connection substrate. A semiconductor substrate having a main surface with a semiconductor integrated circuit;
A base made of resin formed on the main surface of the semiconductor substrate;
A conductive layer formed on the main surface of the semiconductor substrate, connected to the semiconductor integrated circuit and having an extending portion extending on the upper surface of the pedestal;
A semiconductor device comprising: a connection substrate facing the main surface of the semiconductor substrate and connected to the extending portion of the conductive layer on the upper surface of the pedestal. The extending portion of the conductive layer has a first surface facing the upper surface of the pedestal and a second surface facing the first surface;
The semiconductor device according to claim 5, wherein the connection substrate is connected to the second surface of the extending portion of the conductive layer.   The semiconductor device according to claim 5, wherein the extending portion of the conductive layer is connected to a conductive line of the connection substrate.   The semiconductor device according to claim 1, wherein the connection substrate is a tape carrier.   The semiconductor device according to claim 1, wherein the conductive layer has a stacked structure of different conductive materials.   6. The semiconductor device according to claim 1, further comprising: a sealing material that fills a space between the semiconductor substrate and the connection substrate and has the same thermal expansion coefficient as the pedestal.

Images