JP2005218264A - Current limit circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current limit circuit for limiting an output current by controlling a switching element connected between an input and output, and a power circuit, capable of preventing erroneous operation. <P>SOLUTION: This current limit circuit (100), which limits an output current by controlling the switching element (M1) connected between an input and output, includes current mirror circuits (M14, M15) for outputting a current corresponding to a gate potential of the switching element (M1) to a source of the switching element (M1), and control circuits (11, 12, M2, R3, M21 to M24, R21 to R24) for controlling a gate potential corresponding to each of output currents of the current mirror circuits (M14, M15). Moreover, a current inflow side transistor (M14) of the current mirror circuit (M14, M15) has its source kept at a base potential (GND). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a current limiting circuit, and more particularly to a current limiting circuit that limits an output current by controlling a switching element connected between input and output.

  FIG. 6 shows a circuit configuration diagram of an example of a conventional power supply circuit.

The power supply circuit 1 is a circuit that controls the output current Iout according to the output voltage Vout and controls the output voltage Vout to be constant. The power supply circuit 1 includes an error amplifier 11, a reference voltage source 12, a current limiting circuit 13, a transistor M 1, resistors R 1 and R 2, and a one-chip IC (integrated
circuit) and has an input terminal Tin, an output terminal Tout, and a ground terminal Tgnd. A DC power supply 2 and a capacitor C1 are connected in parallel to the input terminal Tin, and a power supply voltage VDD is applied from the DC power supply 2. The power supply voltage VDD is rippled by the capacitor C1. A load RL and a capacitor C2 are connected in parallel to the output terminal Tout, and an output voltage Vout from which ripple has been removed by the capacitor C2 is applied to the load RL. The ground terminal Tgnd is grounded.

  The input terminal Tin is connected to the drain of the transistor M1 inside the power supply circuit 1. The output terminal Tout is connected inside the power supply circuit 1 to the source of the transistor M1 and one end of the resistor R1.

  The transistor M1 is composed of a p-channel MOS (metal-oxide-semiconductor) field effect transistor, the drain-source is connected in series between the input terminal Tin and the output terminal Tout, and the output of the error amplifier 11 is connected to the gate. It is connected. The transistor M1 controls the output current Iout according to the output of the error amplifier 11.

  The error amplifier 11 has a non-inverting input terminal connected to the resistors R1 and R2, and a reference voltage Vref from the reference voltage source 12 is applied to the inverting input terminal. The resistor R1 and the resistor R2 are connected in series between the output terminal Tout and the ground terminal Tgnd, and the detection voltage Vs obtained by dividing the output voltage Vout by the resistance ratio of the resistor R1 and the resistor R2 is used as the resistor R1 and the resistor R2. Output from the connection point with R2.

  The error amplifier 11 outputs a voltage corresponding to the difference between the detection voltage Vs and the reference voltage Vref and supplies it to the gate of the transistor M1. For example, when the detection voltage Vs becomes larger than the reference voltage Vref, the output of the error amplifier 11 increases, the impedance between the drain and source of the transistor M1 increases, the output current Iout decreases, and the output voltage Vout decreases. Further, when the detection voltage Vs becomes smaller than the reference voltage Vref, the output of the error amplifier 11 becomes small, the drain-source impedance of the transistor M1 becomes small, the output current Iout increases, and the output voltage Vout increases. With the above operation, the output voltage Vout is held constant.

  On the other hand, the current limiting circuit 13 is a circuit for limiting the output current Iout, and includes transistors M11 to M16 and a resistor R11.

  The transistors M11 and M12 are p-channel MOS field effect transistors and constitute a clamp circuit. The transistors M11 and M12 are connected in series between the drain of the transistor M1 and the connection point between the resistor R1 and the resistor R2, and the detection voltage Vs is clamped at a predetermined voltage, and the output current Iout is set to the predetermined current Iout0. Limit to.

  The transistor M13 is composed of a p-channel MOS field effect transistor, the drain is connected to the drain of the transistor M1, the source is connected to the drain and gate of the transistor M14 and the gate of the transistor M15, the gate is the gate of the transistor M1, That is, it is connected to the output of the error amplifier 11. The transistor M13 supplies a current corresponding to the output of the error amplifier 11 to the transistor 14.

  The transistors M14 and M15 are composed of n-channel MOS field effect transistors and constitute a current mirror circuit. The transistor M14 has a drain and a gate connected to the source of the transistor M13, and a source connected to the source of the transistor M1. The transistor M15 has a gate connected to the source of the transistor M13 and the drain and gate of the transistor M14, and a drain connected to the drain of the transistor M1 through the resistor R11.

  The transistor M16 is composed of a p-channel MOS field effect transistor, the drain is connected to the drain of the transistor M1, and the source is connected to the connection point between the resistors R1 and R2, that is, the non-inverting input terminal of the error amplifier 11. The gate is connected to the connection point between the resistor R11 and the drain of the transistor M15.

  Here, the operation of the current limiting circuit 13 will be described.

  FIG. 6 is an operation explanatory diagram of the current limiting circuit 13.

  When the output current Iout increases due to an increase in the load RL, the gate-source voltage Vgs of the transistor M1 increases. When the gate-source voltage Vgs of the transistor M1 increases, the transistors M11 and M12 are first turned on, the detection voltage Vs, that is, the non-inverting input terminal of the error amplifier 11 is clamped, and the output current Iout is limited by the current Iout0. Is done.

  When the output current Iout is limited by the current Iout0, the output voltage Vout decreases. When the output voltage Vout decreases, the detection voltage Vs decreases and the output of the error amplifier 11 decreases, so that the impedance between the drain and source of the transistor M13 decreases and the drain current of the transistor M15 increases. As a result, the source current of the transistor M16 increases, the potential of the non-inverting input terminal of the error amplifier 11 increases, the output current Iout and the output voltage Vout both decrease, and the characteristics shown in FIG. Indicates.

  In addition, the publicly known literature corresponding to said power supply circuit 1 was not discovered.

  However, in the conventional power supply circuit 1, when the voltage difference between the input voltage VDD and the output voltage Vout increases, the current flowing through the transistor M15 increases, and thus the transistor M16 is turned on in a region where no current limitation is required. However, there were problems such as the current limit being applied.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a current limiting circuit that can prevent malfunction when a voltage difference between input and output voltages becomes large.

  In the current limiting circuit (113) that limits the output current by controlling the switching element (M1) connected between the input and output, a current corresponding to the gate potential of the switching element (M1) is applied to the switching element (M1). Current mirror circuit (M14, M15) output to the source of M1) and control circuit (11, 12, M2) for controlling the gate potential of the switching element (M1) in accordance with the output current of the current mirror circuit (M14, M15) , R3, M21 to M24, R21 to R24), and the current inflow side transistor (M14) of the current mirror circuit (M14, M15) is characterized in that the source is set to the ground potential (GND).

  The base potential (GND) is a ground potential.

  In the current mirror circuit (M14, M15), a gate is connected to the gate of the switching element (M1), an input voltage is applied to the drain, and a current corresponding to the gate potential of the switching element (M1) is output from the source. Transistor (M13), a second transistor (M14) in which the drain and gate are connected to the source of the first transistor (M13), the source is set to the ground potential (GND), and the gate is the first transistor ( A third transistor (M15) connected to the source of M1) and the drain and gate of the second transistor (M14), the source connected to the source of the switching element (M1), and outputting an output current from the drain; It is characterized by that.

  The control circuit (11, 12, M2, R3, M11, M12, M21 to M24, R21 to R24) includes a reference voltage source (12) that generates a reference voltage (Vref), a reference voltage (Vref), and an output voltage ( An error amplifier (11) that outputs a signal corresponding to a difference from a voltage corresponding to Vout) to the gate of the switching element (M1), and another current mirror circuit that folds back the output current of the current mirror circuit (M14, M15) ( M21, M22, R21, R22) and circuits (M23, R24) for controlling the output of the error amplifier (11) in accordance with the currents returned by the other current mirror circuits (M21, M22, R21, R22) It is characterized by having.

  It has a clamp circuit (M24, R23; M11, M12) for clamping the gate potential of the switching element (M1) when the output current (Iout) exceeds a predetermined value.

  In addition, the said reference code is a reference to the last, This does not limit a claim.

  According to the present invention, the current inflow side transistor (M14) of the current mirror circuit (M14, M15) that outputs a current corresponding to the gate potential of the switching element (M1) to the source of the switching element (M1) has a source at the base potential. (GND) makes it possible to operate the current mirror circuit (M14, M15) with reference to the base potential (GND), and even if the voltage difference between the input voltage VDD and the output voltage Vout becomes large, Since the output current of the mirror circuit (M14, M15) does not increase, the output current of the switching element (M1) can be limited without being affected by the voltage difference between the input voltage VDD and the output voltage Vout. It is possible to prevent malfunction when the voltage difference between the voltage VDD and the output voltage Vout increases.

[First embodiment]
FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, the same components as those in FIG.

  In the power supply circuit 100 of the present embodiment, the connection point between the resistor R1 and the resistor R2 is connected to the inverting input terminal of the error amplifier 11, and the reference voltage Vref generated by the reference voltage source 12 is used as the non-inverting input terminal of the error amplifier 11. And the output of the error amplifier 11 is connected to the gate of the transistor M1 through a buffer composed of the transistor M2 and the resistor R3.

  In the present embodiment, the configuration of the current limiting circuit 113 is different from that of the current limiting circuit 13 of FIG. The current limiting circuit 113 of this embodiment is configured by connecting the source of the transistor M14 of the current limiting circuit 13 to the ground terminal Tgnd.

  By connecting the source of the transistor M14 to the ground terminal Tgnd, the operation can be performed with reference to the ground, so that the current limiting operation can be performed without being affected by the voltage difference between the input voltage VDD and the output voltage Vout. Therefore, malfunction can be prevented.

  In addition, the current limiting circuit 113 of the present embodiment is configured by providing a circuit including transistors M21 to M24 and resistors R21 to R24 in place of the transistors M11, M12, and M16 and the resistor R11 of the current limiting circuit 13. ing.

  The transistors M21 and M22 are composed of n-channel MOS field effect transistors, constitute a current mirror circuit together with the resistors R11 and R12, and output a current corresponding to the drain current of the transistor M15 from the source of the transistor M22. The source of the transistor M22 is grounded through the resistor R24.

  The resistor R24 has one end connected to the ground terminal Tgnd and the other end connected to the source of the transistor M22 and the source of the transistor M24. The current from the transistors M22 and M24 flows, and a voltage corresponding to the flowing current is generated. To do.

  The transistor M24 is composed of a p-channel MOS field effect transistor, the drain is connected to the input terminal Tin through the resistor R23, and the gate is connected to the gate of the transistor M1. The transistor M24 forms a current mirror circuit together with the transistor M1, and supplies a current corresponding to the current flowing through the transistor M1 to the resistor R24. At this time, the current flowing through the transistor M24 is limited by the resistor R23. One end of the resistor R24 is connected to the gate of the transistor M23.

  The transistor M23 is composed of a p-channel MOS field effect transistor, the drain is connected to the output of the error amplifier 11, the source is connected to the ground terminal Tgnd, and the drain current thereof depends on the voltage generated at the resistor R24. Is controlled. The source of the transistor M23 is connected to the ground terminal Tgnd.

  The transistor M2 is composed of a p-channel MOS field effect transistor, and the output of the error amplifier 11 is connected to the gate and the drain of the transistor M23 is connected. The drain of the transistor M2 is connected to the input terminal Tin via a resistor R3. The source of the transistor M2 is connected to the ground terminal Tgnd. A connection point between the drain of the transistor M2 and the resistor R3 is connected to the gate of the transistor M1.

[Operation]
FIG. 2 is an operation explanatory diagram of the current limiting circuit 113.

  When the output current Iout increases due to an increase in the load RL, the transistor M24 that forms a current mirror circuit with the transistor M1 is turned on. When the transistor M24 is turned on, the gate potential of the transistor M23 rises and the transistor M23 is turned on.

  When the transistor M23 is turned on, the gate potential of the transistor M2 is lowered and the transistor M2 is turned off. When the transistor M2 is turned off, the gate potential of the transistor M1 rises and its impedance increases, thereby limiting the output current Iout.

  When the output current Iout is limited by the transistor M1, the output voltage Vout decreases. When the output voltage Vout decreases, the source potential of the transistor M15 decreases. As a result, the source current of the transistor M21 increases. As the source current of the transistor M21 increases, the source current of the transistor M22 increases.

  As the source current of the transistor M22 increases, the gate potential of the transistor M23 increases and the current flowing through the transistor M23 increases. As a result, the gate potential of the transistor M2 is decreased, the impedance of the transistor M2 is further increased, the gate potential of the transistor M1 is increased, the impedance is further increased, and the output current Iout and the output current Vout are further decreased. As shown in FIG.

  In this embodiment, the error amplifier 11 is inverted, the drain current of the transistor M15 is supplied to the output of the error amplifier 11 through the transistors M21 to M24 and the resistors R21 to R24, and the output of the error amplifier 11 is controlled. 11 is inverted by the transistor M2 and the resistor R3 to control the transistor M1. Thereby, temperature characteristics can be improved.

[Second Embodiment]
FIG. 3 shows a circuit configuration diagram of the second embodiment of the present invention. In the figure, the same components as those in FIGS. 1 and 5 are denoted by the same reference numerals, and the description thereof is omitted.

  The power supply circuit 200 of the present embodiment is different from the first embodiment in the configuration of the current limiting circuit 213. The current limiting circuit 213 of this embodiment is a current limiting circuit 13 of the power supply circuit 1 shown in FIG. 5 instead of the current mirror circuit including the transistors M21 and M22 and the resistors R21 and R22 of the current limiting circuit 113 shown in FIG. A circuit composed of a transistor M16 and a resistor R11 is used.

  According to the power supply circuit 200 of the present embodiment, the same effects as in the first embodiment can be obtained.

[Third embodiment]
FIG. 4 shows a circuit configuration diagram of the third embodiment of the present invention. In the figure, the same components as those in FIGS. 1 and 5 are denoted by the same reference numerals, and the description thereof is omitted.

  The power supply circuit 300 of the present embodiment is different from the first embodiment in the configuration of the current limiting circuit 313. The current limiting circuit 313 of this embodiment is a transistor used in the current limiting circuit 13 of the power supply circuit 1 shown in FIG. 5 instead of the clamp circuit comprising the transistor M24 and the resistor R23 of the current limiting circuit 313 shown in FIG. A circuit composed of M11 and M12 is applied as a clamp circuit.

  According to the power supply circuit 300 of the present embodiment, the same effects as in the first embodiment can be obtained.

It is a circuit block diagram of 1st Example of this invention. It is a characteristic view of the output current-output voltage of 1st Example of this invention. It is a circuit block diagram of 2nd Example of this invention. It is a circuit block diagram of 3rd Example of this invention. It is a circuit block diagram of a conventional example. 6 is an operation explanatory diagram of a current limiting circuit 13. FIG.

Explanation of symbols

100, 200, 300 Power supply circuit 113, 213, 313 Current limiting circuit M13, M14, M15, M21 to M24 transistor, R21 to R24 resistor 11 Error amplifier 12 Reference voltage source M1, M2 Transistors R1, R2, R3 Resistor 2 DC power supply RL load C1, C2 capacitor

Claims (5)

In the current limiting circuit that limits the output current by controlling the switching element connected between the input and output,
A current mirror circuit that outputs a current corresponding to a gate potential of the switching element to a source of the switching element;
A control circuit for controlling the gate potential of the switching element according to the output current of the current mirror circuit,
A current limiting circuit, wherein the current inflow side transistor of the current mirror circuit has a source at a base potential. The current limiting circuit according to claim 1, wherein the base potential is a ground potential. The current mirror circuit includes a first transistor whose gate is connected to the gate of the switching element, an input voltage is applied to the drain, and a current corresponding to the gate potential of the switching element is output from the source;
A second transistor in which a drain and a gate are connected to a source of the first transistor, and a source is set to a ground potential;
A gate connected to a source of the first transistor and a drain and gate of the second transistor; a source connected to a source of the switching element; and a third transistor outputting the output current from the drain. The current limiting circuit according to claim 1 or 2. The control circuit includes a reference voltage source that generates a reference voltage, an error amplifier that outputs a signal according to a difference between the reference voltage and a voltage according to the output voltage to a gate of the switching element,
Other current mirror circuits that fold back the output current of the current mirror circuit;
And a circuit for controlling the output of the error amplifier according to the current folded by the other current mirror circuit. 5. The current limiting circuit according to claim 1, further comprising: a clamp circuit that clamps a gate potential of the switching element when the output current exceeds a predetermined value. 6.

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