JP2005217003A - Package for storing semiconductor element - Google Patents

Package for storing semiconductor element Download PDF

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JP2005217003A
JP2005217003A JP2004019549A JP2004019549A JP2005217003A JP 2005217003 A JP2005217003 A JP 2005217003A JP 2004019549 A JP2004019549 A JP 2004019549A JP 2004019549 A JP2004019549 A JP 2004019549A JP 2005217003 A JP2005217003 A JP 2005217003A
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semiconductor element
frame
wiring board
package
thermal expansion
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JP4885425B2 (en
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Kazutaka Maeda
和孝 前田
Shoichi Nakagawa
彰一 仲川
Tomoko Tajiri
智子 田尻
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a package for storing semiconductor element with which a stiffener and a radiation cover plate-low coefficients of thermal expansion can be incorporated into a wiring board without impeding packaging of the semiconductor element, and a firm and stable connection state can be maintained for long time with an outer circuit board. <P>SOLUTION: The package for storing semiconductor element is provided with the wiring board, a semiconductor element loading part formed on one surface of the wiring board, a reinforcing frame arranged at a periphery of the semiconductor element loading part in a frame shape, and a radiation cover which is joined to the reinforcing frame and joined to the surface of the wiring board for closely sealing the semiconductor element. The reinforcing frame is formed of a structure where at least two frame boards are overlapped. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は半導体素子を搭載収納するための半導体素子収納用パッケージに関し、特に、シリコンチップ等の半導体素子を搭載収納するための配線基板、放熱蓋板、等のパッケージ部材の強度を補強する補強枠（スティフナ）を備えた有機樹脂基板製のパッケージに関する。   The present invention relates to a package for housing a semiconductor element for mounting and storing a semiconductor element, and more particularly, a reinforcing frame for reinforcing the strength of a package member such as a wiring board and a heat radiation lid plate for mounting and storing a semiconductor element such as a silicon chip. The present invention relates to a package made of an organic resin substrate provided with (stiffener).

近年、高度情報化時代を迎え、情報通信技術が急速に発展し、それに伴い、各種半導体素子の高速化、高度集積化が図られている。
これに対応して、半導体素子収納パッケージも高性能化及び高実装密度化の傾向が顕著となり、その主流がピン挿入型から表面実装型へ移行するだけでなく半導体素子の作動周波数の向上に伴い配線基板を薄型化して基板内の配線長さをより一層短くすることが強く求められるようになってきている。 In recent years, with the advent of advanced information technology, information communication technology has been rapidly developed, and accordingly, various semiconductor elements have been increased in speed and highly integrated.
Correspondingly, the trend toward higher performance and higher mounting density has become prominent in semiconductor element storage packages, and not only the mainstream shifts from pin insertion type to surface mounting type, but also as the operating frequency of semiconductor elements increases. There is a strong demand to further reduce the wiring length in the substrate by making the wiring substrate thinner.

然し、フリップチップ（flipchip)接続ＢＧＡ(Ball Grid Array)タイプパッケージ等の表面実装型パッケージは、従来構造のままの場合、基板厚みを薄くすると、僅かの外力や温度差で撓みや熱歪みが生じ、パッケージとプリント基板の接続不良等の不都合を招来し勝ちとなる。
この対策として、例えば、特許文献１，特許文献２等に記載されているように、配線基板と放熱蓋板（リッド）との間にスティフナと呼ばれる補強枠板を挿入し、この枠内に素子を収容して配線基板を含むパッケージ全体を機械的に補強し、前記歪み変形を抑制することが従来から行われてきた。 However, surface mount packages such as flip chip connection BGA (Ball Grid Array) type packages have the conventional structure, and if the substrate thickness is reduced, bending and thermal distortion will occur due to slight external force and temperature difference. Inconvenience such as poor connection between the package and the printed circuit board is likely to occur.
As countermeasures, for example, as described in Patent Document 1, Patent Document 2, etc., a reinforcing frame plate called a stiffener is inserted between the wiring board and the heat radiating cover plate (lid), and the element is inserted into this frame. It has been conventionally performed to mechanically reinforce the entire package including the wiring substrate and to suppress the distortion deformation.

参考までに、上記のような従来の半導体装置（半導体素子収納パッケージ）の構造を模式的に図３に示す。
この装置はＢＧＡタイプで、半導体素子２１、配線基板２２，放熱蓋板（リッド、又はキャップ）２３、及び充填樹脂（アンダーフィル）２５等により構成され、更に、半導体素子（チップ）２１にはその底面に複数のハンダバンプ２６が形成されており、このハンダバンプ２６を配線基板２２の上面に形成された接続パターンにハンダ溶融しフリップチップ接続させることにより半導体素子は配線基板２２に搭載される。
配線基板２２には、セラミックスの他、最近では、装置全体のコスト低減を図るため、例えば、ガラス繊維入りエポキシ樹脂、ガラス繊維入りポリイミド樹脂等の有機樹脂製基板やポリエステル樹脂フィルム、ポリイミド樹脂フィルム等からなるフレキシブル基板が多く用いられる傾向にある。
この配線基板２２の下面には外部接続端子となるボール（ハンダボール）２７が配設されている。
又、配線基板２２上面に形成された接続パターンと配線基板２２下面に形成されたハンダボール２７の接合部とは、配線基板２２の内部に配設されたスルーホール（図示せず）により電気的に接続された構成となっている。 For reference, the structure of a conventional semiconductor device (semiconductor element storage package) as described above is schematically shown in FIG.
This device is a BGA type, and is composed of a semiconductor element 21, a wiring substrate 22, a heat radiation cover plate (lid or cap) 23, a filling resin (underfill) 25, and the like. A plurality of solder bumps 26 are formed on the bottom surface, and the semiconductor elements are mounted on the wiring substrate 22 by solder melting the solder bumps 26 to a connection pattern formed on the upper surface of the wiring substrate 22 and performing flip chip connection.
In addition to ceramics, the wiring board 22 is recently made of an organic resin substrate such as an epoxy resin containing glass fiber, a polyimide resin containing glass fiber, a polyester resin film, a polyimide resin film, etc. A flexible substrate made of
Balls (solder balls) 27 serving as external connection terminals are disposed on the lower surface of the wiring board 22.
Further, the connection pattern formed on the upper surface of the wiring board 22 and the joint portion of the solder ball 27 formed on the lower surface of the wiring board 22 are electrically connected by a through hole (not shown) provided in the wiring board 22. It is the composition connected to.

又、放熱蓋板２３は一般的には平板形状で配線基板２２全体を覆うように配置されており、例えば銅やアルミニウム等の熱伝導性の高い金属材料により形成されている。
そして、この放熱蓋板２３と半導体素子２１との間にはペースト材２８が介装された構成となっている。
放熱蓋板２３は半導体素子２１で発生する熱を放熱する放熱板として機能するため、より広い放熱領域を設けられるように配線基板２２を覆うように配置される。 Further, the heat radiation cover plate 23 is generally formed in a flat plate shape so as to cover the entire wiring substrate 22 and is formed of a metal material having high thermal conductivity such as copper or aluminum.
A paste material 28 is interposed between the heat dissipation cover plate 23 and the semiconductor element 21.
Since the heat dissipation cover plate 23 functions as a heat dissipation plate that dissipates heat generated in the semiconductor element 21, the heat dissipation cover plate 23 is disposed so as to cover the wiring substrate 22 so as to provide a wider heat dissipation region.

ペースト材２８には、金属フィラー（例えば銀）入り樹脂ペースト、非金属フィラー（例えばシリコン）入り樹脂ペースト、又はロウ材（例えばハンダ）等の比較的熱伝導性が良く強い接着力を有する材料が用いられる。   The paste material 28 includes a material having a relatively high thermal conductivity and a strong adhesive force, such as a resin paste containing a metal filler (eg, silver), a resin paste containing a non-metal filler (eg, silicon), or a brazing material (eg, solder). Used.

尚、スティフナ（補強枠）２４は配線基板２２と放熱蓋板２３の間に装着し、夫々と接着固定することで放熱蓋板２３の機械的安定性を高める役割をしている。
このスティフナ２４は配線基板２２、放熱蓋板２３の何れかと一体化させておいても良く、この態様のものも多い。
次に充填樹脂（アンダーフィル）２５は例えば熱硬化性のプラスチックであるエポキシ樹脂等が用いられ、このアンダーフィル２５により半導体素子２１は封止され、ハンダバンプ２６に加わる応力を広い面積で受けることによりハンダバンプに加わる応力を分散緩和させる役割を果たす。
特開平１１−０１７０６４号公報 特開２００１−１１０９２６号公報 The stiffener (reinforcing frame) 24 is mounted between the wiring board 22 and the heat dissipation cover plate 23 and serves to enhance the mechanical stability of the heat dissipation cover plate 23 by being bonded and fixed thereto.
The stiffener 24 may be integrated with either the wiring board 22 or the heat dissipation cover plate 23, and there are many such embodiments.
Next, as the filling resin (underfill) 25, for example, an epoxy resin which is a thermosetting plastic is used. The semiconductor element 21 is sealed by the underfill 25, and the stress applied to the solder bump 26 is received over a wide area. It plays a role of dispersing and relaxing the stress applied to the solder bump.
Japanese Patent Laid-Open No. 11-017064 JP 2001-110926 A

既に述べたように、最近に於いては半導体素子の作動周波数の向上に伴い、配線基板の薄型化傾向が顕著であるが、上記従来構造のパッケージでは配線基板の厚みを薄くすると、パッケージとプリント基板のハンダ接合部が、例えば、EIAJ ET−7407等に規定の所定信頼性試験である温度サイクル試験に於いて熱疲労破壊してしまい、信頼性要求を満たすことが出来ないと云う問題がある。
これは、半導体素子の主流を占めるシリコンチップの熱膨張係数が約３ｐｐｍ／℃であるのに対して一般に樹脂製配線基板の熱膨張係数は１５〜１８ｐｐｍ／℃であり、熱膨張係数の差が非常に大きいことに基因している。 As already mentioned, the trend toward thinning of the wiring board has been remarkable recently with the improvement of the operating frequency of the semiconductor element. However, in the package of the conventional structure, when the wiring board is thinned, the package and the print are printed. There is a problem that the solder joint portion of the board fails to satisfy the reliability requirement due to thermal fatigue failure in a temperature cycle test which is a predetermined reliability test prescribed in EIAJ ET-7407, for example. .
This is because the thermal expansion coefficient of silicon chips, which occupy the mainstream of semiconductor elements, is about 3 ppm / ° C., whereas the thermal expansion coefficient of resin wiring boards is generally 15-18 ppm / ° C., and the difference in thermal expansion coefficient is It is based on being very big.

即ち、温度サイクル試験時に例えば−４０から１２５℃の温度変化を与えると、半導体素子と配線基板間には、その熱膨張差により局所的な変形応力歪みが発生し、それを緩和しようとして局所的に反り変形を生じる。
温度サイクル試験に於ける低温・高温サイクルの繰り返しに伴い、ハンダバンプが繰り返し歪み変形応力を受けることにより最終的に疲労破壊してしまうと云うものである。 That is, when a temperature change of, for example, −40 to 125 ° C. is given during the temperature cycle test, a local deformation stress strain is generated between the semiconductor element and the wiring board due to the difference in thermal expansion, and it is locally attempted to alleviate it. Cause warping deformation.
As the low temperature / high temperature cycle in the temperature cycle test is repeated, the solder bumps are repeatedly subjected to strain and deformation stress, resulting in fatigue failure.

スティフナ（補強枠）が無い構造で有れば配線基板も全体的に反ることが出来るため、それにより幾分熱応力を分散緩和することが出来る。
しかしながら、例えば図３のような放熱蓋板、スティフナ、配線基板で囲まれたリジッドな薄型長方形の函体構造で、各部材がほぼ近似した熱膨張係数を有する材質の場合は、配線基板は周縁部をスティフナで固定されているためその全体的な反り変形が抑制されてしまい、半導体素子搭載部だけが局所的に歪むため、ハンダ部に生じる熱応力はスティフナが設けられない構造のものに比べ著しく大きくなる。 If the structure does not have a stiffener (reinforcing frame), the wiring board can also be warped as a whole, whereby thermal stress can be somewhat dispersed and relaxed.
However, for example, in the case of a rigid thin rectangular box structure surrounded by a heat dissipation cover plate, a stiffener, and a wiring board as shown in FIG. Since the part is fixed with a stiffener, its overall warpage deformation is suppressed, and only the semiconductor element mounting part is locally distorted, so the thermal stress generated in the solder part is compared to that of the structure where the stiffener is not provided Remarkably larger.

この半導体素子搭載部の局所熱応力を低減するための手段として、放熱蓋板とスティフナの熱膨張係数を配線基板のそれに比べて小さくする手法が挙げられる。
スティフナと放熱蓋板の熱膨張係数が配線基板よりも幾分小さい場合、スティフナは配線基板と同じ程度には膨張しないため、基板面周縁を拡張させず、温度変化により生じた熱膨張差を配線基板全体が半導体素子と同様に反って緩和する。
このためハンダ接合部に生じる局所熱応力集中を著しく分散緩和させることが出来る。
しかしながら、一方では、スティフナの熱膨張係数が配線基板よりも小さいと、その分素子搭載面を含む基板面の反りが大きくなるという問題がある（半導体素子搭載面の平坦性は素子の正常作動を担保する上で特に重要である。）。
特に配線基板にスティフナを組み付けてから半導体素子を配線基板に実装する場合には、スティフナを組み付けた段階でスティフナと配線基板の熱膨張係数の差に起因した反りが生じてしまうため、半導体素子搭載部の平坦度の問題により半導体素子を配線基板に実装することが困難である。 As a means for reducing the local thermal stress of the semiconductor element mounting portion, there is a technique in which the thermal expansion coefficient of the heat dissipation lid plate and the stiffener is made smaller than that of the wiring board.
When the coefficient of thermal expansion of the stiffener and radiating lid is somewhat smaller than that of the wiring board, the stiffener does not expand to the same extent as the wiring board. The entire substrate is warped and relaxed in the same manner as the semiconductor element.
For this reason, the local thermal stress concentration generated at the solder joint can be remarkably dispersed.
However, on the other hand, if the coefficient of thermal expansion of the stiffener is smaller than that of the wiring board, there is a problem that the warpage of the substrate surface including the element mounting surface becomes larger correspondingly (the flatness of the semiconductor element mounting surface prevents the element from operating normally). It is particularly important in securing.)
In particular, when a semiconductor element is mounted on a wiring board after assembling the stiffener on the wiring board, warping due to the difference in thermal expansion coefficient between the stiffener and the wiring board occurs at the stage where the stiffener is assembled. It is difficult to mount the semiconductor element on the wiring board due to the problem of the flatness of the part.

本発明者等は、パッケージ等の配線基板と外部回路基板の熱膨張差によって接続端子に発生する熱応力を低減する方法について種々検討を重ねた結果、スティフナを重ね構造とすることにより半導体素子の実装を阻害すること無く熱膨張係数の小さいスティフナや放熱蓋板でも配線基板に組み付けることが出来、長期にわたり安定した実装が可能となることを見出し、この知見に基づき本発明を完成した。
従って、本発明の目的は、低熱膨張係数のスティフナや放熱蓋板でも半導体素子の実装を阻害すること無く配線基板に組み付けることが出来、外部回路基板と長期にわたり強固で安定な接続状態を維持出来る半導体素子収納用パッケージを提供するにある。 The inventors of the present invention have made various studies on methods for reducing the thermal stress generated in the connection terminals due to the difference in thermal expansion between a wiring board such as a package and an external circuit board. It has been found that a stiffener or a heat radiation lid plate having a low thermal expansion coefficient can be assembled to a wiring board without hindering the mounting, and stable mounting can be achieved over a long period of time, and the present invention has been completed based on this knowledge.
Accordingly, an object of the present invention is to assemble a stiffener or a heat dissipation lid plate with a low thermal expansion coefficient without disturbing the mounting of a semiconductor element, and maintain a strong and stable connection state with an external circuit board for a long time. It is in providing the package for semiconductor element accommodation.

本発明によれば、配線基板と、該配線基板の一方の表面に形成された半導体素子搭載部と、該半導体素子搭載部の周囲にフレーム状に配設された補強枠と、該補強枠に接合され、半導体素子を気密に封止するために前記配線基板表面に接合された放熱蓋と、を具備する半導体素子収納用パッケージであって、前記補強枠が、少なくとも２枚の枠板を重畳させた構造からなることを特徴とする半導体素子収納用パッケージ。が提供される。   According to the present invention, a wiring board, a semiconductor element mounting portion formed on one surface of the wiring board, a reinforcing frame disposed in a frame shape around the semiconductor element mounting portion, and the reinforcing frame A package for housing semiconductor elements, comprising: a heat dissipation lid bonded to the surface of the wiring board for hermetically sealing the semiconductor elements, wherein the reinforcing frame overlaps at least two frame plates A package for housing a semiconductor element, characterized in that it has the structure described above. Is provided.

即ち、本発明は、フレーム状スティフナ（補強枠）が蓋板と基板の間に挿入固定されている半導体素子収納用のパッケージであって、該スティフナが複数枚の枠板の重畳により構成される点が特徴である。
これにより温度変化時の基板の反り変形を半導体素子の実装を阻害することが無い程度に低減すると共にハンダバンプと配線基板面回路との接続部等のハンダ接合部に生じる熱応力を分散低減させることが出来、且つ、配線基板を補強出来るため、半導体素子の長期にわたる安定した実装が達成できる。 That is, the present invention is a package for housing a semiconductor element in which a frame-like stiffener (reinforcing frame) is inserted and fixed between a lid plate and a substrate, and the stiffener is configured by overlapping a plurality of frame plates. The point is a feature.
This reduces the warping deformation of the substrate when the temperature changes to such an extent that it does not hinder the mounting of the semiconductor element, and also disperses and reduces the thermal stress generated at the solder joints such as the connection part between the solder bump and the circuit board surface circuit. Since the wiring board can be reinforced, stable mounting of the semiconductor element over a long period of time can be achieved.

又、補強枠が２枚の枠板の重畳構造からなり、その配線基板側の枠板の熱膨張係数が、放熱蓋板側の枠板の熱膨張係数よりも大きい態様が好ましく、特に、配線基板側の枠板が、配線基板を構成する材料の熱膨張係数に近似した大きさの熱膨張係数を有する材料を用いて形成されていることが好ましい。
特に、前記配線基板側の枠板は銅を主成分とする材料からなることが好ましい。 In addition, it is preferable that the reinforcing frame has a superposed structure of two frame plates, and the thermal expansion coefficient of the frame plate on the wiring board side is larger than the thermal expansion coefficient of the frame plate on the radiation cover plate side. It is preferable that the board-side frame plate is formed using a material having a thermal expansion coefficient having a magnitude approximate to that of the material constituting the wiring board.
In particular, the frame board on the wiring board side is preferably made of a material mainly composed of copper.

又、上記態様の場合、その放熱蓋板側の枠板はＮｉ−Ｃｏ−Ｆｅ合金（Ｋｏｖａｒ合金等）、Ｃｕ−Ｍｏ合金及びＡｌ−ＳｉＣ複合材からなる群から選択された何れかを主体とする低熱膨張複合材料から形成されていることが好ましい。
又、更に、前記補強枠に於ける放熱蓋板側の枠板の主構成材が樹脂である態様のものは、熱膨張係数は比較的大きいが、弾性率が著しく低く熱応力歪みを効果的に吸収できるため好ましい。 Moreover, in the case of the said aspect, the frame board by the side of the radiation | emission cover board mainly has either selected from the group which consists of a Ni-Co-Fe alloy (Kovar alloy etc.), a Cu-Mo alloy, and an Al-SiC composite material. It is preferably formed from a low thermal expansion composite material.
Further, in the aspect in which the main component of the frame on the side of the radiating lid plate in the reinforcing frame is a resin, the thermal expansion coefficient is relatively large, but the elastic modulus is remarkably low and the thermal stress strain is effective. It is preferable because it can be absorbed.

又、前記放熱蓋板と前記補強枠とが該枠面の４辺中央部のみで接着されている態様のものは比較的熱応力歪みが集中し勝ちなコーナー部がフリーであるためこの部分の過度の応力集中を緩和できる点で好ましい。
更に、配線基板の主構成材料が、熱膨張係数１５乃至１８ｐｐｍ／℃の有機樹脂であることが配線金属材との熱膨張係数値の整合の観点から好ましい。 Further, in the aspect in which the radiating cover plate and the reinforcing frame are bonded only at the center of the four sides of the frame surface, the corner portion where thermal stress distortion tends to concentrate is free, so this portion This is preferable in that excessive stress concentration can be reduced.
Further, the main constituent material of the wiring board is preferably an organic resin having a thermal expansion coefficient of 15 to 18 ppm / ° C. from the viewpoint of matching the thermal expansion coefficient value with the wiring metal material.

本発明の半導体素子収納用パッケージは、プリント基板等の外部回路基板に実装した場合でも半導体素子とパッケージとの熱膨張係数の差に起因して生じるハンダバンプへの応力歪みを低減することが出来、長期間にわたり正確、且つ強固な電気的接続を持続することが可能となる。   The package for housing a semiconductor element of the present invention can reduce the stress strain to the solder bump caused by the difference in thermal expansion coefficient between the semiconductor element and the package even when mounted on an external circuit board such as a printed circuit board, It is possible to maintain an accurate and strong electrical connection for a long time.

以下に、本発明の実施の形態について図面を参照して更に詳細且つ具体的に説明する。
図１は、本発明に於いて好適な半導体素子収納用パッケージの一実施例の断面構造を示す略図であり、図２は、図１で示されるパッケージに於いて放熱蓋板を除去した状態での上面図である。 Hereinafter, embodiments of the present invention will be described in more detail and specifically with reference to the drawings.
FIG. 1 is a schematic view showing a cross-sectional structure of an embodiment of a package for housing a semiconductor element suitable for the present invention, and FIG. 2 is a state in which a heat dissipation cover plate is removed from the package shown in FIG. FIG.

この図１、図２を参照して、両図で示した態様のパッケージは、ＢＧＡタイプのフリップチップパッケージであり、単結晶シリコン等を主構成材とするシリコンチップ等の半導体素子１，ガラス繊維にエポキシ樹脂やポリイミド樹脂等を含浸させた繊維強化樹脂基板、紙・フェノール樹脂基板、ポリエステルフレキシブル基板、ポリイミドフレキシブル基板等からなる配線基板２、高熱伝導材料からなる放熱蓋板３、後に詳述する材料からなる補強枠（ステフナ）４及び絶縁性熱硬化性樹脂からなる充填材（アンダ−フィル）５、ハンダバンプ６等より構成される。   Referring to FIGS. 1 and 2, the package of the embodiment shown in both figures is a BGA type flip chip package, a semiconductor element such as a silicon chip mainly composed of single crystal silicon or the like, glass fiber A fiber reinforced resin substrate impregnated with epoxy resin or polyimide resin, a paper / phenolic resin substrate, a polyester flexible substrate, a wiring substrate 2 made of a polyimide flexible substrate, etc., a heat radiation cover plate 3 made of a highly heat conductive material, and will be described in detail later It is composed of a reinforcing frame (stiffener) 4 made of material, a filler (underfill) 5 made of insulating thermosetting resin, solder bumps 6 and the like.

シリコンを主構成材とする半導体素子１はその底面に複数のハンダバンプ６が形成されており、このハンダバンプ６を配線基板２の上面に形成された接続パターン（図示せず）にハンダ溶融によるフリップチップ接続することにより半導体素子１は配線基板２に搭載される（一次搭載）。
この時ハンダバンプ６は例えば、鉛を９０％以上含有する比較的高融点のハンダ材質とすることで、実装基板（外部回路プリント基板等）へ搭載（二次搭載）する際の加熱などでの再溶融を防止できる。 A plurality of solder bumps 6 are formed on the bottom surface of the semiconductor element 1 having silicon as a main component, and a flip chip is formed by melting the solder bumps 6 on a connection pattern (not shown) formed on the upper surface of the wiring board 2. By connecting, the semiconductor element 1 is mounted on the wiring board 2 (primary mounting).
At this time, the solder bump 6 is made of, for example, a solder material having a relatively high melting point containing 90% or more of lead, so that the solder bump 6 can be reused by heating when mounted (secondary mounting) on a mounting board (external circuit printed circuit board). Melting can be prevented.

又、配線基板２の上面には前述した半導体１に形成されたハンダバンプ６が接合される接続パターンが形成されると共に、その裏面には接続パッドが形成され、外部接続端子となるハンダボール７が配設されている。
ハンダボール７はハンダバンプ６より低融点の材料、例えば、錫ー鉛ハンダ合金を用いる。
又、配線基板２上面に形成された接続パターンと配線基板２下面に形成されたハンダボール７の接合部とは、配線基板２の内部に配設されたスルーホール（図示せず）により電気的に接続された構成となっている。 In addition, a connection pattern is formed on the upper surface of the wiring board 2 to which the solder bumps 6 formed on the semiconductor 1 described above are bonded, and a connection pad is formed on the back surface of the connection pattern, and solder balls 7 serving as external connection terminals are formed. It is arranged.
The solder ball 7 is made of a material having a melting point lower than that of the solder bump 6, for example, a tin-lead solder alloy.
Further, the connection pattern formed on the upper surface of the wiring board 2 and the joint portion of the solder ball 7 formed on the lower surface of the wiring board 2 are electrically connected by a through hole (not shown) disposed in the wiring board 2. It is the composition connected to.

次に、放熱蓋板３は、銅やアルミニウムを主成分とする熱伝導性の高い材料により形成されている。
放熱蓋板３は半導体素子１の上部に位置しており、半導体素子１の全面を覆いスティフナ４ｂと接着されていると共に、半導体素子１との間にはペースト材８が介装された構成となっている。
このペースト材８は放熱蓋板３と半導体素子１とを熱的に且つ機械的に接続させる機能を有するものであり、銀（Ａｇ）等の金属フィラー入り樹脂ペースト、シリコン（Ｓｉ）等の非金属フィラー入り樹脂ペースト、又はハンダ等のロウ材を用いることで熱伝導性と機械的保全性の両機能の両立が可能である。 Next, the radiating lid plate 3 is formed of a material having high thermal conductivity mainly composed of copper or aluminum.
The heat radiating cover plate 3 is located above the semiconductor element 1, covers the entire surface of the semiconductor element 1, is bonded to the stiffener 4 b, and has a configuration in which a paste material 8 is interposed between the semiconductor element 1. It has become.
This paste material 8 has a function of thermally and mechanically connecting the heat dissipation lid plate 3 and the semiconductor element 1, and is made of a resin filler containing a metal filler such as silver (Ag), non-silicon (Si) or the like. By using a metal filler-containing resin paste or soldering material such as solder, it is possible to achieve both functions of thermal conductivity and mechanical integrity.

アンダーフィル（充填材）５は例えばエポキシ樹脂等の熱硬化性樹脂であり、このアンダーフィル５により半導体素子１は封止され、ハンダバンプ６に加わる応力をより広い面積で受けることが可能となり、ハンダバンプ６に加わる応力の緩和が可能となる。   The underfill (filler) 5 is, for example, a thermosetting resin such as an epoxy resin, and the semiconductor element 1 is sealed by the underfill 5 and can receive stress applied to the solder bump 6 in a wider area. The stress applied to 6 can be relaxed.

スティフナ（補強枠）４は、その枠の内周側面が半導体素子１の外周側面に接近して配線基板２と放熱蓋板３の間に装着され、夫々と、例えば、エポキシ樹脂系接着剤、シリコーン樹脂系接着剤等の接着剤で接着固定することで配線基板２と放熱蓋板３の機械的安定性を補強する役目を有している。   The stiffener (reinforcing frame) 4 is mounted between the wiring board 2 and the heat dissipation lid plate 3 with the inner peripheral side surface of the frame approaching the outer peripheral side surface of the semiconductor element 1, and each includes, for example, an epoxy resin adhesive, It serves to reinforce the mechanical stability of the wiring board 2 and the heat dissipation lid 3 by being bonded and fixed with an adhesive such as a silicone resin adhesive.

本発明のパッケージに於いては、このスティフナ（補強枠）４が、少なくとも２枚の枠板を重畳させた構造からなることが特徴であるが、図３のパッケージではスティフナ４は、配線基板側と放熱蓋板側の２枚の枠板（４ａ，４ｂ）からなる。   In the package of the present invention, this stiffener (reinforcing frame) 4 has a structure in which at least two frame plates are superposed. In the package of FIG. 3, the stiffener 4 is on the wiring board side. And two frame plates (4a, 4b) on the side of the heat dissipation cover plate.

配線基板側の枠板４ａは、特に配線基板の反りを低減する重要な役割を担っており、材料としては配線基板と近似した範囲の熱膨張係数（例えば配線基板の熱膨張係数に対して±２×１０−６／℃）を有する材料を用いることが好ましい。
配線に主として銅（Ｃｕ）が用いられることから、本発明で用いる有機樹脂製配線基板は、その熱膨張係数が１５〜１８ｐｐｍ／℃の範囲にあるものを選択することが好まく、そのため、スティフナ枠板４ａの材質は銅（Ｃｕ）であることが好ましい。 The frame board 4a on the wiring board side plays an important role particularly to reduce the warping of the wiring board, and the material has a thermal expansion coefficient in a range approximate to the wiring board (for example, ±± It is preferable to use a material having 2 × 10 −6 / ° C.).
Since copper (Cu) is mainly used for the wiring, it is preferable to select the organic resin wiring board used in the present invention having a coefficient of thermal expansion in the range of 15 to 18 ppm / ° C. The material of the frame plate 4a is preferably copper (Cu).

放熱蓋板側の枠板４ｂは、配線基板２に前記枠板４ａを組み付けてからその枠板４ａ上に組み付けるが、放熱蓋板３に予め組み付けて於いても良い。
配線基板の反りは枠板４ａで抑制出来るので、スティフナー枠板４ｂには低熱膨張係数の材料を使用しても配線基板の反りは顕著ではなくなる。
それ故、熱膨張係数の低いＫｏｖａｒ（商標名）（２９％Ｎｉ−１７％Ｃｏ−５４％Ｆｅ：熱膨張係数９．６〜１０．２ｐｐｍ）、Ｃｕ−Ｍｏ（３０〜５０％Cu,70〜５０%Mo,熱膨張係数７．３〜１０ｐｐｍ）、或いはＡｌ−ＳｉＣ（Al３０〜５０％、SiC７０〜５０％、８〜１２ｐｐｍ）等の合金や複合材料を使用して良い。
又、一般にこれらの複合材料は高価であるため、厚さを薄くして銅製スティフナと併用できることはコスト上からも有利である。
上記枠板４ａと４ｂとの接着には、例えば、エポキシ樹脂系接着剤、シリコーン樹脂系接着剤等の接着剤が好適に用いられる。 The frame plate 4b on the side of the heat dissipating cover plate is assembled on the frame plate 4a after the frame plate 4a is assembled to the wiring board 2, but may be assembled to the heat dissipating cover plate 3 in advance.
Since the warping of the wiring board can be suppressed by the frame plate 4a, even if a material having a low thermal expansion coefficient is used for the stiffener frame plate 4b, the warping of the wiring board is not remarkable.
Therefore, Kovar (trade name) having a low coefficient of thermal expansion (29% Ni-17% Co-54% Fe: coefficient of thermal expansion 9.6 to 10.2 ppm), Cu-Mo (30 to 50% Cu, 70 to An alloy or a composite material such as 50% Mo, thermal expansion coefficient 7.3 to 10 ppm) or Al—SiC (Al 30 to 50%, SiC 70 to 50%, 8 to 12 ppm) may be used.
Moreover, since these composite materials are generally expensive, it is advantageous from the viewpoint of cost that the thickness can be reduced and used together with a copper stiffener.
For adhesion between the frame plates 4a and 4b, for example, an adhesive such as an epoxy resin adhesive or a silicone resin adhesive is suitably used.

一方、枠板４ｂ材として上記とは異なり熱膨張係数は大きいが、弾性率が著しく低い、シリコーン樹脂やエポキシ樹脂等の樹脂材料を用いることも効果的である。
上記のような樹脂製枠板は、放熱蓋板３に銅やアルミニウム等の熱膨張係数の高い材料を使用する際に緩衝材としての役割を果たし、スティフナー枠板４ａや配線基板２の変形を妨げない。
そのため、放熱蓋板３に銅やアルミニウム等の熱膨張係数の高い材料を使用しても熱応力を抑制できる。
この態様の枠体４ｂと前記配線基板側枠体４ａとの接着には、例えば、エポキシ樹脂、シリコーン樹脂等の接着剤が好適に用いられる。 On the other hand, it is also effective to use a resin material such as a silicone resin or an epoxy resin, which has a large thermal expansion coefficient, unlike the above, but has a remarkably low elastic modulus as the frame plate 4b material.
The resin frame plate as described above serves as a buffer material when a material having a high thermal expansion coefficient such as copper or aluminum is used for the heat radiating cover plate 3, and the deformation of the stiffener frame plate 4 a and the wiring substrate 2 is prevented. I do not disturb.
Therefore, thermal stress can be suppressed even when a material having a high thermal expansion coefficient such as copper or aluminum is used for the radiating cover plate 3.
For adhesion between the frame body 4b of this aspect and the wiring board side frame body 4a, for example, an adhesive such as epoxy resin or silicone resin is preferably used.

尚、スティフナー枠板４ｂと放熱蓋板３とは、既に述べたエポキシ樹脂等の接着剤により接合されるが、スティフナー４ｂの４辺中央部のみ接着し、比較的熱応力歪みが集中し勝ちなコーナー部をフリーとする接合態様は、この部分に対する過度の応力集中を緩和できる点で、配線基板の過度の変形を抑制できる観点から好ましい。   The stiffener frame plate 4b and the radiating cover plate 3 are joined by the adhesive such as epoxy resin already described. However, only the central part of the four sides of the stiffener 4b is bonded, and the thermal stress distortion tends to concentrate. The joining mode in which the corner portion is free is preferable from the viewpoint of suppressing excessive deformation of the wiring board in that excessive stress concentration on this portion can be relaxed.

本発明のスティフナ４に於いて、配線基板側枠板４ａと放熱蓋板側枠板４ｂの厚さ比は、枠板４ａ厚さ／枠板４ｂ厚さ＝１/４〜４/1の範囲、特に1/２〜２/１の範囲にあることが、応力歪みを有効性に分散させる観点から好ましい。   In the stiffener 4 of the present invention, the thickness ratio of the wiring board side frame plate 4a and the radiating lid plate side frame plate 4b is in the range of frame plate 4a thickness / frame plate 4b thickness = 1/4 to 4/1. In particular, it is preferably in the range of 1/2 to 2/1 from the viewpoint of effectively dispersing stress strain.

このように本発明の半導体素子収納用パッケージは、スティフナを２枚重ね構造とすることにより半導体素子の実装を阻害することなく熱膨張係数の小さいスティフナー（枠板４ｂ）や放熱蓋板を配線基板に組み付けることができ、長期にわたり安定した実装が可能である。   As described above, the package for housing a semiconductor element of the present invention has a stiffener (frame plate 4b) or a radiating cover plate having a low thermal expansion coefficient without hindering the mounting of the semiconductor element by using a two-layer stiffener structure. And can be mounted stably over a long period of time.

図１，２に示したＢＧＡタイプのフリップチップ接続構造のパッケージであって、下記部材仕様のものを用意した。
半導体素子１（シリコンチップ；１５×１５ｍｍ平方、厚さ０．７ｍｍ）
配線基板２（室温〜２５０℃の熱膨張係数；１８×１０−６／℃、ガラス繊維・エポキシ樹脂製；４０×４０ｍｍ平方、厚さ０．７ｍｍ、配線Ｃｕ）
放熱蓋板３（銅（Ｃｕ）製；４０×４０ｍｍ平方、厚さ０．５ｍｍ）
アンダーフィル５（エポキシ樹脂）
ハンダバンプ６（Ｐｂ含有率９０％の高融点ハンダ）
外部接続端子用ハンダボール７（錫（Ｓｎ）−鉛（Ｐｂ）低融点ハンダ）
ペースト材８（銀（Ａｇ）フィラー入り樹脂ペースト）
尚、スティフナ４は、サイズが外形４０×４０ｍｍ平方、開口部２６×２６ｍｍ平方で、１枚のスティフナからなる試料Ｎｏ．１の比較例品では厚さ０．７ｍｍの銅製、２枚のスティフナからなるＮｏ．２〜６の実施例品では、配線基板側スティフナ枠板４ａは何れも厚さ０．３ｍｍの銅製、放熱蓋板側スティフナ枠板４ｂは厚さ０．３ｍｍで夫々表１に記載の各材料を用いた。また、ステフィナの熱膨張係数は、それぞれ、Ｃｕ：１８×１０−６／℃、Ａｌ：２３×１０−６／℃、エポキシ樹脂：６０×１０−６／℃である。 The BGA type flip-chip connection structure package shown in FIGS. 1 and 2 having the following member specifications was prepared.
Semiconductor element 1 (silicon chip; 15 × 15 mm square, thickness 0.7 mm)
Wiring board 2 (thermal expansion coefficient from room temperature to 250 ° C .; 18 × 10 −6 / ° C., glass fiber / epoxy resin; 40 × 40 mm square, thickness 0.7 mm, wiring Cu)
Radiation cover plate 3 (made of copper (Cu); 40 × 40 mm square, thickness 0.5 mm)
Underfill 5 (epoxy resin)
Solder bump 6 (Pb content 90% high melting point solder)
Solder balls 7 for external connection terminals (tin (Sn) -lead (Pb) low melting point solder)
Paste material 8 (resin paste containing silver (Ag) filler)
The stiffener 4 has an outer size of 40 × 40 mm square and an opening of 26 × 26 mm square. No. 1 made of copper having a thickness of 0.7 mm and No. 2 consisting of two stiffeners were used as comparative examples. In Examples 2 to 6, the wiring board side stiffener frame plate 4a is made of copper with a thickness of 0.3 mm, and the heat dissipation lid plate side stiffener frame plate 4b is 0.3 mm with a thickness of each material shown in Table 1. Was used. The thermal expansion coefficients of Stefina are Cu: 18 × 10 −6 / ° C., Al: 23 × 10 −6 / ° C., and epoxy resin: 60 × 10 −6 / ° C., respectively.

上記の半導体素子収納パッケージを夫々厚さ１．６ｍｍのＦＲ−４グレードプリント基板（耐燃性ガラス布基材エポキシ樹脂銅張積層板）にハンダ実装して信頼性試験の寿命サイクル数を比較した。
信頼性試験は、大気雰囲気にて−４０℃と１２５℃の各温度に制御した恒温槽に試験サンプルを２５分／２５分の保持を１サイクルとして最高３５００サイクル繰り返した。
そして、各１００サイクル毎にプリント基板の配線導体とパッケージ配線基板との電気抵抗を測定し、電気抵抗に変化が現れるまでのサイクル数を計数した。
結果を表１に示した。 The above semiconductor element storage packages were solder mounted on 1.6 mm thick FR-4 grade printed circuit boards (flame-resistant glass cloth base epoxy resin copper-clad laminates), and the life cycle numbers of the reliability test were compared.
The reliability test was repeated for a maximum of 3500 cycles, with a test sample held at 25 minutes / 25 minutes in a thermostat controlled at −40 ° C. and 125 ° C. in an air atmosphere as one cycle.
And the electrical resistance of the wiring conductor of a printed circuit board and a package wiring board was measured every 100 cycles, and the number of cycles until a change appeared in the electrical resistance was counted.
The results are shown in Table 1.

表１より明らかなように、本発明品パッケージは、何れのものも３０００サイクル近くまで抵抗変化は全く認められず、極めて安定で良好な電気的接続状態を維持できた。
然し、本発明品以外の比較例品（試料Ｎｏ．１）では２０００サイクルから抵抗変化が検出され、実装後の信頼性に欠けることが判る。 As can be seen from Table 1, in any of the packages of the present invention, no resistance change was observed until nearly 3000 cycles, and an extremely stable and good electrical connection state could be maintained.
However, in the comparative product (sample No. 1) other than the product of the present invention, a change in resistance is detected from 2000 cycles, and it is understood that the reliability after mounting is lacking.

Figure 2005217003
Figure 2005217003

本発明の半導体素子収納パッケージの一好適実施例の構造を示す断面略図Schematic cross-sectional view showing the structure of a preferred embodiment of the semiconductor device storage package of the present invention. 図１のパッケージの上面略図（放熱蓋板を省略）1 is a schematic top view of the package of FIG. 1 (the heat dissipation cover is omitted). 従来の半導体素子収納パッケージの構造を示す断面略図。The cross-sectional schematic which shows the structure of the conventional semiconductor element storage package.

符号の説明Explanation of symbols

１、２１ 半導体素子
２、２２ 配線基板
３，２３ 放熱蓋板
４、２４ スティフナ（補強枠）
４ａ 放熱蓋板側枠板
４ｂ 配線基板側枠板
５、２５ アンダーフィル（充填材）
６、２６ ハンダバンプ
７，２７ ハンダボール（外部接続端子）
８、２８ ペースト材
９，２９ 接着剤 1,21 Semiconductor element 2,22 Wiring board 3,23 Radiation cover plate 4,24 Stiffener (reinforcement frame)
4a Radiation cover plate side frame plate 4b Wiring board side frame plate 5, 25 Underfill (filler)
6, 26 Solder bump 7, 27 Solder ball (external connection terminal)
8, 28 Paste material 9, 29 Adhesive

Claims (8)

配線基板と、該配線基板の一方の表面に形成された半導体素子搭載部と、該半導体素子搭載部の周囲にフレーム状に配設された補強枠と、該補強枠に接合され、半導体素子を気密に封止するために前記配線基板表面に接合された放熱蓋と、を具備する半導体素子収納用パッケージであって、
前記補強枠が、少なくとも２枚の枠板を重畳させた構造からなることを特徴とする半導体素子収納用パッケージ。 A wiring board; a semiconductor element mounting portion formed on one surface of the wiring board; a reinforcing frame disposed in a frame shape around the semiconductor element mounting portion; and a semiconductor element bonded to the reinforcing frame, A semiconductor element storage package comprising a heat dissipation lid bonded to the surface of the wiring board for hermetically sealing,
A package for housing a semiconductor element, wherein the reinforcing frame has a structure in which at least two frame plates are superposed. 前記補強枠が２枚の枠板の重畳構造からなり、その配線基板側の枠板の熱膨張係数が、放熱蓋板側の枠板の熱膨張係数よりも大きいことを特徴とする請求項１記載の半導体素子収納用パッケージ。   2. The reinforcing frame is formed by a superposition structure of two frame plates, and the thermal expansion coefficient of the frame plate on the wiring board side is larger than the thermal expansion coefficient of the frame plate on the radiation cover plate side. A package for housing a semiconductor element as described. 前記配線基板側の枠板が、配線基板を構成する材料の熱膨張係数と近似した大きさの熱膨張係数を有する材料を用いて形成されていることを特徴とする請求項２に記載の半導体素子収納用パッケージ。   3. The semiconductor according to claim 2, wherein the frame board on the wiring board side is formed using a material having a thermal expansion coefficient approximately equal to a thermal expansion coefficient of a material constituting the wiring board. Package for element storage. 前記配線基板側の枠板が、銅を主成分とする材料からなることを特徴とする請求項１乃至３の何れかに記載の半導体素子収納用パッケージ。   4. The package for housing a semiconductor element according to claim 1, wherein the frame board on the wiring board side is made of a material mainly composed of copper. 前記補強枠が２枚の枠板の重畳構造からなり、その放熱蓋板側の枠板がＮｉ−Ｃｏ−Ｆｅ、Ｃｕ−Ｍｏ及びＡｌ−ＳｉＣからなる群から選択された何れかを主体とする材料から形成されるていることを特徴とする請求項１乃至４の何れかに記載の半導体素子収納用パッケージ。   The reinforcing frame has a superposed structure of two frame plates, and the frame plate on the side of the radiating lid plate is mainly selected from the group consisting of Ni—Co—Fe, Cu—Mo and Al—SiC. 5. The package for housing a semiconductor element according to claim 1, wherein the package is made of a material. 前記補強枠が２枚の枠板の重畳構造からなり、その放熱蓋板側の枠板の主構成材が樹脂であることを特徴とする請求項１記載の半導体素子収納用パッケージ。   2. The package for housing a semiconductor element according to claim 1, wherein the reinforcing frame has a superposed structure of two frame plates, and a main constituent material of the frame plate on the side of the heat dissipation lid plate is a resin. 前記放熱蓋板と前記補強枠とが該枠面の４辺中央部のみで接着されている請求項１乃至６の何れかに記載の半導体素子収納用パッケージ。   The package for housing a semiconductor element according to any one of claims 1 to 6, wherein the radiating cover plate and the reinforcing frame are bonded only at the center of the four sides of the frame surface. 前記配線基板の主構成材料が、熱膨張係数１５乃至１８ｐｐｍ／℃の有機樹脂である請求項１乃至８の何れかに記載の半導体素子収納用パッケージ。   The package for housing a semiconductor element according to any one of claims 1 to 8, wherein a main constituent material of the wiring board is an organic resin having a thermal expansion coefficient of 15 to 18 ppm / ° C.
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