JPH1117064A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH1117064A
JPH1117064A JP16757897A JP16757897A JPH1117064A JP H1117064 A JPH1117064 A JP H1117064A JP 16757897 A JP16757897 A JP 16757897A JP 16757897 A JP16757897 A JP 16757897A JP H1117064 A JPH1117064 A JP H1117064A
Authority
JP
Japan
Prior art keywords
resin
wiring board
mounting
plate
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP16757897A
Other languages
Japanese (ja)
Inventor
Ken Iwasaki
建 岩崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP16757897A priority Critical patent/JPH1117064A/en
Publication of JPH1117064A publication Critical patent/JPH1117064A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

PROBLEM TO BE SOLVED: To obtain a compact semiconductor package wherein the warp is reduced or avoided and a high reliability connection/mounting is possible, by laminating and integrating a wiring board and resin board composed of similar kinds of resin bases on both sides of a reinforcing board around a semiconductor element mounting/layout area. SOLUTION: A package comprises a wiring board 8 having a resin film as a base, connection terminals 8a on one main surface and outer connection terminals 8b led out and disposed on the other main surface, semiconductor elements 9 electrically connected and mounted corresponding to the terminals 8a, resin board 12 laminated around the elements 9 through an adhesive layer 11a on the surface of the wiring board, heat sink 13 integrated with the top surface of the elements 9 through the adhesive layer 11b and resin layer 14 sealing the connections and mounting parts of the elements 9. This dispersively absorbs and relaxes the thermal expansion coefficient of the reinforcing board influencing the warp, thereby reducing/suppressing the warp of the package.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体パッケージ
に係り、さらに詳しくは反りの発生などを低減・解消し
た半導体パッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which warpage is reduced or eliminated.

【0002】[0002]

【従来の技術】電子機器類の軽量化やコンパクト化など
に伴って、電子回路の高密度実装型の開発が進められて
いる。また、この高密度実装回路の構成に当たっては、
搭載・実装する電子部品、たとえば半導体パッケージの
小形・薄型化が望まれている。すなわち、実装回路装置
の高密度化や高機能化には、配線の高密度化だけでな
く、半導体素子(IC素子など)などの回路部品の高機能
・小形・薄型化を要するからである。
2. Description of the Related Art With the reduction in weight and size of electronic devices, development of high-density mounting of electronic circuits has been promoted. Also, in the configuration of this high-density mounting circuit,
There is a demand for smaller and thinner electronic components to be mounted and mounted, for example, semiconductor packages. That is, in order to increase the density and function of the mounted circuit device, it is necessary not only to increase the density of the wiring but also to increase the function, size and thickness of circuit components such as semiconductor elements (IC elements and the like).

【0003】このような要求に対応して、一主面に接続
端子が設けられ、他主面に外部接続端子が導出配置され
たポリイミド樹脂を基材とする配線基板を用いた BGA(B
allGride Array)タイプ、TBGA(Tape Ball Gride Array)
タイプ、あるいは LGA(Land Gride Array)タイプの半
導体パッケージが開発されている。
In response to such demands, a BGA (BGA) using a polyimide resin-based wiring board in which connection terminals are provided on one main surface and external connection terminals are led out and arranged on the other main surface.
allGride Array) type, TBGA (Tape Ball Gride Array)
Semiconductor packages of type LGA (Land Gride Array) have been developed.

【0004】図3は、TBGAタイプの半導体パッケージの
要部構造を断面的に示すもので、1は一主面に接続端子
1aが設けられ、他主面に外部接続端子1bが導出配置され
た樹脂を基材としたフィルム型(もしくはテープ型)の
配線基板である。ここで、配線基板1は、たとえば厚さ
50〜 100μm 程度、20×20mm〜40×40mm角程度のポリイ
ミド樹脂フィルム(もしくはテープ)であり、また、他
主面に導出された外部接続端子1bは、いわゆるボールバ
ンプで格子状に配置されている。
FIG. 3 is a sectional view showing the structure of a main part of a TBGA type semiconductor package.
This is a film-type (or tape-type) wiring board having a resin as a base material provided with an external connection terminal 1b on the other main surface and provided with a main surface 1a. Here, the wiring board 1 has a thickness of, for example,
It is a polyimide resin film (or tape) of about 50 to 100 μm, about 20 × 20 mm to 40 × 40 mm square, and the external connection terminals 1b led to the other main surface are arranged in a grid pattern by so-called ball bumps. I have.

【0005】2は前記配線基板1の接続端子1aに対応さ
せ電気的に接続・搭載された半導体素子、たとえばICチ
ップであり、3は前記半導体素子2周辺を囲繞し、配線
基板1面に接着剤層4aを介して積層された補強板、5は
前記補強板3に上面に対しては離隔し(間隙を持ち)、
半導体素子2の上面に接着剤層4bを介して一体的に配置
された放熱板、6は前記半導体素子2の接続・搭載部を
封止する樹脂層である。ここで、補強板3は、たとえば
厚さ 200〜 500μm 程度、20×20mm〜40×40mm角程度
で、前記半導体素子2の搭載・実装領域に対応する部分
を開口させた環状のステンレス鋼製板であり、接着剤層
4a,4bは、たとえばエポキシ樹脂やアクリル樹脂などの
熱硬化性もしくは熱可塑性の樹脂である。また、放熱板
5は、たとえば厚さ 200〜 500μm 程度、20×20mm〜40
×40mm角程度の銅板やステンレス鋼板などであり、さら
に、封止樹脂層6は、たとえばシリカ粉末を分散・含有
したエポキシ樹脂など、一般的に、半導体装置の構成で
使用されている封止用樹脂でる。 そして、このような
半導体パッケージは、たとえば半田ペーストを塗布(印
刷)した実装用配線基板7の導電パッド(図示省略)
に、前記ボールバンプ1bを対応・位置合わせマウント
し、半田ペーストをリフローさせて実装回路装置を形成
する形態で使用されている。
[0005] Reference numeral 2 denotes a semiconductor element, for example, an IC chip, which is electrically connected and mounted in correspondence with the connection terminal 1a of the wiring board 1, and 3 surrounds the periphery of the semiconductor element 2 and is adhered to the surface of the wiring board 1. The reinforcing plate 5 laminated through the agent layer 4a is separated from the upper surface of the reinforcing plate 3 (has a gap),
A radiator plate 6 is disposed integrally on the upper surface of the semiconductor element 2 with an adhesive layer 4b interposed therebetween. Reference numeral 6 denotes a resin layer for sealing the connection / mounting portion of the semiconductor element 2. Here, the reinforcing plate 3 is, for example, an annular stainless steel plate having a thickness of about 200 to 500 μm, a size of about 20 × 20 mm to 40 × 40 mm square, and an opening corresponding to the mounting / mounting area of the semiconductor element 2. And the adhesive layer
4a and 4b are thermosetting or thermoplastic resins such as epoxy resin and acrylic resin. The heat sink 5 has a thickness of, for example, about 200 to 500 μm,
The sealing resin layer 6 is, for example, an epoxy resin in which silica powder is dispersed and contained, such as a copper plate or a stainless steel plate having a size of about × 40 mm square. With resin. Such a semiconductor package has conductive pads (not shown) of the mounting wiring board 7 on which, for example, a solder paste is applied (printed).
Then, the ball bumps 1b are mounted in correspondence and position alignment, and the solder paste is reflowed to form a mounted circuit device.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、上記半
導体パッケージの場合は、次ぎのような不具合な問題が
ある。すなわち、 (a)ポリイミド樹脂を基材とするフィ
ルム(もしくはテープ)状の配線基板1、接着材層4a、
補強板3、さらには実装用配線基板7などの間に熱膨脹
率の差があること、 (b)ポリイミド樹脂などフィルム状
の配線基板用の基材が吸湿性を有することなどによっ
て、半導体パッケージの組み立て(もしくは製造)工程
における加熱、あるいは組み込んだ実装回路装置(電子
機器)が使用環境下で温度変化にあった場合など、半導
体パッケージに反りが生じる。
However, the above-described semiconductor package has the following problems. That is, (a) a film (or tape) -shaped wiring board 1 having a polyimide resin as a base material, an adhesive layer 4a,
There is a difference in the coefficient of thermal expansion between the reinforcing plate 3 and the wiring board 7 for mounting, and the like. (B) The base material of the film-shaped wiring board such as a polyimide resin has a hygroscopic property. The semiconductor package is warped due to, for example, heating in an assembly (or manufacturing) process, or a change in temperature of a mounted circuit device (electronic device) incorporated in a use environment.

【0007】この点をより具体的に例示・説明すると、
たとえば40×40mm角のポリイミド樹脂を基材とするフィ
ルム状配線基板1を使用したTBGAタイプの半導体パッケ
ージにおいては、フィルム状配線基板1の吸排湿に起因
する反りが約44μm 、厚さ 350μm の補強板3の打ち抜
き加工時に発生した反り約70μm 、および熱変形による
反りとによって、 100μm を超える反りが生じる。
[0007] This point will be more specifically illustrated and described.
For example, in a TBGA type semiconductor package using a film-shaped wiring board 1 made of a 40 × 40 mm square polyimide resin as a base material, the film-shaped wiring board 1 has a warp caused by moisture absorption and discharge of about 44 μm and a thickness of 350 μm. The warpage of more than 100 μm is caused by the warpage of about 70 μm generated at the time of punching the plate 3 and the warpage due to thermal deformation.

【0008】そして、この半導体パッケージの反り発生
は、実装用配線基板7面に対する実装工程での不良率増
大を招来することになり、また、使用環境下での反り発
生は、半田接合部に対する応力集中・歪みの発生による
接合部の離脱を招来し、長期信頼性が損なわれる恐れが
ある。
The warpage of the semiconductor package causes an increase in the defect rate in the mounting process on the surface of the mounting wiring board 7, and the warpage under the use environment is caused by the stress on the solder joint. Concentration / distortion may cause the detachment of the joint, which may impair long-term reliability.

【0009】前記反りの発生対策として、補強板3を厚
くして反りを低減する試みも成されているが、高容量化
に伴う半導体素子(半導体チップ)の大形化、換言する
と半導体パッケージの大形化に対応できない状況にあ
る。すなわち、補強板3の厚さを 400〜1000μm 程度
と、従来の 2倍程度に厚くしても、実用性を考慮した場
合、半導体パッケージの反りを規格の範囲内に抑えるこ
とが困難である。しかも、補強板3を厚くすると剛性が
増加し、その剛性の影響によって半田接合部に対する応
力集中・歪みの発生が助長され、接合の信頼性が低下す
るという問題がある。 本発明は上記事情に対処してな
されたもので、コンパクトで、かつ反りの発生が低減・
防止され、信頼性の高い接続・実装が可能な半導体パッ
ケージの提供を目的とする。
As a countermeasure against the warpage, attempts have been made to reduce the warp by increasing the thickness of the reinforcing plate 3. However, the size of the semiconductor element (semiconductor chip) is increased due to the increase in capacity, in other words, the size of the semiconductor package is reduced. It is in a situation where it cannot cope with enlargement. That is, even if the thickness of the reinforcing plate 3 is about 400 to 1000 μm, which is about twice as large as that of the related art, it is difficult to suppress the warpage of the semiconductor package within the standard range in consideration of practicality. In addition, when the reinforcing plate 3 is made thicker, the rigidity increases, and the effect of the rigidity promotes stress concentration and distortion at the soldered joints, thereby deteriorating the joint reliability. The present invention has been made in view of the above circumstances, and is compact and reduces the occurrence of warpage.
It is an object of the present invention to provide a semiconductor package that can be prevented from being connected and mounted with high reliability.

【0010】[0010]

【課題を解決するための手段】請求項1の発明は、一主
面に接続端子が設けられ、他主面に外部接続端子が導出
配置された樹脂を基材としたフィルム状の配線基板と、
前記配線基板の接続端子に対応させ電気的に接続・搭載
された半導体素子と、前記半導体素子周辺を囲繞し、か
つ配線基板面に接着剤層を介して順次積層された補強板
および前記配線基板の基材と同種の樹脂板と、前記樹脂
板上面との間に間隙を持たせ、かつ半導体素子上面に接
着剤層を介して一体的に配置された放熱板とを具備する
ことを特徴とする半導体パッケージである。
According to a first aspect of the present invention, there is provided a film-shaped wiring board made of resin and having a connection terminal provided on one main surface and an external connection terminal led out on the other main surface. ,
A semiconductor element electrically connected and mounted in correspondence with a connection terminal of the wiring board, a reinforcing plate surrounding the periphery of the semiconductor element, and sequentially laminated on a wiring board surface via an adhesive layer, and the wiring board A base plate and a resin plate of the same type, and a heat sink provided with a gap between the upper surface of the resin plate and integrally disposed on the upper surface of the semiconductor element via an adhesive layer. Semiconductor package.

【0011】請求項2の発明は、請求項1記載の半導体
パッケージにおいて、樹脂フィルムが、ポリイミド樹脂
製であることを特徴とする。
According to a second aspect of the present invention, in the semiconductor package according to the first aspect, the resin film is made of a polyimide resin.

【0012】上記請求項1および2の発明では、同種の
樹脂板で補強板の両主面を挟着させ、対称的な構成とし
たことにより、温度変化や湿度の影響で反りを発生し易
い補強板の膨脹作用などが、両主面側に分散的に及ぶこ
とになって、厚さ方向に発生する反り現象が容易に、防
止・低減化される。そして、本願発明は、構成素材の積
層断面を対称に設計・構成したとき、それら積層素材の
熱膨脹率差や吸湿性差に起因する積層方向(厚さ方向)
における積層体の反り発生が効果的に抑えられ、良好な
平坦性を保持することに着目してなされたものである。
According to the first and second aspects of the present invention, the two main surfaces of the reinforcing plate are sandwiched by the same type of resin plate to form a symmetrical structure, so that warpage is easily caused by the influence of temperature change and humidity. The expansion effect of the reinforcing plate and the like spreads over both main surfaces in a distributed manner, so that the warping phenomenon occurring in the thickness direction can be easily prevented and reduced. In the present invention, when the laminated cross sections of the constituent materials are designed and configured symmetrically, the laminating direction (thickness direction) caused by the difference in thermal expansion coefficient and the difference in hygroscopicity of the laminated materials.
In this case, the generation of warpage of the laminated body is effectively suppressed and attention is paid to maintaining good flatness.

【0013】[0013]

【発明の実施の形態】本発明において、補強板を接着剤
層を介して挟着する樹脂製のフィルム状(ないしテープ
状)配線基板および樹脂板は、たとえばポリイミド樹
脂、ポリブチレンテレフタレート樹脂などを基材とした
配線基板および樹脂板である。そして、その厚さは、ほ
ぼ同等であることがま望ましく、一般的に、50〜 200μ
m 程度で、コストおよび加工性などを考慮した場合、ポ
リイミド樹脂を基材としたものが好ましい。また、他主
面に導出・配置された外部接続端子は、一般的に、ラン
ド型もしくはボール型で、かつ所定ピッチの格子状や千
鳥状など任意に配列されている。つまり、 BGA(Ball Gr
ide Array)タイプ、TBGA(Tape Ball Gride Array)タイ
プ、 LGA(Land Gride Array)タイプ、TLGA(Tape Land G
ride Array) タイプの半導体パッケージが対象となる。
なお、前記外部接続端子は、たとえば金,銀,ニッケ
ル,アルミニウム,錫,半田類などで形成される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a resin film-shaped (or tape-shaped) wiring board and a resin plate which sandwich a reinforcing plate via an adhesive layer are made of, for example, polyimide resin, polybutylene terephthalate resin, or the like. A wiring board and a resin plate as base materials. And, it is desirable that the thickness is almost the same, and generally 50 to 200 μm.
In consideration of cost, workability, and the like, it is preferable to use a polyimide resin as a base material. In addition, the external connection terminals led out and arranged on the other main surface are generally land-shaped or ball-shaped, and are arranged arbitrarily, such as in a lattice or staggered pattern at a predetermined pitch. In other words, BGA (Ball Gr
ide Array), TBGA (Tape Ball Grid Array), LGA (Land Grid Array), TLGA (Tape Land G)
ride Array) type semiconductor package.
The external connection terminal is formed of, for example, gold, silver, nickel, aluminum, tin, solder, or the like.

【0014】本発明において、前記樹脂製のフィルム状
配線基板に搭載する半導体素子は、たとえばICチップな
ど、チップ型のものであれば特に限定されない。また、
その配線基板面に搭載された半導体素子数は、一般的に
は1個であるが複数個であってもよいし、他の受動素子
なども搭載した構成を採ってもよい。
In the present invention, the semiconductor element to be mounted on the resin film wiring board is not particularly limited as long as it is of a chip type such as an IC chip. Also,
The number of semiconductor elements mounted on the wiring board surface is generally one, but may be plural, or may adopt a configuration in which other passive elements are mounted.

【0015】本発明において、補強板は、たとえば厚さ
200〜 500μm 程度のステンレス鋼板や銅板などであ
り、また、この補強板を樹脂製のフィルム状配線基板面
に貼着・一体化などする接着剤としては、たとえばエポ
キシ樹脂系もしくはアクリル樹脂系などが挙げられる。
なお、貼着・一体化に寄与する接着剤層の厚さは、特に
限定されないが、少なくとも補強板の両面側の厚さをほ
ぼ等しく、また、厚さムラのないように設定することが
好ましい。
In the present invention, the reinforcing plate has a thickness of, for example,
A stainless steel plate or copper plate with a thickness of about 200 to 500 μm is used.As an adhesive for attaching and integrating the reinforcing plate to the surface of a resin film wiring board, for example, epoxy resin or acrylic resin is used. No.
The thickness of the adhesive layer that contributes to the attachment and integration is not particularly limited, but it is preferable that at least the thickness of both sides of the reinforcing plate is substantially equal, and that the thickness is set so as to have no thickness unevenness. .

【0016】本発明においては、通常、半導体素子の実
装・接続部を樹脂封止するが、一般的に、半導体素子の
封止に使用されている封止用樹脂ならばいずれをも使用
できる。すなわち、半導体素子を外界雰囲気中の水分や
不純物成分などに対して、あるいは機械的に保護するた
めに、被覆封止する樹脂のモールド材ならばいずれも使
用できる。たとえば精製処理したエポキシ樹脂に、Na成
分などを精製除去したシリカ粉末などをフィラーとして
含む封止用のエポキシ樹脂系組成物、あるいはポリスル
フォン酸樹脂などでモールド樹脂層を形成できる。
In the present invention, the mounting and connecting portions of the semiconductor element are usually sealed with a resin, but any sealing resin generally used for sealing a semiconductor element can be used. That is, any resin molding material that covers and seals the semiconductor element can be used in order to protect the semiconductor element against moisture and impurity components in the external atmosphere or mechanically. For example, a mold resin layer can be formed from an epoxy resin composition for encapsulation containing, as a filler, silica powder from which a Na component or the like has been purified and removed from a purified epoxy resin, or a polysulfonic acid resin.

【0017】本発明において、放熱板は、たとえば厚さ
200〜 500μm ( 0.2〜 0.5mm)程度のステンレス鋼板
や銅板などであり、半導体素子の動作による発熱の放出
を目的として配置される。したがって、外界への放熱
を、より効果的に行うために、補強板上に積層・一体化
される樹脂板上面に対しても、適宜の間隙を採る。
In the present invention, the radiator plate has a thickness of, for example,
It is a stainless steel plate or copper plate of about 200 to 500 μm (0.2 to 0.5 mm), and is arranged to release heat generated by the operation of the semiconductor element. Therefore, in order to more effectively dissipate heat to the outside, an appropriate gap is also provided for the upper surface of the resin plate laminated and integrated on the reinforcing plate.

【0018】次に、図1および図2を参照して具体例を
説明する。
Next, a specific example will be described with reference to FIGS.

【0019】図1はTBGAタイプの半導体パッケージの要
部構造を示す断面図である。図1において、8は一主面
に接続端子8aが設けられ、他主面に外部接続端子8bが導
出配置された樹脂フィルムを基材とした配線基板であ
る。ここで、配線基板8は、たとえば厚さ50〜 100μm
程度、40×40mm角のポリイミド樹脂製のフィルム(もし
くはテープ)状配線基板であり、また、他主面に導出さ
れた外部接続端子8bは、いわゆる金製のボールバンプで
格子状に配置されている。
FIG. 1 is a sectional view showing the structure of a main part of a TBGA type semiconductor package. In FIG. 1, reference numeral 8 denotes a wiring board made of a resin film having a connection terminal 8a provided on one main surface and an external connection terminal 8b led out on the other main surface. Here, the wiring board 8 has a thickness of, for example, 50 to 100 μm.
It is a film (or tape) -like wiring board made of polyimide resin of about 40 x 40 mm square, and the external connection terminals 8b led out to the other main surface are arranged in a grid pattern by so-called gold ball bumps. I have.

【0020】9は前記配線基板8の接続端子8aに対応さ
せ電気的に接続・搭載された半導体素子、たとえばICチ
ップであり、10は前記半導体素子2周辺を囲繞し、配線
基板8面に接着剤層 11aを介して積層された補強板、12
は前記補強板10の上面に接着剤層 11aを介して積層され
た樹脂板、13は前記樹脂板12に対しては離隔し(間隙を
持ち)、半導体素子9の上面に接着剤層 11bを介して一
体的に配置された放熱板、14は前記半導体素子9の接続
・搭載部を封止する樹脂層である。ここで、補強板10
は、たとえば厚さ 350μm 程度、40×40mm角程度で、前
記半導体素子9の搭載・実装領域に対応する部分を開口
させた環状のステンレス鋼製板であり、接着剤層 11a,
11bは、たとえばエポキシ樹脂やアクリル樹脂などの樹
脂である。また、樹脂板12は、厚さが50〜 200μm (0.
05〜 0.2mm)程度で、補強板10と同様の形状に形成され
たポリイミド樹脂板であり、放熱板13は、たとえば厚さ
200〜 500μm ( 0.2〜 0.5mm)程度、20×20mm〜40×
40mm角程度のステンレス鋼板や銅板などである。さら
に、封止樹脂層6は、たとえばシリカ粉末を分散・含有
したエポキシ樹脂など、一般的に、半導体装置の構成で
使用されている封止用樹脂である。
Reference numeral 9 denotes a semiconductor element, for example, an IC chip, which is electrically connected and mounted in correspondence with the connection terminal 8a of the wiring board 8, and 10 surrounds the periphery of the semiconductor element 2 and is adhered to the surface of the wiring board 8. Reinforcing plates laminated via the agent layer 11a, 12
Is a resin plate laminated on the upper surface of the reinforcing plate 10 via an adhesive layer 11a, 13 is separated from the resin plate 12 (has a gap), and an adhesive layer 11b is formed on the upper surface of the semiconductor element 9. A radiator plate 14 is disposed integrally with the resin element, and is a resin layer for sealing the connection / mounting portion of the semiconductor element 9. Here, reinforcing plate 10
Is an annular stainless steel plate having a thickness of, for example, about 350 μm and a size of about 40 × 40 mm square, and having an opening at a portion corresponding to the mounting / mounting area of the semiconductor element 9.
11b is a resin such as an epoxy resin or an acrylic resin. The resin plate 12 has a thickness of 50 to 200 μm (0.
05 to 0.2 mm), and is a polyimide resin plate formed in the same shape as the reinforcing plate 10.
About 200 ~ 500μm (0.2 ~ 0.5mm), 20x20mm ~ 40x
It is a stainless steel plate or copper plate of about 40 mm square. Furthermore, the sealing resin layer 6 is a sealing resin generally used in the configuration of a semiconductor device, such as an epoxy resin in which silica powder is dispersed and contained.

【0021】上記構成のTBGAタイプの半導体パッケージ
は、フィルム状配線基板8の吸排湿および補強板などの
熱変形に起因する反りがほとんどなくなり、補強板10の
打ち抜き加工時に発生した反りのみに抑制・低減化す
る。上記反りの発生を抑制・低減化できることは、補強
板10の厚さを薄くできることになる。したがって、補強
板10の剛性に起因する半導体パッケージのボールバンプ
8bを半田付け・接合した接続部における応力集中の回避
となり、半田付け・接合の信頼性向上を助長することに
なる。
In the TBGA type semiconductor package having the above structure, the warpage caused by the moisture absorption and discharge of the film-like wiring board 8 and the thermal deformation of the reinforcing plate is almost eliminated, and only the warpage generated at the time of punching the reinforcing plate 10 is suppressed. Reduce. The ability to suppress and reduce the occurrence of the warpage means that the thickness of the reinforcing plate 10 can be reduced. Therefore, the ball bumps of the semiconductor package due to the rigidity of the reinforcing plate 10
This avoids stress concentration at the connection portion where the 8b is soldered and joined, which helps to improve the reliability of the soldering and joining.

【0022】図2は、上記構成の半導体パッケージを実
装用配線基板15に搭載・実装して構成した実装回路装置
の要部構成を示す断面図である。すなわち、半田ペース
トを塗布(印刷)など行った実装用配線基板15の導電パ
ッド(図示省略)に、前記半導体パッケージのボールバ
ンプ8bを対応・位置合わせマウントした後、前記半田ペ
ーストをリフローさせ、実装用配線基板15の導電パッド
に、対応するボールバンプ8bを電気的および機械的に接
合して、形成した実装回路装置である。
FIG. 2 is a cross-sectional view showing a configuration of a main part of a mounted circuit device configured by mounting and mounting the semiconductor package having the above configuration on the mounting wiring board 15. That is, after the ball bumps 8b of the semiconductor package are mounted on the conductive pads (not shown) of the mounting wiring board 15 on which solder paste is applied (printed) or the like, the solder paste is reflowed and mounted. This is a mounted circuit device formed by electrically and mechanically bonding the corresponding ball bumps 8b to the conductive pads of the wiring board 15 for use.

【0023】上記実装回路装置においては、実装用配線
基板に対し、半導体パッケージのボールバンプ8bを半田
付け・接合した接続部、すなわち半田接続部における疲
労破壊などの発生もほとんど認められず、信頼性の高い
実装構造を採っていた。
In the above-described mounting circuit device, the occurrence of fatigue destruction or the like in the connection portion where the ball bump 8b of the semiconductor package is soldered / joined to the mounting wiring board, that is, the solder connection portion is hardly recognized, and the reliability is improved. High mounting structure.

【0024】なお、本発明は上記例示に限定されるもの
でなく、発明の趣旨を逸脱しない範囲でいろいろの変形
を採り得る。ポリイミド樹脂を基材とする配線基板や樹
脂板の代りに他の耐熱性樹脂、たとえばポリブチレンテ
レフタレート樹脂を基材とした配線基板や樹脂板を用い
てもよいし、また、補強板もステンレス鋼以外の金属製
であってもよい。
It should be noted that the present invention is not limited to the above examples, and various modifications can be made without departing from the spirit of the invention. Instead of a wiring substrate or a resin plate based on a polyimide resin, another heat-resistant resin, for example, a wiring substrate or a resin plate based on a polybutylene terephthalate resin may be used. Other metals may be used.

【0025】[0025]

【発明の効果】請求項1および請求項2の発明によれ
ば、構成部材の熱膨脹率差による反りの発生が、吸収的
に緩和・抑制されるので、たとえば BGA型端子などを導
出配置した配線基板面の平坦性が容易に確保され、信頼
性の高い接続・実装が可能な半導体パッケージが提供さ
れる。すなわち、半導体素子を搭載・配置した領域周辺
部に配置された補強板は、その両面に同種の樹脂基材か
ら成る配線基板および樹脂板を積層一体化した構成を採
ったことにより、反りの発生に大きく影響する補強板の
熱膨脹率が、それらに分散的に吸収・緩和されるので、
樹脂系の配線基板を中心に、半導体パッケージ自体の反
りが全面的に低減・抑制される。したがって、実装用配
線基板面に対する接続・実装に当たってはその平坦性に
伴って、良好な精度での位置決めが可能となるだけでな
く、耐久的な電気的および機械的な接続実装もでき、信
頼性の高い実装回路装置の提供に大きく寄与する。
According to the first and second aspects of the present invention, the occurrence of the warpage due to the difference in the thermal expansion coefficient of the constituent members is absorbed and alleviated and suppressed. Provided is a semiconductor package in which flatness of a substrate surface is easily ensured and connection and mounting with high reliability are possible. That is, the reinforcing plate arranged around the area where the semiconductor element is mounted and arranged has a structure in which a wiring board and a resin plate made of the same type of resin base material are laminated and integrated on both surfaces thereof, thereby causing warpage. Since the coefficient of thermal expansion of the reinforcing plate, which greatly affects the
The warpage of the semiconductor package itself is reduced and suppressed over the entire area of the resin-based wiring board. Therefore, when connecting and mounting to the surface of the mounting wiring board, not only is it possible to perform positioning with good accuracy due to its flatness, but also durable electrical and mechanical connection and mounting is possible, and reliability is improved. This greatly contributes to the provision of a high-performance mounting circuit device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体パッケージの要部構成例を
示す断面図。
FIG. 1 is a sectional view showing an example of a configuration of a main part of a semiconductor package according to the present invention.

【図2】本発明に係る半導体パッケージを搭載した実装
回路装置の要部構成例を示す断面図。
FIG. 2 is a cross-sectional view showing a configuration example of a main part of a mounted circuit device on which a semiconductor package according to the present invention is mounted.

【図3】従来の半導体パッケージを搭載した実装回路装
置の要部構成を示す断面図。
FIG. 3 is a cross-sectional view showing a configuration of a main part of a mounting circuit device on which a conventional semiconductor package is mounted.

【符号の説明】[Explanation of symbols]

8……樹脂系配線基板 8a……接続端子 8b……外部接続端子 9……半導体素子 10……補強板 11a, 11b……接着剤層 12……樹脂板 13……放熱板 14……封止樹脂層 15……実装用配線基板 8 resin wiring board 8a connection terminal 8b external connection terminal 9 semiconductor element 10 reinforcing plate 11a, 11b adhesive layer 12 resin plate 13 heat sink 14 sealing Stopping resin layer 15: Wiring board for mounting

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 一主面に接続端子が設けられ、他主面に
外部接続端子が導出配置された樹脂フィルムを基材とし
た配線基板と、 前記配線基板の接続端子に対応させ電気的に接続・搭載
された半導体素子と、 前記半導体素子周辺を囲繞し、かつ配線基板面に接着剤
層を介して順次積層された補強板および前記配線基板の
基材と同種の樹脂板と、 前記樹脂板との間に間隙を持たせ、かつ半導体素子上面
に接着剤層を介して一体的に配置された放熱板とを具備
することを特徴とする半導体パッケージ。
1. A wiring board having a resin film as a base material having connection terminals provided on one main surface and external connection terminals led out and arranged on the other main surface, and electrically connected to the connection terminals of the wiring board. A semiconductor element connected and mounted, a resin plate of the same kind as a reinforcing plate and a base material of the wiring board, which are sequentially laminated via an adhesive layer on the wiring board surface, surrounding the semiconductor element, and the resin A semiconductor package, comprising: a heat radiating plate having a gap between the plate and a heat radiating plate integrally disposed on an upper surface of the semiconductor element via an adhesive layer.
【請求項2】 樹脂フィルムが、ポリイミド樹脂製であ
ることを特徴とする請求項1記載の半導体パッケージ。
2. The semiconductor package according to claim 1, wherein the resin film is made of a polyimide resin.
JP16757897A 1997-06-24 1997-06-24 Semiconductor package Withdrawn JPH1117064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16757897A JPH1117064A (en) 1997-06-24 1997-06-24 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16757897A JPH1117064A (en) 1997-06-24 1997-06-24 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH1117064A true JPH1117064A (en) 1999-01-22

Family

ID=15852353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16757897A Withdrawn JPH1117064A (en) 1997-06-24 1997-06-24 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH1117064A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002045164A3 (en) * 2000-12-01 2003-03-27 Broadcom Corp Thermally and electrically enhanced ball grid array packaging
US6876553B2 (en) 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
US6879039B2 (en) 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
JP2005217003A (en) * 2004-01-28 2005-08-11 Kyocera Corp Package for storing semiconductor element
WO2009121200A1 (en) * 2008-03-31 2009-10-08 巨擘科技股份有限公司 Method of balancing multilayer substrate stress and multilayer substrate
JPWO2012029526A1 (en) * 2010-08-30 2013-10-28 住友ベークライト株式会社 Semiconductor package and semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002045164A3 (en) * 2000-12-01 2003-03-27 Broadcom Corp Thermally and electrically enhanced ball grid array packaging
US6879039B2 (en) 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
US6876553B2 (en) 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
JP2005217003A (en) * 2004-01-28 2005-08-11 Kyocera Corp Package for storing semiconductor element
WO2009121200A1 (en) * 2008-03-31 2009-10-08 巨擘科技股份有限公司 Method of balancing multilayer substrate stress and multilayer substrate
JPWO2012029526A1 (en) * 2010-08-30 2013-10-28 住友ベークライト株式会社 Semiconductor package and semiconductor device

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