JP2005213126A - Reduction-resistant dielectric composition and ceramic electronic component using the same - Google Patents

Reduction-resistant dielectric composition and ceramic electronic component using the same Download PDF

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JP2005213126A
JP2005213126A JP2004025234A JP2004025234A JP2005213126A JP 2005213126 A JP2005213126 A JP 2005213126A JP 2004025234 A JP2004025234 A JP 2004025234A JP 2004025234 A JP2004025234 A JP 2004025234A JP 2005213126 A JP2005213126 A JP 2005213126A
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JP4674438B2 (en
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Nobuaki Nagai
伸明 永井
Yuichi Murano
雄一 村野
Shoichi Ikebe
庄一 池辺
Akio Hidaka
晃男 日高
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a reduction-resistant dielectric composition prepared by uniformly dispersing a sintering additive component into a main component without segregation and a ceramic electronic component using the reduction-resistant dielectric composition, having excellent reliable durability, small self-heating in high frequency current and excellent charcteristics for medium/high voltage. <P>SOLUTION: The reduction-resistant dielectric composition is obtained by successively carrying out a process for preparing a colloidal suspension containing the sintering additive component expressed by general formula, (Ca<SB>1-X</SB>Ba<SB>X</SB>)SiO<SB>3</SB>(where 0≤X≤1) by dropping ammonia water while stirring and mixing acetate aqueous solution of at least one or more kinds of Ca and Ba with a metal alkoxide ethanol solution of Si and a process for preparing raw material powder by mixing the colloidal suspension with powder of a main component expressed by general formula, (Sr<SB>1-X</SB>Ca<SB>X</SB>)<SB>m</SB>(Ti<SB>1-Y</SB>Zr<SB>Y</SB>)O<SB>2+m</SB>(where 0.55≤X≤0.85, 0.80≤Y≤1.00 and 993≤m≤1,007) and a trace quantity of an additive. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、内部電極が卑金属から成り、JIS規格COG特性を満足し、高周波電流が流れるためQ値(誘電体損失係数の逆数)が高く且つ低自己発熱が要求されるスイッチング電源のトランジスタスナバー回路、液晶ディスプレイパネル(LCD)を構成しているバックライトのインバータ電源回路、及び低歪み率が要求される通信用デジタルモデムの対サージ回路等に中高圧用として広く適用される積層セラミックコンデンサに代表されるセラミック電子部品及びそれを製造する為の耐還元性誘電体組成物に関するものである。   The present invention provides a transistor snubber circuit for a switching power supply in which an internal electrode is made of a base metal, satisfies JIS standard COG characteristics, and a high-frequency current flows, so that a high Q value (reciprocal of dielectric loss coefficient) is required and low self-heating is required. Typical examples of multilayer ceramic capacitors widely used for medium- and high-voltage applications in inverter power supply circuits for backlights that make up liquid crystal display panels (LCDs) and anti-surge circuits for communication digital modems that require low distortion The present invention relates to a ceramic electronic component to be manufactured and a reduction-resistant dielectric composition for producing the same.

近年、通信用モデム、LCD及びスイッチング電源等のPC周辺機器及び電子通信機器の軽薄短小化に伴いそれに使用される重要な受動部品の1つであるセラミックコンデンサも従来の円板型から積層型への移行が急速に進み、スイッチング電源回路やモデム回路の小型化、樹脂モールド化、及びLCDの薄型化に寄与している。また、信用調査機関のデータによると西暦2005年にはセラミックコンデンサの積層化率は90%を超える事が確実であり、低定格電圧品のみならず中高圧品、更には安全規格品の領域にまで積層化が波及するのは時間の問題である。   In recent years, ceramic peripherals, which are one of the important passive components used for PC peripheral devices such as communication modems, LCDs, and switching power supplies, and electronic communication devices are becoming more and more compact. The transition of this technology is progressing rapidly, contributing to the miniaturization of switching power supply circuits and modem circuits, the resin molding, and the thinning of LCDs. In addition, according to the data of the credit bureau, it is certain that the lamination rate of ceramic capacitors will exceed 90% in the year 2005, and not only low rated voltage products but also medium and high voltage products, as well as safety standard products. It is a matter of time for the lamination to spread.

例えば、100KHz程度の高周波電流が流れるスイッチング電源のトランジスタスナバー回路には定格電圧が2〜3KVDCで静電容量が数10pFのJIS規格SL特性を満足する中高圧用積層セラミックコンデンサが使用されており、回路の小型化に寄与している。また、LCDの薄型化に伴いバックライトのインバータ電源回路には、従来の円板型に代わって、定格電圧が3KVDCで静電容量が数10〜100pFのJIS規格SL特性を満足する中高圧用積層セラミックコンデンサが適用されつつある。   For example, a transistor snubber circuit of a switching power supply in which a high-frequency current of about 100 KHz flows uses a medium-high voltage multilayer ceramic capacitor that satisfies a JIS standard SL characteristic with a rated voltage of 2 to 3 KVDC and a capacitance of several tens of pF. This contributes to miniaturization of the circuit. In addition, the LCD inverter power supply circuit is used for medium- and high-voltages that satisfy the JIS standard SL characteristics with a rated voltage of 3 KVDC and a capacitance of several tens to 100 pF, instead of the conventional disk type, as LCDs become thinner. Multilayer ceramic capacitors are being applied.

上記中高圧用積層セラミックコンデンサの構造は、セラミック誘電体層と内部電極層が交互に複数積層されて静電容量を取得する有効層が形成され、その有効層の上下に全体の寸法調整と内部気密封止の為にセラミック誘電体層のみから成る無効層が形成されている。そして、内部電極層の電気的接続は、それらの終端部分が露出した両端面に外部電極を設けることによって行い、これら外部電極表面には半田付け実装を容易に且つ支障なく行える様に、Ni鍍金の上にSn鍍金又はCu鍍金が層状に施された構造となっている。   The above-mentioned medium- and high-voltage multilayer ceramic capacitor has a structure in which a plurality of ceramic dielectric layers and internal electrode layers are alternately stacked to form an effective layer for obtaining capacitance, and the entire dimension adjustment and internal structure are formed above and below the effective layer. An ineffective layer consisting only of a ceramic dielectric layer is formed for hermetic sealing. The internal electrode layers are electrically connected by providing external electrodes on both end faces where the terminal portions are exposed, and Ni plating is performed on these external electrode surfaces so that they can be easily soldered and mounted. It has a structure in which Sn plating or Cu plating is applied in layers.

従来より、この様な用途のJIS規格SL特性を満足する中高圧用積層セラミックコンデンサは、低損失であると同時に高周波電流により異常発熱しないことが求められており、誘電体組成物としては主成分であるSrTiO3−CaTiO3系に数種類の添加物を加えたものが主流であり、主成分であるSrTiO3−CaTiO3−MgTiO3系に添加物としてZrO2、Nb25、Ta25、V25等を加えた組成物が開示されており、これによると主成分を構成している化合物の比率で静電容量温度変化率を制御し、添加物により絶縁破壊電圧と絶縁抵抗値を向上させることが記載されている(例えば特許文献1参照)。 Conventionally, a multilayer ceramic capacitor for medium to high voltage satisfying JIS standard SL characteristics for such applications has been required to have low loss and not to generate abnormal heat due to high frequency current. In the SrTiO 3 —CaTiO 3 system, several types of additives are added, and the main component SrTiO 3 —CaTiO 3 —MgTiO 3 system includes ZrO 2 , Nb 2 O 5 , Ta 2 O as additives. 5 , a composition to which V 2 O 5 and the like are added is disclosed. According to this, the rate of change in capacitance temperature is controlled by the ratio of the compounds constituting the main component, and the breakdown voltage and insulation are controlled by the additive. It is described that the resistance value is improved (see, for example, Patent Document 1).

しかしながら上記誘電体組成物は、耐還元性を有しているものではなく、内部電極としてPd系貴金属の使用を前提としたものであり、特に高積層数高静電容量の品種において原材料コストの面で問題があった。これを解決する方法として、Pd系の貴金属に代わりコストの安いNiあるいはNiを主成分とする合金を使用することが公知であり、中高圧用積層セラミックコンデンサに占める卑金属内部電極品の割合は増加傾向にある。   However, the dielectric composition does not have reduction resistance, and is premised on the use of a Pd-based noble metal as an internal electrode. There was a problem in terms. As a method for solving this problem, it is known to use low-cost Ni or an alloy containing Ni as a main component instead of Pd-based noble metals, and the proportion of base metal internal electrode products in the medium- and high-pressure multilayer ceramic capacitors is increased. There is a tendency.

Niは卑金属であるので、従来の貴金属の積層セラミックコンデンサの様に酸素雰囲気
中で焼成することは不可能で、低酸素分圧雰囲気中においてNiが酸化されないように焼成しなければならない。セラミックコンデンサ用として公知であるABO3の一般式で表現されるペロブスカイト酸化物は、1,000℃以上の高温においてNiの酸化還元平衡酸素分圧以下の雰囲気に晒されると還元され、絶縁抵抗値が低下したり、電界を印加した状態での信頼性試験、いわゆる負荷寿命での不良率が増大し、コンデンサ用誘電体としての機能を果たさなくなる。
Since Ni is a base metal, it cannot be fired in an oxygen atmosphere like conventional noble metal multilayer ceramic capacitors, and must be fired so that Ni is not oxidized in a low oxygen partial pressure atmosphere. A perovskite oxide expressed by the general formula of ABO 3 which is well known for ceramic capacitors is reduced when exposed to an atmosphere below the Ni redox equilibrium oxygen partial pressure at a high temperature of 1,000 ° C. or higher, resulting in an insulation resistance value. Or the reliability test in a state where an electric field is applied, that is, a failure rate in a so-called load life increases, and the function as a dielectric for a capacitor is not achieved.

この課題に対し、これらペロブスカイト酸化物が、AサイトとBサイトに存在するイオンの化学量論比を変化させたり、あるいは格子中にドナーとなって固溶しうる、例えば遷移金属イオン等を添加したりすることによって、前述のような熱処理を行っても還元されにくくなる性質を利用して、ペロブスカイト酸化物と微量の添加物から構成される多くの耐還元性誘電体組成物が考案され、開示されている。以前の耐還元性誘電体組成物は、静電容量の温度変化率が大きいJIS規格F特性は言うまでもないが、静電容量の温度変化率が小さいJIS規格B特性或いはEIA規格X7R特性が主流であったが、近年積極的な材料開発が行われ、卑金属化が困難とされていた低誘電率系のJIS規格COG特性或いはJIS規格SL特性が積層セラミックコンデンサに適用されている。例えば、特開2002−80278号公報には主成分のSrTiO3−CaTiO3系に対して、添加物としてV25及びMnCO3、焼結助剤としてSiO2−CaO系化合物を各々含有した耐還元性誘電体組成物が開示されている。これにより、歪み率が小さく、DCバイアス特性に優れ、しかも安価なNi系の内部電極を使用した大容量の積層セラミックコンデンサが主として50VDCの低定格電圧品を中心に商品化されている。
特開平7−211140号公報
In response to this problem, these perovskite oxides can change the stoichiometric ratio of ions existing at the A site and B site, or can be dissolved in the lattice as a donor, such as transition metal ions. As a result, many reduction-resistant dielectric compositions composed of a perovskite oxide and a small amount of an additive have been devised, taking advantage of the property that it is difficult to reduce even if heat treatment as described above is performed, It is disclosed. The previous reduction-resistant dielectric composition has JIS standard F characteristics with a large capacitance temperature change rate, but JIS standard B characteristics or EIA standard X7R characteristics with a small capacitance temperature change rate are the mainstream. In recent years, however, active material development has been carried out, and low dielectric constant JIS standard COG characteristics or JIS standard SL characteristics, which have been difficult to be made into base metals, have been applied to multilayer ceramic capacitors. For example, Japanese Patent Application Laid-Open No. 2002-80278 contains V 2 O 5 and MnCO 3 as additives and a SiO 2 —CaO compound as a sintering aid with respect to the main component SrTiO 3 —CaTiO 3 . A reduction resistant dielectric composition is disclosed. As a result, large-capacity monolithic ceramic capacitors using a Ni-type internal electrode with a low distortion rate, excellent DC bias characteristics, and low cost are mainly commercialized mainly for low rated voltage products of 50 VDC.
Japanese Patent Laid-Open No. 7-211140

しかしながら、従来の耐還元性誘電体組成物の多くは主成分であるペロブスカイト酸化物に対する微量添加物の均一な分散性や反応性を考慮して設計されたものであるとは言い難く、工程上制御しえない要因によって製品の特性、品質が変動し、歩留まりの低下や信頼性不良を引き起こしている。例えば、従来のプロセスである仮焼混合法により作製した耐還元性誘電体組成物は微量添加物の中でも特にSiO2−CaO系やSiO2−CaO−BaO系等の焼結助剤成分を均一に分散させることが難しく、焼結助剤成分が不均一に分散した組成物であった。その結果、焼成時の反応過程で局部的な異常反応を起こし、結晶粒子径のばらつきが大きくなりしかもポアーが多い不均質な微細構造となり、静電容量や誘電体損失のばらつきが生じ、絶縁破壊電圧が低く、また超加速寿命試験(HALT)における故障時間の分布が広く、平均故障時間が短いという問題点を有していた。 However, it is difficult to say that many of the conventional reduction-resistant dielectric compositions are designed in consideration of the uniform dispersibility and reactivity of trace additives with respect to the main component perovskite oxide. The characteristics and quality of the product fluctuate due to factors that cannot be controlled, causing a decrease in yield and poor reliability. For example, reduction-resistant dielectric composition prepared by calcination mixing method is a conventional process uniform sintering aid component, especially SiO 2 -CaO-based and SiO 2 -CaO-BaO based, etc. Among dopants It was difficult to disperse in the composition, and the sintering aid component was dispersed non-uniformly. As a result, a local abnormal reaction occurs in the reaction process during firing, resulting in a heterogeneous microstructure with large variations in crystal particle size and many pores, resulting in variations in capacitance and dielectric loss, and dielectric breakdown. The problem is that the voltage is low, the failure time distribution in the super accelerated life test (HALT) is wide, and the average failure time is short.

そこで、本発明は以上のような課題を解決し、焼結助剤成分を偏析させることなく主成分中に均一に分散させた耐還元性誘電体組成物を提供し、該耐還元性誘電体組成物を用いて、Q値が高く、高周波電流下において自己発熱が小さく、中高圧用として耐久信頼性に優れ、且つ静電容量温度変化率がJIS規格COG特性を満足するセラミック電子部品を提供することを目的としている。   Accordingly, the present invention provides a reduction-resistant dielectric composition in which the above-described problems are solved and the sintering aid component is uniformly dispersed in the main component without segregation, and the reduction-resistant dielectric is provided. Using the composition, ceramic electronic parts with high Q value, low self-heating under high-frequency current, excellent durability and reliability for medium and high pressure, and satisfying JIS standard COG characteristics with capacitance temperature change rate The purpose is to do.

この目的を達成するために本発明の耐還元性誘電体組成物は、Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造したものである。これに
より、Ca、Ba及びSiを含有するコロイド状懸濁液の均一分散が達成され、主成分であるSrTiO3−CaZrO3系固溶体粒子の周囲がこれらの成分により均一にコーティングされる為、焼成時に局部的な異常反応がなく焼結助剤成分が均一に分散された非常に緻密な組織を形成することが可能な耐還元性誘電体組成物が得られる。
In order to achieve this object, the reduction-resistant dielectric composition of the present invention is prepared by dropping ammonia water while stirring and mixing at least one acetate aqueous solution of Ca and Ba with a metal alkoxide ethanol solution of Si ( A step of preparing a colloidal suspension containing a component represented by the general formula of Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ 1), and the colloidal suspension (Sr 1- X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) The raw material powder is manufactured by sequentially mixing with the main component powder and a small amount of additives. Thereby, uniform dispersion of the colloidal suspension containing Ca, Ba and Si is achieved, and the periphery of the main component SrTiO 3 —CaZrO 3 solid solution particles is uniformly coated with these components. A reduction-resistant dielectric composition capable of forming a very dense structure in which there is sometimes no local abnormal reaction and the sintering aid component is uniformly dispersed is obtained.

また、前記コロイド状懸濁液に含まれる(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分量及び前記添加物の種類とその添加量を主成分の粉末に対して規定することにより、優れた初期特性と耐久信頼性を有し、高周波電流下における自己発熱が小さい中高圧用積層セラミックコンデンサに代表されるセラミック電子部品を実現することが可能な耐還元性誘電体組成物が得られる。 In addition, the amount of the component represented by the general formula of (Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ 1) contained in the colloidal suspension, and the types and amounts of the additives By defining for the main component powder, it is possible to realize ceramic electronic components represented by multilayer ceramic capacitors for medium to high pressure that have excellent initial characteristics and durability reliability, and have low self-heating under high-frequency current. A possible reduction-resistant dielectric composition is obtained.

また、本発明のセラミック電子部品は第1の複数のセラミック誘電体層の間にNi或いはNiを主成分とする合金よりなる内部電極層を設けた有効層及び第2の複数のセラミック誘電体層より成る無効層を有した基体と、前記基体の両端部から側部に至るように設けられ、前記内部電極層と電気的に接合された一対の外部電極と、前記外部電極にそれぞれ接続された端子とを備え、前記基体及び外部電極が樹脂により埋め込まれたモールド型のセラミック電子部品であり、前記セラミック誘電体層を前記耐還元性誘電体組成物で構成することにより、所定の製品規格値を全て満足しうる中高圧用積層セラミックコンデンサに代表されるセラミック電子部品が得られる。   The ceramic electronic component of the present invention includes an effective layer in which an internal electrode layer made of Ni or an alloy containing Ni as a main component is provided between a plurality of first ceramic dielectric layers, and a second plurality of ceramic dielectric layers. A base having an ineffective layer, a pair of external electrodes provided from both ends to the side of the base and electrically joined to the internal electrode layer, and connected to the external electrode, respectively A molded ceramic electronic component in which the base body and the external electrode are embedded with resin, and the ceramic dielectric layer is made of the reduction-resistant dielectric composition, thereby providing a predetermined product standard value. Thus, a ceramic electronic component typified by a multilayer ceramic capacitor for medium and high voltage satisfying all of the above can be obtained.

以上の様に本発明によれば、Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び特性向上のための微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造した耐還元性誘電体組成物であるため、Ca、Ba及びSiを含有するコロイド状懸濁液の均一分散が達成され、主成分である(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)固溶体粒子の周囲がこれらの成分により均一にコーティングされる為、焼成時に局部的な異常反応がなく焼結助剤成分が均一に分散された非常に緻密な組織を有するセラミック誘電体層が形成されるため、中高圧用として良好な電気特性と耐久信頼性を有するNi内部電極積層セラミックコンデンサを実現することができる。 As described above, according to the present invention, ammonia water is added dropwise (Ca 1-X Ba X ) SiO 3 while stirring and mixing at least one acetate aqueous solution of Ca and Ba and a metal alkoxide ethanol solution of Si. (However, a step of preparing a colloidal suspension containing a component represented by the general formula of 0 ≦ X ≦ 1), and the colloidal suspension (Sr 1−X Ca X ) m (Ti 1− Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) Colloidal suspension containing Ca, Ba, and Si because it is a reduction-resistant dielectric composition manufactured by sequentially performing a process of producing raw material powder by mixing with a small amount of additive for improvement (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) The solid solution particles are uniformly coated with these components. Therefore, there is no local abnormal reaction during firing, and a ceramic dielectric layer with a very dense structure in which the sintering aid components are uniformly dispersed is formed. It is possible to realize a Ni internal electrode multilayer ceramic capacitor having the characteristics.

また、前記(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される焼結助剤成分の量及び前記添加物の種類とその添加量を規定することにより、高度な製品特性を有し、且つ高周波のパルスが印加される回路において優れた耐久信頼性を有するNi内部電極中高圧用積層セラミックコンデンサに代表されるセラミック電子部品を実現することができる。 Further, the amount of the sintering aid component represented by the general formula of (Ca 1−X Ba X ) SiO 3 (where 0 ≦ X ≦ 1), the kind of the additive, and the amount of the additive are specified. As a result, it is possible to realize a ceramic electronic component represented by a multilayer ceramic capacitor for high voltage in the Ni internal electrode, which has high product characteristics and excellent durability reliability in a circuit to which a high frequency pulse is applied.

また、前記耐還元性誘電体組成物を使用することにより、中高圧用としてそれぞれの特徴を生かして、ユーザの要望に応じた回路設計が可能なチップ型、モールド型及びリード型のNi内部電極積層セラミックコンデンサに代表されるセラミック電子部品を実現することができる。   In addition, by using the reduction-resistant dielectric composition, chip-type, mold-type and lead-type Ni internal electrodes that can be used for medium-high voltage applications and can be designed in accordance with user requirements. A ceramic electronic component typified by a multilayer ceramic capacitor can be realized.

本発明の請求項1に記載の発明は、Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下し
て(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造した耐還元性誘電体組成物であって、高圧用として良好な電気特性と耐久信頼性を有するNi内部電極積層セラミックコンデンサを実現することができる。
According to the first aspect of the present invention, ammonia water is added dropwise (Ca 1-X Ba X ) while stirring and mixing at least one acetate aqueous solution of Ca and Ba and a metal alkoxide ethanol solution of Si. A step of preparing a colloidal suspension containing a component represented by the general formula of SiO 3 (where 0 ≦ X ≦ 1), and the colloidal suspension is (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) And a reduction-resistant dielectric composition produced by sequentially performing a process of producing a raw material powder by mixing together with a small amount of additives, and having a good internal property and durability reliability for high pressure use A multilayer ceramic capacitor can be realized.

本発明の請求項2に記載の発明は、Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造した耐還元性誘電体組成物において、前記コロイド状懸濁液に含まれる(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分は、前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して、1.0〜5.0モルの範囲内であることを特徴とする耐還元性誘電体組成物であって、高圧用として良好な電気特性と耐久信頼性を有するNi内部電極積層セラミックコンデンサを実現することができる。 According to the second aspect of the present invention, ammonia water is dropped while stirring and mixing an aqueous solution of at least one acetate salt of Ca and Ba and a metal alkoxide ethanol solution of Si (Ca 1-X Ba X ). A step of preparing a colloidal suspension containing a component represented by the general formula of SiO 3 (where 0 ≦ X ≦ 1), and the colloidal suspension is (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) And a reduction-resistant dielectric composition manufactured by sequentially performing a process of preparing a raw material powder by mixing with a small amount of additives, and (Ca 1-X Ba X ) SiO contained in the colloidal suspension 3 (where, 0 ≦ X ≦ 1) component represented by the general formula, the (Sr 1-X C X) m (Ti 1-Y Zr Y) O 2 + m ( where, represented by the general formula 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) A reduction-resistant dielectric composition characterized by being in the range of 1.0 to 5.0 moles with respect to 100 moles of the main component powder, and has good electrical properties and durability reliability for high pressure use It is possible to realize a Ni internal electrode multilayer ceramic capacitor having the characteristics.

本発明の請求項3に記載の発明は、Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造した耐還元性誘電体組成物において、前記添加物は、前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して、各々Mn34が0.05〜2.0モルの範囲内、V25が0.01〜0.3モルの範囲内、Al203が0.05〜1.0モルの範囲内、CeO2が0.01〜2.0モルの範囲内、及びMgOが0.01〜0.2モルの範囲内であることを特徴とする耐還元性誘電体組成物であって、高圧用として良好な電気特性と耐久信頼性を有するNi内部電極積層セラミックコンデンサを実現することができる。 In the invention according to claim 3 of the present invention, ammonia water is added dropwise (Ca 1-X Ba X ) while stirring and mixing at least one of an aqueous solution of acetate of Ca and Ba and a metal alkoxide ethanol solution of Si. A step of preparing a colloidal suspension containing a component represented by the general formula of SiO 3 (where 0 ≦ X ≦ 1), and the colloidal suspension is (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) In addition, in the reduction-resistant dielectric composition manufactured by sequentially performing a process of preparing a raw material powder by mixing with a small amount of additive, the additive is the (Sr 1-X Ca X ) m (Ti 1 -Y Zr Y) O 2 + m ( where, 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 99 ≦ respect m ≦ 1.007 powder 100 moles of the main component represented by the general formula), each Mn 3 O 4 is in the range of 0.05 to 2.0 mole, V 2 O 5 is 0.01 In the range of ~ 0.3 mol, Al203 in the range of 0.05 to 1.0 mol, CeO2 in the range of 0.01 to 2.0 mol, and MgO in the range of 0.01 to 0.2 mol. It is possible to realize a Ni internal electrode multilayer ceramic capacitor which is a reduction-resistant dielectric composition characterized in that it has good electrical characteristics and durability reliability for high voltage use.

本発明の請求項4に記載の発明は、Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造した耐還元性誘電体組成物において、前記コロイド状懸濁液に含まれる(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分は、前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して、1.0〜5.0モルの範囲内であることを特徴とし、さらに前記添加物は、前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉
末100モルに対して、各々Mn34が0.05〜2.0モルの範囲内、V25が0.01〜0.3モルの範囲内、Al23が0.05〜1.0モルの範囲内、CeO2が0.01〜2.0モルの範囲内、及びMgOが0.01〜0.2モルの範囲内であることを特徴とする耐還元性誘電体組成物であって、高圧用として良好な電気特性と耐久信頼性を有するNi内部電極積層セラミックコンデンサを実現することができる。
In the invention according to claim 4 of the present invention, ammonia water is dropped while stirring and mixing at least one of an aqueous solution of acetate of Ca and Ba and a metal alkoxide ethanol solution of Si (Ca 1-X Ba X ). A step of preparing a colloidal suspension containing a component represented by the general formula of SiO 3 (where 0 ≦ X ≦ 1), and the colloidal suspension is (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) And a reduction-resistant dielectric composition manufactured by sequentially performing a process of preparing a raw material powder by mixing with a small amount of additives, and (Ca 1-X Ba X ) SiO contained in the colloidal suspension 3 (where, 0 ≦ X ≦ 1) component represented by the general formula, the (Sr 1-X C X) m (Ti 1-Y Zr Y) O 2 + m ( where, represented by the general formula 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) The additive is contained in the range of 1.0 to 5.0 moles with respect to 100 moles of the main component powder. Further, the additive is the (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (however, 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) On the other hand, Mn 3 O 4 is in the range of 0.05 to 2.0 mol, V 2 O 5 is in the range of 0.01 to 0.3 mol, and Al 2 O 3 is 0.05 to 1.0. A reduction-resistant dielectric composition characterized by having a molar range, CeO 2 within a range of 0.01 to 2.0 mol, and MgO within a range of 0.01 to 0.2 mol. For high pressure It is possible to realize the Ni internal electrode multilayer ceramic capacitor having excellent electric properties and durability and reliability.

本発明の請求項5に記載の発明は、第1の複数のセラミック誘電体層の間にNi或いはNiを主成分とする合金よりなる内部電極層を設けた有効層及び第2の複数のセラミック誘電体層より成る無効層を有した基体と、前記基体の両端部から側部に至るように設けられ、前記内部電極層と電気的に接合された一対の外部電極とを備えたチップ型のセラミック電子部品であり、前記セラミック誘電体層を請求項1〜4いずれか1記載の耐還元性誘電体組成物で構成したことを特徴とするセラミック電子部品であって、高度な製品特性を有し、且つ高周波のパルスが印加される回路において優れた耐久信頼性を有するNi内部電極中高圧用積層セラミックコンデンサに代表されるセラミック電子部品を実現することができる。   According to a fifth aspect of the present invention, an effective layer in which an internal electrode layer made of Ni or an alloy containing Ni as a main component is provided between the first plurality of ceramic dielectric layers and the second plurality of ceramics. A chip type comprising: a base having an ineffective layer made of a dielectric layer; and a pair of external electrodes provided from both ends of the base to the side and electrically joined to the internal electrode layer A ceramic electronic component, wherein the ceramic dielectric layer is composed of the reduction-resistant dielectric composition according to any one of claims 1 to 4, and has high product characteristics. In addition, it is possible to realize a ceramic electronic component typified by a multilayer ceramic capacitor for medium-high voltage Ni internal electrodes having excellent durability and reliability in a circuit to which a high-frequency pulse is applied.

本発明の請求項6に記載の発明は、第1の複数のセラミック誘電体層の間にNi或いはNiを主成分とする合金よりなる内部電極層を設けた有効層及び第2の複数のセラミック誘電体層より成る無効層を有した基体と、前記基体の両端部から側部に至るように設けられ、前記内部電極層と電気的に接合された一対の外部電極と、前記外部電極にそれぞれ接続された端子とを備え、前記基体及び外部電極が樹脂により埋め込まれたモールド型のセラミック電子部品であり、前記セラミック誘電体層を請求項1〜4いずれか1記載の耐還元性誘電体組成物で構成したことを特徴とするセラミック電子部品であって、高度な製品特性を有し、且つ高周波のパルスが印加される回路において優れた耐久信頼性を有するNi内部電極中高圧用積層セラミックコンデンサに代表されるセラミック電子部品を実現することができる。   According to a sixth aspect of the present invention, there is provided an effective layer in which an internal electrode layer made of Ni or an alloy containing Ni as a main component is provided between the first plurality of ceramic dielectric layers, and the second plurality of ceramics. A base having an ineffective layer made of a dielectric layer, a pair of external electrodes provided from both ends of the base to the side, and electrically joined to the internal electrode layer; and A reduction-resistant dielectric composition according to any one of claims 1 to 4, wherein the ceramic dielectric layer is a molded ceramic electronic component including a connected terminal, and the base and the external electrode are embedded with a resin. A ceramic electronic component characterized in that it is composed of a product, and has high product characteristics and has excellent durability and reliability in a circuit to which a high-frequency pulse is applied. It is possible to realize a ceramic electronic component typified by a click capacitor.

本発明の請求項7に記載の発明は、第1の複数のセラミック誘電体層の間にNi或いはNiを主成分とする合金よりなる内部電極層を設けた有効層及び第2の複数のセラミック誘電体層より成る無効層を有した基体と、前記基体の両端部から側部に至るように設けられ、前記内部電極層と電気的に接合された一対の外部電極と、前記外部電極にそれぞれ接続されたリード線とを備え、前記基体及び外部電極が樹脂により被覆されたリード型のセラミック電子部品であり、前記セラミック誘電体層を請求項1〜4いずれか1記載の耐還元性誘電体組成物で構成したことを特徴とするセラミック電子部品であって、高度な製品特性を有し、且つ高周波のパルスが印加される回路において優れた耐久信頼性を有するNi内部電極中高圧用積層セラミックコンデンサに代表されるセラミック電子部品を実現することができる。   According to a seventh aspect of the present invention, there is provided an effective layer in which an internal electrode layer made of Ni or an alloy containing Ni as a main component is provided between the first plurality of ceramic dielectric layers, and the second plurality of ceramics. A base having an ineffective layer made of a dielectric layer, a pair of external electrodes provided from both ends of the base to the side, and electrically joined to the internal electrode layer; and A reduction-resistant dielectric according to any one of claims 1 to 4, wherein the ceramic dielectric layer is a lead-type ceramic electronic component comprising a connected lead wire, the base and the external electrode being covered with a resin. A ceramic electronic component comprising a composition, having high product characteristics, and having excellent durability and reliability in a circuit to which a high-frequency pulse is applied. It is possible to realize a ceramic electronic component typified by a click capacitor.

本発明の請求項8に記載の発明は、前記外部電極は上層、下層の二層構造であり、下層は前記基体の端面のみに設けたことを特徴とする請求項5〜7いずれか1記載のセラミック電子部品であって、高度な製品特性を有し、且つ高周波のパルスが印加される回路において優れた耐久信頼性を有するNi内部電極中高圧用積層セラミックコンデンサに代表されるセラミック電子部品を実現することができる。   According to an eighth aspect of the present invention, the external electrode has a two-layer structure of an upper layer and a lower layer, and the lower layer is provided only on an end surface of the base. A ceramic electronic component represented by a multilayer ceramic capacitor for high voltage in Ni internal electrode, having high product characteristics and excellent durability reliability in a circuit to which a high frequency pulse is applied. Can be realized.

以下、本発明の実施例について図面を用いて説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図1は、本発明のセラミック電子部品の一実施例を示す断面図である。これによると、セラミック誘電体層13とNiを含む内部電極層12a、12b、12cとを交互に積層して形成された静電容量取得層となる有効層の上下に無効層としてセラミック誘電体層13が積層されて積層体11が形成されており、該積層体11の両端部に前記内部電極層1
2b、12cと電気的に接合されたNi質下層外部電極14が設けられ、その上にAg質上層外部電極15が設けられた構成である。
FIG. 1 is a cross-sectional view showing an embodiment of the ceramic electronic component of the present invention. According to this, the ceramic dielectric layer as an ineffective layer above and below the effective layer serving as a capacitance acquisition layer formed by alternately laminating the ceramic dielectric layer 13 and the internal electrode layers 12a, 12b, and 12c containing Ni. 13 is laminated to form a laminated body 11, and the internal electrode layer 1 is formed at both ends of the laminated body 11.
2b and 12c, a Ni-type lower external electrode 14 that is electrically joined to each other is provided, and an Ag-type upper external electrode 15 is provided thereon.

また、図2は、本発明のセラミック電子部品の一実施例を示す断面図である。これによると、セラミック誘電体層23とNiを含む内部電極層22a、22b、22cとを交互に積層して形成された静電容量取得層となる有効層の上下に無効層としてセラミック誘電体層23が積層されて積層体21が形成されており、該積層体21の両端部に内部電極層22b,22cと電気的に接合されたNi質下層外部電極24が設けられ、その上にAg質上層外部電極25が設けられた構成である。そして、熱硬化性樹脂26に埋込まれた積層体21の両端部から導電性の端子27が引出され、該端子27を介して回路基板に表面実装できるように構成されている。   FIG. 2 is a cross-sectional view showing an embodiment of the ceramic electronic component of the present invention. According to this, the ceramic dielectric layer as an ineffective layer above and below the effective layer serving as a capacitance acquisition layer formed by alternately laminating the ceramic dielectric layer 23 and the internal electrode layers 22a, 22b, and 22c containing Ni. 23 is laminated to form a laminated body 21, and Ni-type lower external electrodes 24 electrically connected to the internal electrode layers 22 b and 22 c are provided at both ends of the laminated body 21, and Ag quality is provided thereon. The upper layer external electrode 25 is provided. Then, conductive terminals 27 are drawn from both end portions of the laminate 21 embedded in the thermosetting resin 26, and are configured to be surface-mounted on the circuit board via the terminals 27.

さらに、図3は、本発明のセラミック電子部品の一実施例を示す断面図である。これによると、セラミック誘電体層33とNiを含む内部電極層32a、32b、32cとを交互に積層して形成された静電容量取得層となる有効層の上下に無効層としてセラミック誘電体層33が積層されて積層体31が形成されており、該積層体31の両端部に前記内部電極層32b,32cと電気的に接合されたNi質下層外部電極34が設けられ、その上にAg質上層外部電極35が設けられた構成である。そして、外装材36に被覆された積層体31の両端部から導電性のリード線37が引出され、該リード線37を介して回路基板に半田付けできるように構成されている。前記、3種類の構造を有する中高圧用積層セラミックコンデンサは、それぞれの特徴を生かしてユーザの要望に応じた使い分けが可能であるが、特にモールド型及びリード型中高圧用積層セラミックコンデンサは、異常電圧による沿面放電の心配がなく、さらに回路基板には各々の積層体の両端部から引出された端子及びリード線が半田付けされる為、回路基板にたわみが発生したとしても積層体本体には機械的応力が一切印加されないため、回路設計上優位性の極めて高いものである。   FIG. 3 is a cross-sectional view showing an embodiment of the ceramic electronic component of the present invention. According to this, the ceramic dielectric layer as an ineffective layer above and below the effective layer serving as a capacitance acquisition layer formed by alternately laminating the ceramic dielectric layer 33 and the internal electrode layers 32a, 32b, and 32c containing Ni. 33 is laminated to form a laminated body 31, and Ni-based lower external electrodes 34 electrically connected to the internal electrode layers 32b and 32c are provided at both ends of the laminated body 31, and Ag is formed thereon. In this configuration, a high-quality external electrode 35 is provided. Then, conductive lead wires 37 are drawn out from both end portions of the laminate 31 covered with the exterior material 36, and can be soldered to the circuit board via the lead wires 37. The medium and high voltage multilayer ceramic capacitors having the three types of structures can be selectively used according to the user's request by taking advantage of their respective characteristics. Particularly, the mold type and the lead type medium and high voltage multilayer ceramic capacitors are abnormal. There is no worry of creeping discharge due to voltage, and the terminals and lead wires drawn from both ends of each laminate are soldered to the circuit board, so even if the circuit board is bent, the laminate body has Since no mechanical stress is applied, the circuit design is extremely superior.

そして、前記中高圧用積層セラミックコンデンサのセラミック誘電体層を構成している耐還元性誘電体組成物は、Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造したものであり、好ましくは前記コロイド状懸濁液に含まれる(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分は、前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.850≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して、1.0〜5.0モルの範囲内であり、前記添加物は前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して、各々Mn34が0.05〜2.0モルの範囲内、V25が0.01〜0.3モルの範囲内、Al203が0.05〜1.0モルの範囲内、CeO2が0.01〜2.0モルの範囲内、及びMgOが0.01〜0.2モルの範囲内である。 And, the reduction-resistant dielectric composition constituting the ceramic dielectric layer of the above-mentioned medium-high voltage multilayer ceramic capacitor is prepared by stirring and mixing at least one acetate aqueous solution of Ca and Ba with a metal alkoxide ethanol solution of Si. A colloidal suspension containing a component represented by the general formula of (Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ 1) by dropping ammonia water while (Sr 1−X Ca X ) m (Ti 1−Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) is produced by sequentially carrying out a raw material powder by mixing with the main component powder represented by the general formula and a trace amount of additives, preferably the colloidal suspension contained in the liquid (Ca 1-X Ba X) SiO 3 However, components of the general formula of 0 ≦ X ≦ 1), the (Sr 1-X Ca X) m (Ti 1-Y Zr Y) O 2 + m ( where 0.55 ≦ X ≦ 0 .850 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) with respect to 100 moles of the main component powder represented by the general formula: 1.0 to 5.0 moles, and the additive Is (Sr 1−X Ca X ) m (Ti 1−Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1. 007) with respect to 100 mol of the main component powder represented by the general formula: Mn 3 O 4 is in the range of 0.05 to 2.0 mol, and V 2 O 5 is 0.01 to 0.3 mol. In the range, Al203 is in the range of 0.05 to 1.0 mol, CeO2 is in the range of 0.01 to 2.0 mol, and MgO is in the range of 0.01 to 0.2 mol.

本発明の実施において使用する(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末は、平均粒子径と粒子径分布の幅が小さいものが好ましい。また、反応性についてはそれが小さい方がCOG特性の発現が容易であるので、結晶化度の高い粉末を使用するのが好ましい。このような主成分の粉末を製造する工程において混入する不純物としては、ストロンチウム、カルシウム以外のアルカリ土類金属や鉄、珪素及びアル
ミニウム等があるが、これらの不純物は数千ppmのオーダで含有されていても特に支障はない。この(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85
0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末は、JIS規格COG特性(−55〜+125℃の温度範囲内で静電容量変化率0±30ppm/℃)を満足させる上において最も重要なものである。この化合物はSrTiO3−CaZrO3の各粉末、若しくはSrCO3−CaCO3−TiO2−ZrO2の各粉末から固相反応により合成される。具体的には、1100〜1300℃の仮焼温度で合成され、粉砕工程等を経由して本発明のセラミック電子部品である中高圧用積層セラミックコンデンサを製造する為に4.0〜7.0m2/gのBET値を有する粉末に調整される。
(Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m used in the practice of the present invention (provided that 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993) The powder of the main component represented by the general formula of ≦ m ≦ 1.007) preferably has a small average particle size and a narrow particle size distribution. In addition, it is preferable to use a powder having a high degree of crystallinity because the smaller the reactivity, the easier the expression of COG characteristics. Impurities mixed in the process of producing such a main component powder include alkaline earth metals other than strontium and calcium, iron, silicon and aluminum. These impurities are contained in the order of several thousand ppm. There is no particular problem. This (Sr 1−X Ca X ) m (Ti 1−Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85
The powder of the main component represented by the general formula of 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) is a JIS standard COG characteristic (capacitance change rate within a temperature range of −55 to + 125 ° C.). 0 ± 30 ppm / ° C.) is the most important. This compound is synthesized from each powder of SrTiO 3 —CaZrO 3 or each powder of SrCO 3 —CaCO 3 —TiO 2 —ZrO 2 by solid phase reaction. Specifically, in order to produce a multilayer ceramic capacitor for medium to high pressure, which is a ceramic electronic component of the present invention, synthesized at a calcination temperature of 1100 to 1300 ° C. and passing through a pulverization process or the like, 4.0 to 7.0 m Adjusted to a powder with a BET value of 2 / g.

主成分の粉末を混合するコロイド状懸濁液の出発材料であるCa及びBaの酢酸塩及びSiのアルコキシドは一般的市販品が使え、これらに含有される不純物は似通った化学的性質を有する金属であるため、前述の主成分と同様に数千ppmのオーダで含有されていても特に支障はない。また、アルコキシドを溶解させるエタノールも一般的な市販品が使用できる。   Ca and Ba acetates and Si alkoxides, which are starting materials for colloidal suspensions mixed with powders of main components, can be used as commercially available products, and impurities contained therein are metals having similar chemical properties. Therefore, even if it is contained in the order of several thousand ppm like the above-mentioned main component, there is no particular problem. Moreover, a general commercial item can also be used for ethanol in which the alkoxide is dissolved.

これら酢酸塩やアルコキシドは水−エタノール溶液中で水和したイオンとして存在し、後のアンモニア水の滴下によって微細な水酸化物をコロイド状懸濁液の形で生成し、これを主成分の粉末と混合した際、均一な状態で分散されるのが望ましい為、アンモニア水の濃度は1モル/リットル以下、工程の設備的、時間的余裕がある場合にはより低濃度にするのが望ましい。アンモニア水の濃度が1モル/リットルを超えて高濃度になると、前述の水酸化物が偏って生成し組成的に不均一な状態で主成分の粉末と混合されるため、最終的に組成不均一な耐還元性誘電体組成物となり、本発明の意図するところとは全く異なった結果となる。   These acetates and alkoxides exist as hydrated ions in a water-ethanol solution, and fine hydroxide is produced in the form of a colloidal suspension by the subsequent dropwise addition of aqueous ammonia, which is then used as the main powder. When mixed with, it is desirable that the aqueous ammonia be dispersed in a uniform state. Therefore, the concentration of ammonia water is 1 mol / liter or less, and it is desirable to lower the concentration when there is a sufficient facility and time for the process. When the concentration of ammonia water exceeds 1 mol / liter, the above-mentioned hydroxide is generated unevenly and mixed with the main component powder in a compositionally non-uniform state. The result is a uniform reduction resistant dielectric composition, which is completely different from what is intended by the present invention.

主成分である(Sr1-XCaXm(Ti1-YZrY)O2+mにおいて、xは、0.55≦X≦0.85の範囲である。Xが0.55未満ではJIS規格COG特性から逸脱し、またXが0.85を超えると誘電率が著しく低下する。Yは、0.80≦Y≦1.00の範囲である。Yが0.80未満ではQ値が低下し、自己発熱が大きくなる。さらに、mは、0.993≦m≦1.007の範囲である。mが0.993未満ではセラミック誘電体層において粒成長が助長されると同時に耐還元性が損なわれるため、Q値の低下および絶縁破壊電圧の劣化が生じる。また、mが1.007を超えるとセラミック誘電体層が難焼結となり、緻密な焼結体を得るのに高い焼結温度を有する。 In the main component (Sr 1−X Ca X ) m (Ti 1−Y Zr Y ) O 2 + m , x is in the range of 0.55 ≦ X ≦ 0.85. When X is less than 0.55, it deviates from the JIS standard COG characteristics, and when X exceeds 0.85, the dielectric constant is remarkably lowered. Y is in the range of 0.80 ≦ Y ≦ 1.00. When Y is less than 0.80, the Q value decreases and self-heating increases. Furthermore, m is in the range of 0.993 ≦ m ≦ 1.007. If m is less than 0.993, grain growth is promoted in the ceramic dielectric layer, and at the same time the reduction resistance is impaired, so that the Q value is lowered and the dielectric breakdown voltage is degraded. On the other hand, if m exceeds 1.007, the ceramic dielectric layer is difficult to sinter and has a high sintering temperature to obtain a dense sintered body.

(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して添加される各添加物の量は、中高圧用積層セラミックコンデンサの製品特性である誘電率、Q値、静電容量の温度変化率、絶縁抵抗、絶縁破壊電圧、高温負荷寿命、自己発熱及び焼成温度における耐還元性の観点から限定される。 (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (however, 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) The amount of each additive added to 100 moles of the main component powder represented by the general formula is a dielectric constant, a Q value, and a temperature change rate of capacitance, which are product characteristics of the multilayer ceramic capacitor for medium to high pressure In terms of insulation resistance, dielectric breakdown voltage, high temperature load life, self-heating, and reduction resistance at the firing temperature.

(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対してMn34が2.0モルを超えると静電容量の温度変化率が大きくなり、JIS規格COG特性から逸脱し、また0.05モル未満になると耐還元性が損なわれ、Q値が低下し、絶縁抵抗及び絶縁破壊電圧が劣化する。主成分の粉末100モルに対してV25が0.3モルを超えると耐還元性が損なわれ容易に還元され、絶縁抵抗及び絶縁破壊電圧が劣化し、また0.01モル未満になると高温負荷寿命が短くなる。主成分の粉末100モルに対してAl23が1.0モルを超えると難焼結性となり誘電率が低下し、また0.05モル未満になると高温負荷寿命が短くなる。主成分の粉末100モルに対してCeO2が2.0モルを超えると絶縁抵抗及び絶縁破壊電圧が劣化し、また0.01モル未満にな
ると高温負荷寿命が短くなる。主成分の粉末100モルに対してMgOが0.2モルを超えるとQ値が低下し、自己発熱が増大し、また0.01モル未満になると高温負荷寿命が短くなる。
(Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (however, 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) When Mn 3 O 4 exceeds 2.0 mol with respect to 100 mol of the main component powder represented by the general formula, the temperature change rate of the capacitance increases, deviating from the JIS standard COG characteristics, and 0. When it is less than 05 mol, the reduction resistance is impaired, the Q value is lowered, and the insulation resistance and the breakdown voltage are deteriorated. When V 2 O 5 exceeds 0.3 mol with respect to 100 mol of the main component powder, the reduction resistance is impaired and easily reduced, and the insulation resistance and breakdown voltage are deteriorated. High temperature load life is shortened. When Al 2 O 3 exceeds 1.0 mol with respect to 100 mol of the main component powder, it becomes difficult to sinter and the dielectric constant decreases, and when it is less than 0.05 mol, the high temperature load life is shortened. When CeO2 exceeds 2.0 moles with respect to 100 moles of the main component powder, the insulation resistance and breakdown voltage deteriorate, and when it is less than 0.01 moles, the high temperature load life is shortened. When MgO exceeds 0.2 mol with respect to 100 mol of the main component powder, the Q value decreases and self-heating increases, and when it is less than 0.01 mol, the high temperature load life is shortened.

さらに、(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される焼結助剤成分が5.0モルを超えると誘電率が低下すると共に高温負荷寿命が劣化し、また1.0モル未満になると焼結助剤成分としての効果が得られず焼成による緻密化が不完全となり同時にQ値が低下し、自己発熱が増大する。 Further, (Sr 1−X Ca X ) m (Ti 1−Y Zr Y ) O 2 + m (however, 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1. 007) with respect to 100 moles of the main component powder represented by the general formula (Ca 1-X Ba x ) SiO 3 (where 0 ≦ X ≦ 1) If it exceeds 5.0 mol, the dielectric constant decreases and the high-temperature load life deteriorates, and if it is less than 1.0 mol, the effect as a sintering aid component cannot be obtained and densification by firing becomes incomplete, and at the same time Q The value decreases and self-heating increases.

次に、本発明のセラミック電子部品の一つである中高圧用積層セラミックコンデンサの詳細な製造方法について説明する。   Next, a detailed manufacturing method of the multilayer ceramic capacitor for medium and high voltage which is one of the ceramic electronic components of the present invention will be described.

主成分である(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される粉末及び添加物であるMn34、V25、Al23、CeO2、MgOの各々の所定量を組成表に基づいて電子天秤で秤量し、5mmφのZrO2質ボールが350g入った内容積が600CCのポリエチレン製ポットミル中に投入する。次に、Ba、Caの酢酸塩及びTEOS(テトラエトキシシラン)の所定量を同じく組成表に基づいて電子天秤で秤量した後、酢酸塩は100CCの純水に、またTEOSは150CCのエタノールに別々に溶解させる。そして、酢酸塩水溶液をエタノール溶液中に投入して、プロペラ攪拌機で攪拌を続けながら1規定のアンモニア水を所定量滴下して、(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される焼結助剤成分を含むコロイド状懸濁液を得た。 (Sr 1−X Ca X ) m (Ti 1−Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦) A predetermined amount of each of Mn 3 O 4 , V 2 O 5 , Al 2 O 3 , CeO 2 , and MgO, which are powders represented by the general formula (1.007) and additives, is added to the electronic balance based on the composition table. Weigh and put into a polyethylene pot mill with an internal volume of 600 CC containing 350 g of 5 mmφ ZrO 2 quality balls. Next, after predetermined amounts of Ba, Ca acetate and TEOS (tetraethoxysilane) were weighed with an electronic balance based on the same composition table, acetate was separated into 100 CC pure water, and TEOS was separated into 150 CC ethanol. Dissolve in. Then, an aqueous acetate solution was put into the ethanol solution, and a predetermined amount of 1N ammonia water was dropped while continuing to stir with a propeller stirrer, and (Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ A colloidal suspension containing a sintering aid component represented by the general formula 1) was obtained.

次に、該コロイド状懸濁液を上記ポットミル中に投入し100rpmの回転速度で20時間混合した。混合物は150メッシュのシルクスクリーンで濾過して、テフロン(登録商標)シートを敷いたステンレスバット中に投入し、そして防爆型乾燥機を使用して120℃の温度で乾燥した。乾燥した塊状物はアルミナ乳鉢中で解砕した後、32メッシュのナイロン篩を通過してアルミナ製坩堝に入れて400℃/2時間の条件で熱処理してスラリー用粉末とした。   Next, the colloidal suspension was put into the pot mill and mixed for 20 hours at a rotation speed of 100 rpm. The mixture was filtered through a 150 mesh silk screen, placed in a stainless steel vat lined with a Teflon sheet, and dried at a temperature of 120 ° C. using an explosion proof dryer. The dried lump was crushed in an alumina mortar, passed through a 32 mesh nylon sieve, placed in an alumina crucible, and heat treated under conditions of 400 ° C./2 hours to obtain a slurry powder.

次に、スラリー用粉末を所定量の溶剤及び可塑剤と共に混合することにより湿潤した。湿潤後、ポリビニルブチラール樹脂より成るビヒクルを混合してシート成形用スラリーを作製した。   Next, the slurry powder was wetted by mixing with a predetermined amount of solvent and plasticizer. After wetting, a vehicle made of polyvinyl butyral resin was mixed to prepare a sheet forming slurry.

次に、該スラリーを150メッシュのシルクスクリーンで濾過した後、成膜してセラミック生シートを得た。そして、該セラミック生シートと、Niペーストより作製した内部電極シートを用いて転写工法により所定の積層仕様に基ずいて積層した後、切断してグリーンチップを得た。   Next, the slurry was filtered through a 150 mesh silk screen, and then formed into a film to obtain a ceramic raw sheet. Then, the ceramic raw sheet and an internal electrode sheet made of Ni paste were used for lamination based on a predetermined lamination specification by a transfer method, and then cut to obtain a green chip.

次に、得られたグリーンチップを面取りした後、その両端面に下層外部電極となるNiペーストを塗布し乾燥した後、脱脂した。そして、回転式雰囲気炉により還元雰囲気焼成を実施した。焼成は、グリーンガス、CO2及びN2により調整したNiの平衡酸素分圧よりも2桁程度低い酸素分圧雰囲気中で1250℃の温度で2時間保持した。そして、焼成したチップの両端面に上層外部電極となるAgペーストを塗布して大気中で焼き付けた後、Ni鍍金及びその上にSn鍍金を施すことにより(図1)に示した様な、本発明のセラミック電子部品の一つであるチップ型中高圧用積層セラミックコンデンサを得ることができる。 Next, after chamfering the obtained green chip, Ni paste used as a lower layer external electrode was applied to both end faces, dried, and then degreased. And reduction atmosphere baking was implemented with the rotary atmosphere furnace. Firing was held at a temperature of 1250 ° C. for 2 hours in an oxygen partial pressure atmosphere that was about two orders of magnitude lower than the equilibrium oxygen partial pressure of Ni adjusted with green gas, CO 2 and N 2 . Then, an Ag paste serving as an upper external electrode is applied to both end faces of the fired chip and baked in the air, and then Ni plating and Sn plating thereon are applied (FIG. 1). It is possible to obtain a chip-type medium / high voltage multilayer ceramic capacitor which is one of the ceramic electronic components of the invention.

また、前記チップ型中高圧用積層セラミックコンデンサ素子の両端面に導電性の金属端子を半田付けした後、該素子及び金属端子の主要な部分を熱硬化性樹脂で埋め込むことにより(図2)に示した様な、本発明のセラミック電子部品の一つであるモールド型中高圧用積層セラミックコンデンサを得ることができる。   Also, after soldering conductive metal terminals to both end faces of the chip-type medium- and high-voltage multilayer ceramic capacitor element, the main parts of the element and metal terminals are embedded with a thermosetting resin (FIG. 2). As shown, it is possible to obtain a mold type medium and high voltage multilayer ceramic capacitor which is one of the ceramic electronic components of the present invention.

さらに、前記チップ型中高圧用積層セラミックコンデンサ素子の両端面に導電性のリード線を半田付けした後、該素子及びリード線の主要な部分を外装材で被覆することにより図3に示した様な、本発明のセラミック電子部品の一つであるリード型中高圧用積層セラミックコンデンサを得ることができる。   Further, after soldering conductive lead wires to both end faces of the chip-type medium- and high-voltage multilayer ceramic capacitor element, the main part of the element and the lead wires are covered with an exterior material as shown in FIG. In addition, a lead-type medium / high voltage multilayer ceramic capacitor, which is one of the ceramic electronic components of the present invention, can be obtained.

この様にして得られたセラミック電子部品の一つである中高圧用積層セラミックコンデンサは、そのセラミック誘電体層が限定された耐還元性誘電体組成物により構成されており、しかもその微細構造が非常に均一で緻密な組織を有しているため、Q値が非常に高く、静電容量温度変化率がJIS規格COG特性を満足し、高周波電流下において自己発熱が小さく、中高圧用として耐久信頼性に優れており、LCDを構成しているバックライトのインバータ電源回路等の主として高周波高パルスが印加される回路に適用される。また、本発明の中高圧用積層セラミックコンデンサは、その形状がチップ型、モールド型及びリード型としてそれぞれの構造上の特徴を生かしてユーザの要望に応じた使い分けが可能である。   One of the ceramic electronic components obtained in this way is a multilayer ceramic capacitor for medium and high voltage, which has a ceramic dielectric layer made of a limited reduction-resistant dielectric composition, and has a fine structure. Because it has a very uniform and dense structure, the Q value is very high, the rate of change in capacitance temperature satisfies the JIS standard COG characteristics, self-heating is small under high-frequency current, and it is durable for medium- and high-pressure applications. It is excellent in reliability and is applied mainly to a circuit to which a high frequency high pulse is applied, such as an inverter power supply circuit of a backlight constituting an LCD. Further, the multilayer ceramic capacitor for medium and high voltage of the present invention can be used properly according to the user's request by taking advantage of the structural features of the chip type, mold type and lead type.

次に本発明の具体例を説明する。   Next, specific examples of the present invention will be described.

(実施例1)
実験の手順は(表1)に示した組成表に従って、主成分である(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される粉末(共立マテリアル製)及び添加物であるMn34、V25、Al23、CeO2、MgOの各々の所定量を電子天秤で秤量した配合物と、Ba、Ca及びSiより成る焼結助剤成分を含むコロイド状懸濁液をポットミルで混合して各々の出発原料粉末を作製する。なお、本実施例1における、焼結助剤成分の組成は(Ba0.6Ca0.4)SiO3である。
(Example 1)
The experimental procedure is (Sr 1 -X Ca X ) m (Ti 1 -Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0) according to the composition table shown in (Table 1). .85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) and powders (manufactured by Kyoritsu Materials Co., Ltd.) and additives Mn 3 O 4 , V 2 O 5 , Al 2 O 3 , a mixture obtained by weighing a predetermined amount of each of CeO 2 and MgO with an electronic balance and a colloidal suspension containing a sintering aid component composed of Ba, Ca and Si by a pot mill, Make a powder. The composition of the sintering aid component in Example 1 is (Ba 0.6 Ca 0.4 ) SiO 3 .

次に、作製した粉末を使用して、テストサンプルとして(図1)に示したような形状が3216サイズのNi内部電極チップ型積層セラミックコンデンサを試作して総合評価するものである。   Next, using the produced powder, a Ni internal electrode chip type multilayer ceramic capacitor having a 3216 size shape as shown in FIG. 1 as a test sample is produced and comprehensively evaluated.

なお、テストサンプルであるNi内部電極チップ型積層セラミックコンデンサの製造方法は、前記実施の形態において示した一連の手順と同じである。   The manufacturing method of the Ni internal electrode chip type multilayer ceramic capacitor as the test sample is the same as the series of procedures shown in the above embodiment.

以下に、試作したNi内部電極チップ型積層セラミックコンデンサの評価項目及び評価方法について説明する。   The evaluation items and evaluation method of the prototype Ni internal electrode chip type multilayer ceramic capacitor will be described below.

静電容量(Cap)とQ値はYHP製LCRメータ4284Aを使用して1V/1MHzの信号電圧下で測定した。誘電率は測定した静電容量(Cap)値と試作したNi内部電極チップ型積層セラミックコンデンサのセラミック誘電体層の厚み及び対向電極面積より算出した。絶縁抵抗値(IR)はアドバンテスト社製絶縁抵抗計R8340Aを使用して500VDCを1分間印加して測定した。絶縁破壊電圧(BDV)は菊水電子製耐圧計を使用してシリコーン油中で直流破壊電圧を測定した。静電容量の温度変化率(Cap−TC)は恒温槽にYHP製LCRメータ4284Aを接続して0〜+125℃の範囲内で測定した。自己発熱は高周波電源を使用してコイルのインダクタンスLとコンデンサの静
電容量Capによる共振回路を応用して200KHzの周波数で共振させながら徐々に昇圧して2KVの電圧で測定した。また、信頼性評価の一環として、125℃の温度で2.0KVDCの電圧を印加して高温負荷試験を実施した。
Capacitance (Cap) and Q value were measured using a YHP LCR meter 4284A under a signal voltage of 1 V / 1 MHz. The dielectric constant was calculated from the measured capacitance (Cap) value, the thickness of the ceramic dielectric layer of the prototype Ni internal electrode chip type multilayer ceramic capacitor, and the counter electrode area. The insulation resistance value (IR) was measured by applying 500 VDC for 1 minute using an insulation resistance meter R8340A manufactured by Advantest Corporation. With respect to the dielectric breakdown voltage (BDV), a DC breakdown voltage was measured in silicone oil using a pressure gauge made by Kikusui Electronics. The rate of change in capacitance temperature (Cap-TC) was measured within the range of 0 to + 125 ° C. by connecting a YHP LCR meter 4284A to a thermostat. Self-heating was measured at a voltage of 2 KV by gradually increasing the voltage while resonating at a frequency of 200 KHz by applying a resonance circuit using a coil inductance L and a capacitance Cap of the capacitor using a high frequency power source. As part of the reliability evaluation, a high temperature load test was performed by applying a voltage of 2.0 KVDC at a temperature of 125 ° C.

静電容量とQ値は各々20個測定に供し、絶縁抵抗値と絶縁破壊電圧は各々10個、静電容量の温度変化率と自己発熱は各々2個測定し、平均値を算出した。また、高温負荷試験は、各組成物により試作したテストサンプルを各々20個ずつ専用の基板に半田付け実装した後、前記条件下で実施し、1000時間に至るまでに3個以上破壊したものをNGとした。   The capacitance and Q value were each measured for 20 pieces, the insulation resistance value and the dielectric breakdown voltage were each 10 pieces, the temperature change rate of the capacitance and the self-heating two pieces were measured, and the average value was calculated. The high-temperature load test was performed by soldering and mounting 20 test samples, each prototyped with each composition, on a dedicated substrate, and then destroying 3 or more samples by 1000 hours. NG.

Figure 2005213126
Figure 2005213126

これら一連の測定結果を(表2)に示した。   These series of measurement results are shown in Table 2.

ここで、(表2)のRunNo.は(表1)のRunNo.に対応している。また、(表2)中のRunNo.に※印を記したものは、評価項目の内少なくとも1つについて良好な結果が得られなかったテストサンプルであり、本発明範囲外の耐還元性誘電体組成物である。   Here, in Run No. of (Table 2). (Run No. in Table 1). It corresponds to. In addition, Run No. in (Table 2). Those marked with * are test samples in which good results were not obtained for at least one of the evaluation items, and are reduction-resistant dielectric compositions outside the scope of the present invention.

Figure 2005213126
Figure 2005213126

(表1)及び(表2)より明らかな様に、主成分である(Sr1-XCaXm(Ti1-YZrY)O2+mにおいて、モル比Xが0.55未満では+125℃における静電容量の温度変化率が大きくなり、JIS規格COG特性から逸脱し、絶縁抵抗値及びQ値が低下傾向にあり、またモル比Xが0.85を超えると誘電率が急激に低下した。モル比Yが0.80未満ではQ値の低下とともに自己発熱が増大した。さらに、モル比mが0.993未満ではセラミック誘電体層において粒成長が著しくなり同時に耐還元性が損なわれる為、Q値が低下して、さらに絶縁破壊電圧が劣化した。また、mが1.007を超えるとセラミック誘電体層が難焼結性となり、緻密質なセラミック誘電体層が形成されにくく、誘電率が低下した。 (Table 1) and (Table 2) As is clear from the main component in (Sr 1-X Ca X) m (Ti 1-Y Zr Y) O 2 + m, the molar ratio X is less than 0.55 In this case, the rate of change in capacitance at + 125 ° C. increases, deviates from the JIS standard COG characteristics, and the insulation resistance value and Q value tend to decrease, and when the molar ratio X exceeds 0.85, the dielectric constant increases rapidly. Declined. When the molar ratio Y was less than 0.80, self-heating increased as the Q value decreased. Further, when the molar ratio m is less than 0.993, grain growth is remarkable in the ceramic dielectric layer, and at the same time, the reduction resistance is impaired. Therefore, the Q value is lowered and the dielectric breakdown voltage is further deteriorated. When m exceeded 1.007, the ceramic dielectric layer became difficult to sinter, a dense ceramic dielectric layer was hardly formed, and the dielectric constant was lowered.

(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、X=0.698 Y=0.972 m=0.998)で表される主成分の粉末100モルに対してMn34が2.0モルを超えると静電容量の温度変化率が大きくなり、また0.05モル未満になると耐還元性が損なわれ、Q値が低下し、絶縁抵抗及び絶縁破壊電圧が劣化し、自己発熱が増大し、高温負荷寿命が悪化した。前記、主成分の粉末100モルに対してAL23が1.0モルを超えると誘電率が急激に低下し、Q値と絶縁抵抗が劣化傾向にあり、また0.05未満になる
と高温負荷寿命試験において不具合が発生した。前記、主成分の粉末100モルに対してCeO2が2.0モルを超えると絶縁抵抗および絶縁破壊電圧が低下し、また0.01モル未満になると高温負荷寿命試験において不具合が発生した。前記、主成分の粉末100モルに対してMgOが0.2モルを超えるとQ値が低下し、自己発熱が増大し、また0.01モル未満になると高温負荷寿命が短くなる。前記、主成分の粉末100モルに対してV25が0.3モルを超えると耐還元性が損なわれ容易に還元され、絶縁抵抗及び絶縁破壊電圧が劣化し、また0.01モル未満になると高温負荷寿命が短くなる。
100 mol of the main component powder represented by (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (where X = 0.698 Y = 0.972 m = 0.998) On the other hand, when Mn 3 O 4 exceeds 2.0 mol, the rate of change in capacitance temperature increases, and when it is less than 0.05 mol, the reduction resistance is impaired, the Q value decreases, the insulation resistance and Dielectric breakdown voltage deteriorated, self-heating increased, and high temperature load life deteriorated. When AL 2 O 3 exceeds 1.0 mol with respect to 100 mol of the main component powder, the dielectric constant decreases rapidly, and the Q value and the insulation resistance tend to deteriorate. A failure occurred in the load life test. When CeO 2 exceeds 2.0 mol with respect to 100 mol of the main component powder, the insulation resistance and dielectric breakdown voltage are lowered, and when it is less than 0.01 mol, problems occur in the high temperature load life test. When MgO exceeds 0.2 mol with respect to 100 mol of the main component powder, the Q value decreases and self-heating increases, and when it is less than 0.01 mol, the high temperature load life is shortened. When V 2 O 5 exceeds 0.3 mol with respect to 100 mol of the main component powder, the reduction resistance is impaired and easily reduced, the insulation resistance and the breakdown voltage are deteriorated, and less than 0.01 mol If it becomes, the high temperature load life will become short.

さらに、(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、X=0.698 Y=0.972 m=0.998)の一般式で表される主成分の粉末100モルに対して(Ca0.4Ba0.6)SiO3の一般式で表される焼結助剤成分が5.0モルを超えると誘電率が低下すると共に高温負荷寿命が劣化し、また1.0モル未満になると焼結助剤成分としての効果が得られず焼成による緻密化が不完全となり同時にQ値が低下し、自己発熱が増大した。 Further, (Sr 1−X Ca X ) m (Ti 1−Y Zr Y ) O 2 + m (where X = 0.698 Y = 0.972 m = 0.998) When the sintering aid component represented by the general formula of (Ca 0.4 Ba 0.6 ) SiO 3 exceeds 5.0 moles with respect to 100 moles of the component powder, the dielectric constant decreases and the high temperature load life deteriorates. When the amount was less than 1.0 mol, the effect as a sintering aid component was not obtained, and densification by firing became incomplete, and at the same time, the Q value was lowered and self-heating was increased.

これに対して、本発明範囲内の耐還元性誘電体組成物により作製したNi内部電極チップ型積層セラミックコンデンサは、良好な焼結性と耐還元性とを有し、静電容量の温度変化率がJIS規格COG特性を満足すると同時に中高圧用としての用途に適した電気特性を有し、高周波電流下における自己発熱が小さく、耐久信頼性に優れたものであった。   On the other hand, the Ni internal electrode chip type multilayer ceramic capacitor produced by the reduction-resistant dielectric composition within the scope of the present invention has good sinterability and reduction resistance, and the capacitance changes with temperature. The rate satisfied the JIS standard COG characteristics, and at the same time had electrical characteristics suitable for medium- and high-pressure applications, small self-heating under high-frequency current, and excellent durability and reliability.

以上の様に、本発明の耐還元性誘電体組成物によれば、LCDを構成しているバックライトのインバータ電源等の高周波高パルスが印加される回路に最適な高Q値、低発熱の中高圧用チップ型積層セラミックコンデンサに代表されるセラミック電子部品を実現することが可能である。   As described above, according to the reduction-resistant dielectric composition of the present invention, the high Q value and low heat generation optimum for a circuit to which a high frequency high pulse is applied, such as an inverter power supply of a backlight constituting an LCD. It is possible to realize a ceramic electronic component typified by a medium-high voltage chip type multilayer ceramic capacitor.

(実施例2)
(表1)中のRunNo.3の組成に従って、主成分である(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、X=0.698 Y=0.972 m=0.998)の一般式で表される粉末(共立マテリアル製)及び添加物であるMn34、V25、Al23、CeO2、MgOの各々の所定量を電子天秤で秤量した配合物と、Ba、Ca及びSiより成る焼結助剤成分を含むコロイド状懸濁液をポットミルで混合して各々の出発原料粉末を作製する。なお、本実施例2における、焼結助剤成分の組成は(Ba0.6Ca0.4)SiO3である。
(Example 2)
Run No. in Table 1 (Sr 1−X Ca X ) m (Ti 1−Y Zr Y ) O 2 + m (where X = 0.698 Y = 0.972 m = 0.998) A powder of a general formula (made by Kyoritsu Material) and a composition in which a predetermined amount of each of Mn 3 O 4 , V 2 O 5 , Al 2 O 3 , CeO 2 and MgO as additives is weighed with an electronic balance; Colloidal suspensions containing sintering aid components consisting of Ba, Ca and Si are mixed in a pot mill to prepare each starting material powder. The composition of the sintering aid component in Example 2 is (Ba 0.6 Ca 0.4 ) SiO 3 .

次に、作製した粉末を使用して、前記実施の形態において記載した手順でチップ型中高圧用積層セラミックコンデンサ素子を作製した。   Next, using the prepared powder, a chip-type medium / high pressure multilayer ceramic capacitor element was manufactured according to the procedure described in the above embodiment.

次に、該チップ型中高圧用積層セラミックコンデンサ素子の両端面に金属端子を半田付けした後、該素子及び金属端子の主要な部分をエポキシ系の熱硬化性樹脂で埋め込むことにより(図2)に示した様な、本発明のセラミック電子部品の一つであるモールド型中高圧用積層セラミックコンデンサを作製した。   Next, after soldering metal terminals to both end faces of the chip-type medium / high voltage multilayer ceramic capacitor element, the main part of the element and the metal terminal are embedded with an epoxy-based thermosetting resin (FIG. 2). As shown in the above, a mold type medium-high voltage multilayer ceramic capacitor, which is one of the ceramic electronic components of the present invention, was produced.

作製した本実施例2のモールド型積層セラミックコンデンサは、(図2)に示したように(Sr0.302Ca0.6980.998(Ti0.028Zr0.972)O2.998質セラミック誘電体層23とNiを含む内部電極層22a、22b、22cとを交互に積層して形成された静電容量取得層となる有効層の上下に無効層として(Sr0.302Ca0.6980.998(Ti0.028Zr0.972)O2.998質セラミック誘電体層23が積層されて積層体21が形成されており、該積層体21の両端部に前記内部電極層22b、22cと電気的に接合されたNi質下層外部電極24が設けられ、その上にAg質上層外部電極25が設けられていた。そして、熱硬化性樹脂26に埋込まれた積層体21の両端部から導電性の金属端子27が引出され
、該金属端子27を介して回路基板に表面実装できるように構成されている。
The produced mold type multilayer ceramic capacitor of Example 2 has (Sr 0.302 Ca 0.698 ) 0.998 (Ti 0.028 Zr 0.972 ) O 2.998 quality ceramic dielectric layer 23 and an internal electrode containing Ni as shown in FIG. (Sr 0.302 Ca 0.698 ) 0.998 (Ti 0.028 Zr 0.972 ) O 2.998 quality ceramic dielectric as an ineffective layer above and below the effective layer to be a capacitance acquisition layer formed by alternately laminating layers 22a, 22b and 22c A layered body 21 is formed by laminating the layers 23, and Ni-based lower layer external electrodes 24 electrically connected to the internal electrode layers 22b and 22c are provided at both ends of the layered body 21, on which the layered body 21 is formed. An Ag quality upper layer external electrode 25 was provided. Then, conductive metal terminals 27 are drawn out from both end portions of the laminate 21 embedded in the thermosetting resin 26 and can be surface-mounted on the circuit board via the metal terminals 27.

次に、本実施例2のモールド型積層セラミックコンデンサのたわみ強度を測定した。たわみ強度は表面実装用電子部品の信頼性を判断する為の重要な評価項目であり、専用のプリント基板に被試験品を半田付けした後、専用の治具で3点曲げを付加させながら静電容量を測定し、静電容量値が急激に低下した時点での基板のたわみ幅(mm)をたわみ強度とするものである。通常、静電容量値が急激に低下した時点で被試験品に亀裂が発生している場合が多い。本実施例2のモールド型積層セラミックコンデンサの場合、たわみ幅が15mmを越えても静電容量値の低下がなく安定していた。同時に、実施例1のチップ型積層セラミックコンデンサの場合、たわみ幅(mm)が6mmで静電容量値が急激に低下して亀裂が発生した被試験品が見られた。たわみ強度の規格は最小値が2.0mmであるため双方共全く問題のないレベルであるが、明らかにモールド型の方が優れていた。   Next, the bending strength of the mold type multilayer ceramic capacitor of Example 2 was measured. Deflection strength is an important evaluation item for judging the reliability of electronic components for surface mounting. After soldering the product under test to a dedicated printed circuit board, it is statically added with a 3-point bend using a dedicated jig. The capacitance is measured, and the deflection width (mm) of the substrate at the time when the capacitance value suddenly decreases is defined as the deflection strength. Usually, there are many cases in which a crack is generated in a product under test at the time when the capacitance value suddenly decreases. In the case of the mold type multilayer ceramic capacitor of Example 2, the capacitance value did not decrease and was stable even when the deflection width exceeded 15 mm. At the same time, in the case of the chip-type multilayer ceramic capacitor of Example 1, there was a product to be tested in which the deflection width (mm) was 6 mm and the capacitance value suddenly decreased and cracks occurred. Since the minimum value of the flexure strength standard is 2.0 mm, both are at a level where there is no problem, but the mold type was clearly superior.

また、実施例1のチップ型積層セラミックコンデンサは、規格外の異常電圧に対して、積層体表面の結露等が原因となり沿面リークが発生することがあるが、本実施例2のモールド型積層セラミックコンデンサは、その可能性がなく耐久信頼性の高いものである。   Further, the chip-type multilayer ceramic capacitor of Example 1 may cause creeping leakage due to condensation on the surface of the multilayer body with respect to abnormal voltage outside the standard, but the mold-type multilayer ceramic of Example 2 The capacitor has no possibility and has high durability and reliability.

以上の様に、本発明のモールド型積層セラミックコンデンサは、素子及び金属端子の主要な部分がエポキシ系の熱硬化性樹脂で埋め込まれた構造であるため、中高圧用として高い信頼性と優れた表面実装性を実現することができ、液晶ディスプレイパネル(LCD)を構成しているバックライトのインバータ電源回路、及び低歪み率が要求される通信用デジタルモデムの対サージ回路等に最適なものである。   As described above, the mold-type multilayer ceramic capacitor of the present invention has a structure in which the main parts of the element and the metal terminal are embedded with an epoxy-based thermosetting resin, and thus has high reliability and excellent for medium and high pressure applications. It can achieve surface mountability and is ideal for inverter power supply circuits for backlights that make up liquid crystal display panels (LCDs) and surge circuits for communication digital modems that require low distortion. is there.

本発明の耐還元性誘電体組成物は、Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造したものである。これにより、Ca、Ba及びSiを含有するコロイド状懸濁液の均一分散が達成され、主成分であるSrTiO3−CaZrO3系固溶体粒子の周囲がこれらの成分により均一にコーティングされる為、焼成時に局部的な異常反応がなく焼結助剤成分が均一に分散された非常に緻密な組織を形成することが可能な耐還元性誘電体組成物により、焼成時に局部的な異常反応がなく焼結助剤成分が均一に分散された非常に緻密な組織を有するセラミック誘電体層が形成されるため、中高圧用として良好な電気特性と耐久信頼性を有するNi内部電極積層セラミックコンデンサを実現することが必要な用途にも適用できる。 The reduction-resistant dielectric composition of the present invention is prepared by dropping ammonia water while stirring and mixing at least one acetate aqueous solution of Ca and Ba and a metal alkoxide ethanol solution of Si (Ca 1-X Ba X ). A step of preparing a colloidal suspension containing a component represented by the general formula of SiO 3 (where 0 ≦ X ≦ 1), and the colloidal suspension is (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) And a step of producing a raw material powder by mixing together with a small amount of additives. Thereby, uniform dispersion of the colloidal suspension containing Ca, Ba and Si is achieved, and the periphery of the main component SrTiO 3 —CaZrO 3 solid solution particles is uniformly coated with these components. A reduction-resistant dielectric composition capable of forming a very dense structure in which the sintering aid component is uniformly dispersed sometimes without any local abnormal reaction. A ceramic dielectric layer having a very dense structure in which the binder component is uniformly dispersed is formed, thereby realizing a Ni internal electrode multilayer ceramic capacitor having good electrical characteristics and durability reliability for medium and high pressure. It can also be applied to applications where this is necessary.

本発明のセラミック電子部品の一実施例を示す断面図Sectional drawing which shows one Example of the ceramic electronic component of this invention 本発明のセラミック電子部品の一実施例を示す断面図Sectional drawing which shows one Example of the ceramic electronic component of this invention 本発明のセラミック電子部品の一実施例を示す断面図Sectional drawing which shows one Example of the ceramic electronic component of this invention

符号の説明Explanation of symbols

11、21、31 積層体
12a、12b、12c、22a、22b、22c、32a、32b、32c 内部電極層
13、23、33 セラミック誘電体層
14、24、34 Ni質下層外部電極
15、25、35 Ag質上層外部電極
26 熱硬化性樹脂
27 端子
36 外装材
37 リード線
38 半田
11, 21, 31 Laminate 12a, 12b, 12c, 22a, 22b, 22c, 32a, 32b, 32c Internal electrode layer 13, 23, 33 Ceramic dielectric layer 14, 24, 34 Ni-based lower external electrode 15, 25, 35 Ag upper external electrode 26 Thermosetting resin 27 Terminal 36 Exterior material 37 Lead wire 38 Solder

Claims (8)

Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造したことを特徴とする耐還元性誘電体組成物。 While stirring and mixing at least one of an aqueous acetate solution of Ca and Ba and a metal alkoxide ethanol solution of Si, ammonia water is added dropwise (Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ 1). a step of preparing a colloidal suspension containing a component represented by the general formula, the colloidal suspension (Sr 1-X Ca X) m (Ti 1-Y Zr Y) O 2 + m ( where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) and mixed with the main component powder represented by the general formula and a small amount of additives A reduction-resistant dielectric composition characterized by being manufactured by sequentially performing the manufacturing process. Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造した耐還元性誘電体組成物において、前記コロイド状懸濁液に含まれる(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分は、前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して、1.0〜5.0モルの範囲内であることを特徴とする耐還元性誘電体組成物。 While stirring and mixing at least one of an aqueous acetate solution of Ca and Ba and a metal alkoxide ethanol solution of Si, ammonia water is added dropwise (Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ 1). a step of preparing a colloidal suspension containing a component represented by the general formula, the colloidal suspension (Sr 1-X Ca X) m (Ti 1-Y Zr Y) O 2 + m ( where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) and mixed with the main component powder represented by the general formula and a small amount of additives In the reduction-resistant dielectric composition manufactured by sequentially performing the manufacturing steps, (Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ 1) contained in the colloidal suspension ingredient of the formula, the (Sr 1-X Ca X) m (Ti 1-Y Zr Y) O 2 + m ( 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) with respect to 100 moles of the main component powder represented by the general formula A reduction-resistant dielectric composition characterized by being in the range of 0.0 mol. Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造した耐還元性誘電体組成物において、前記添加物は、前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して、各々Mn34が0.05〜2.0モルの範囲内、V25が0.01〜0.3モルの範囲内、Al23が0.05〜1.0モルの範囲内、CeO2が0.01〜2.0モルの範囲内、及びMgOが0.01〜0.2モルの範囲内であることを特徴とする耐還元性誘電体組成物。 While stirring and mixing at least one of an aqueous acetate solution of Ca and Ba and a metal alkoxide ethanol solution of Si, ammonia water is added dropwise (Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ 1). a step of preparing a colloidal suspension containing a component represented by the general formula, the colloidal suspension (Sr 1-X Ca X) m (Ti 1-Y Zr Y) O 2 + m ( where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) and mixed with the main component powder represented by the general formula and a small amount of additives In the reduction-resistant dielectric composition manufactured by sequentially performing the manufacturing process, the additive is the (Sr 1-X Ca X ) m (Ti 1-Y Zr Y ) O 2 + m (where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) Against powder 100 moles of the main component that, each Mn 3 O 4 is in the range of 0.05 to 2.0 mole, V 2 O 5 in the range of 0.01 to 0.3 mol, Al 2 0 3 In a range of 0.05 to 1.0 mol, CeO 2 in a range of 0.01 to 2.0 mol, and MgO in a range of 0.01 to 0.2 mol. A reducing dielectric composition. Ca及びBaのうち少なくとも一種以上の酢酸塩水溶液とSiの金属アルコキシドエタノール溶液を撹拌混合しながらアンモニア水を滴下して(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分を含むコロイド状懸濁液を作製する工程と、該コロイド状懸濁液を(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末及び微量の添加物と共に混合して原料粉末を作製する工程とを順次行うことにより製造した耐還元性誘電体組成物において、前記コロイド状懸濁液に含まれる(Ca1-XBaX)SiO3(但し、0≦X≦1)の一般式で表される成分は、前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して、1.0〜5.0モルの範囲内であることを特徴とし、さらに前記添加物は、前記(Sr1-XCaXm(Ti1-YZrY)O2+m(但し、0.55≦X≦0.85 0.80≦Y≦1.00 993≦m≦1.007)の一般式で表される主成分の粉末100モルに対して、各々Mn34が0.05〜2.0モルの範囲内、V25が0.01〜0.3モルの範囲内、Al203が0.05〜1.0モルの範囲内、CeO2が0.01〜2.0モルの範囲内、及びMg
Oが0.01〜0.2モルの範囲内であることを特徴とする耐還元性誘電体組成物。
While stirring and mixing at least one of an aqueous acetate solution of Ca and Ba and a metal alkoxide ethanol solution of Si, ammonia water is added dropwise (Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ 1). a step of preparing a colloidal suspension containing a component represented by the general formula, the colloidal suspension (Sr 1-X Ca X) m (Ti 1-Y Zr Y) O 2 + m ( where 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) and mixed with the main component powder represented by the general formula and a small amount of additives In the reduction-resistant dielectric composition manufactured by sequentially performing the manufacturing steps, (Ca 1-X Ba X ) SiO 3 (where 0 ≦ X ≦ 1) contained in the colloidal suspension ingredient of the formula, the (Sr 1-X Ca X) m (Ti 1-Y Zr Y) O 2 + m ( 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) with respect to 100 moles of the main component powder represented by the general formula In the range of 0.0 mol, the additive may be (Sr 1−X Ca X ) m (Ti 1−Y Zr Y ) O 2 + m (provided that 0.55 ≦ X ≦ 0.85 0.80 ≦ Y ≦ 1.00 993 ≦ m ≦ 1.007) with respect to 100 moles of the main component powder represented by the general formula, 0.05 to 2.0 Mn 3 O 4 respectively. the range of mole, in the range V 2 O 5 is 0.01 to 0.3 mol, Al203 in the range of 0.05 to 1.0 mol, the range CeO2 is 0.01 to 2.0 mole, And Mg
A reduction-resistant dielectric composition, wherein O is in the range of 0.01 to 0.2 mol.
第1の複数のセラミック誘電体層の間にNi或いはNiを主成分とする合金よりなる内部電極層を設けた有効層及び第2の複数のセラミック誘電体層より成る無効層を有した基体と、前記基体の両端部から側部に至るように設けられ、前記内部電極層と電気的に接合された一対の外部電極とを備えたチップ型のセラミック電子部品であり、前記セラミック誘電体層を請求項1〜4いずれか1記載の耐還元性誘電体組成物で構成したことを特徴とするセラミック電子部品。 A base having an effective layer in which an internal electrode layer made of Ni or an alloy containing Ni as a main component is provided between the first plurality of ceramic dielectric layers, and an ineffective layer made of the second plurality of ceramic dielectric layers; A chip-type ceramic electronic component provided with a pair of external electrodes provided so as to extend from both ends to the side of the base body and electrically connected to the internal electrode layer, the ceramic dielectric layer being A ceramic electronic component comprising the reduction-resistant dielectric composition according to any one of claims 1 to 4. 第1の複数のセラミック誘電体層の間にNi或いはNiを主成分とする合金よりなる内部電極層を設けた有効層及び第2の複数のセラミック誘電体層より成る無効層を有した基体と、前記基体の両端部から側部に至るように設けられ、前記内部電極層と電気的に接合された一対の外部電極と、前記外部電極にそれぞれ接続された端子とを備え、前記基体及び外部電極が樹脂により埋め込まれたモールド型のセラミック電子部品であり、前記セラミック誘電体層を請求項1〜4いずれか1記載の耐還元性誘電体組成物で構成したことを特徴とするセラミック電子部品。 A base having an effective layer in which an internal electrode layer made of Ni or an alloy containing Ni as a main component is provided between the first plurality of ceramic dielectric layers, and an ineffective layer made of the second plurality of ceramic dielectric layers; A pair of external electrodes provided so as to extend from both ends of the base to the side and electrically joined to the internal electrode layer, and terminals connected to the external electrodes, respectively, 5. A ceramic electronic component having an electrode embedded with a resin, wherein the ceramic dielectric layer is composed of the reduction-resistant dielectric composition according to any one of claims 1 to 4. . 第1の複数のセラミック誘電体層の間にNi或いはNiを主成分とする合金よりなる内部電極層を設けた有効層及び第2の複数のセラミック誘電体層より成る無効層を有した基体と、前記基体の両端部から側部に至るように設けられ、前記内部電極層と電気的に接合された一対の外部電極と、前記外部電極にそれぞれ接続されたリード線とを備え、前記基体及び外部電極が樹脂により被覆されたリード型のセラミック電子部品であり、前記セラミック誘電体層を請求項1〜4いずれか1記載の耐還元性誘電体組成物で構成したことを特徴とするセラミック電子部品。 A base having an effective layer in which an internal electrode layer made of Ni or an alloy containing Ni as a main component is provided between the first plurality of ceramic dielectric layers, and an ineffective layer made of the second plurality of ceramic dielectric layers; A pair of external electrodes provided so as to extend from both ends of the base to the side and electrically joined to the internal electrode layer, and lead wires respectively connected to the external electrodes, A lead-type ceramic electronic component in which an external electrode is coated with a resin, and the ceramic dielectric layer is composed of the reduction-resistant dielectric composition according to any one of claims 1 to 4. parts. 前記外部電極は上層、下層の二層構造であり、下層は前記基体の端面のみに設けたことを特徴とする請求項5〜7いずれか1記載のセラミック電子部品。 8. The ceramic electronic component according to claim 5, wherein the external electrode has a two-layer structure of an upper layer and a lower layer, and the lower layer is provided only on an end surface of the base.
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JP2002252138A (en) * 2001-02-22 2002-09-06 Matsushita Electric Ind Co Ltd Reduction-resistant dielectric ceramic, its manufacturing method, and laminated ceramic capacitor using the same

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US7133274B2 (en) 2005-01-20 2006-11-07 Matsushita Electric Industrial Co., Ltd. Multilayer capacitor and mold capacitor
JP2011195347A (en) * 2010-03-17 2011-10-06 Murata Mfg Co Ltd Dielectric ceramic composition and laminated capacitor for temperature compensation
US8472161B2 (en) 2010-03-17 2013-06-25 Murata Manufacturing Co., Ltd. Dielectric ceramic composition and temperature compensation laminated capacitor
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WO2016157954A1 (en) * 2015-03-27 2016-10-06 株式会社村田製作所 Dielectric material production method
WO2016157952A1 (en) * 2015-03-27 2016-10-06 株式会社村田製作所 Method for producing dielectric material
JPWO2016157954A1 (en) * 2015-03-27 2018-02-01 株式会社村田製作所 Method for manufacturing dielectric material

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