JP2005208261A - Electrooptical apparatus, its driving circuit and driving method, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently remove residual charges by a simple configuration. <P>SOLUTION: The electrooptical apparatus 10 has pixels 116 which are disposed in correspondence to the respective intersections of a plurality of scanning lines 312 and a plurality of data lines 212, a scanning line driving circuit 350 which selects the respective scanning lines 312 a plurality of times and applies a selection voltage thereto in an off-sequence period after a display stop signal Soff instructing the stop of driving of the pixels 116 is inputted, a control circuit 400 and voltage generation circuit 500 which make the selection voltage to be applied to the respective scanning lines 312 by the scanning line driving circuit 350 lower with lapse of time in the off-sequence period, and a data line driving circuit 250 which applies the voltage meeting the gradation of the pixels 116 corresponding to the intersections of the data lines 212 and the scanning lines 312 selected by the scanning line driving circuit 350 to each of the plurality of data lines 212 and on the other hand, applies a non-lighting voltage to respective data lines 212 in the off-sequence period. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a technique for removing charges accumulated in each of a plurality of pixels when image display is stopped.

  An electro-optical device using an electro-optical material such as liquid crystal has a configuration in which a large number of pixels each having an electro-optical material and an electrode for applying an electric field thereto are arranged in a planar shape. In this type of electro-optical device, if charges remain on the electrodes of each pixel even after image display is stopped, a DC voltage may continue to be applied to the electro-optical material, leading to degradation of its optical characteristics. In order to solve this problem, for example, in Patent Document 1, when an instruction to stop display is made, the electrodes of each pixel are connected to a predetermined fixed potential, whereby the charges accumulated in each pixel (hereinafter “ A configuration for removing “residual charges”) is disclosed.

JP 2000-2866 (paragraphs 0120 and 0121)

  However, under this configuration, it is necessary to provide a configuration for connecting the electrodes of each pixel to a fixed potential separately from a configuration for driving each pixel (configuration for displaying an image). There may be a problem that the structure of the electro-optical device is complicated. The present invention has been made in view of such circumstances, and an object thereof is to efficiently remove residual charges with a simple configuration.

  In order to solve this problem, according to the present invention, a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines and each of the plurality of scanning lines are sequentially selected to select a selection voltage. A scanning line driving circuit that applies a selection voltage by selecting each scanning line a plurality of times in an off-sequence period after a display stop signal instructing display stop is input, and a scanning line drive A voltage control circuit for reducing a selection voltage applied to each scanning line by the circuit with time in an off-sequence period, and a scanning line selected by the data line and the scanning line driving circuit for each of the plurality of data lines And a data line driving circuit for applying a non-lighting voltage to each data line in the off-sequence period while applying a voltage corresponding to the gray level of the pixel corresponding to the crossing of. The “non-lighting voltage” in the present invention means a voltage having the same polarity as the selection voltage applied to the scanning line during the period among the voltages that can be applied to the data line during the period when the scanning line is selected. Say. In addition, the pixel in the present invention is an element including various electro-optical materials whose optical characteristics such as transmittance and luminance are changed by applying a voltage. However, since the present invention aims to remove the residual charge, it is particularly suitable for an electro-optical device using an electro-optical material in which deterioration of characteristics due to the residual charge is a problem. A typical example of such an electro-optical material is a liquid crystal, but the present invention can also be applied to an electro-optical device using another electro-optical material.

  According to this configuration, each scanning line is sequentially selected in the off-sequence period after the display stop signal is input, and a non-lighting voltage is applied to each data line at the time of selection. That is, since the configuration for displaying an image is also used for removing residual charges, the configuration for removing the residual charge of each pixel is compared with the case where the configuration for displaying images is provided separately from the configuration for displaying images. This simplifies the configuration. Further, according to this configuration, since each scanning line is selected a plurality of times in the off sequence period, each scanning line is selected only once in one vertical scanning period after the display stop signal is input. In comparison, the residual charge is sufficiently removed. On the other hand, the voltage applied to each scanning line during image display is generally larger than the non-lighting voltage applied to the data line. Accordingly, if a selection voltage of the same level as that during image display is applied to each scanning line even during the off-sequence period, it is inevitable that a certain amount of charge still remains in each pixel. On the other hand, in the present invention, since the selection voltage applied to each scanning line in the off-sequence period is lowered with time, residual charges can be efficiently removed as compared with the above configuration.

  Note that the selection voltage may be decreased in the off-sequence period. For example, the selection voltage may be decreased stepwise in each of a plurality of vertical scanning periods constituting the off sequence period, or the selection voltage may be decreased continuously from the start point to the end point of the off sequence period. However, for example, if the selection voltage is changed within one vertical scanning period, the gradation differs depending on the position of each pixel in the display area, which may give the viewer a sense of discomfort. Therefore, in the present invention, it is desirable to reduce the selection voltage applied to each scanning line for each vertical scanning period.

  In a preferred aspect of the present invention, the voltage control circuit generates a selection voltage at a level indicated by the control circuit, the control circuit indicating the level of the selection voltage applied to each scanning line during the off-sequence period, and the scanning line. And a voltage generation circuit for outputting to the drive circuit. According to this configuration, the level of the selection voltage applied to each scanning line in the off sequence period is appropriately adjusted according to an instruction from the control circuit. However, the configuration of the voltage control circuit is not limited to this. For example, a circuit that generates a plurality of types of selection voltages at different levels is used as a voltage control circuit, and one of these types of selection voltages is selected by a scanning line driving circuit and applied to each scanning line. Can be done.

  The electro-optical device according to the invention can be employed as a display device for various electronic apparatuses. According to this electronic apparatus, a high-quality display can be realized by suppressing a reduction in display quality caused by the residual charge.

  The present invention is also specified as a circuit for driving an electro-optical device. In other words, this drive circuit is a circuit that sequentially selects each of the plurality of scanning lines and applies a selection voltage, and each scanning is performed in an off sequence period after a display stop signal instructing display stop is input. A scanning line driving circuit that selects a line a plurality of times and applies a selection voltage; and a voltage control circuit that reduces the selection voltage applied to each scanning line by the scanning line driving circuit over time in an off-sequence period. To do. According to this drive circuit, similar to the electro-optical device according to the present invention, residual charges are efficiently removed with a simple configuration.

  Furthermore, the present invention is also specified as a method for removing residual charges of an electro-optical device. That is, in this driving method, each of the plurality of scanning lines is sequentially selected and applied with the selection voltage, while the plurality of scanning lines are arranged in the off-sequence period after the display stop signal instructing the stop of the display is input. A selection voltage is applied repeatedly, and the selection voltage applied to each scanning line is decreased over time in the off-sequence period, and the data line and the selected scanning line are selected for each of the plurality of data lines. On the other hand, a voltage corresponding to the gray level of the pixel corresponding to the crossing of is applied to each data line during the off-sequence period. According to this method, similar to the electro-optical device according to the present invention, residual charges are efficiently removed with a simple configuration.

<A: Configuration of electro-optical device>
First, an embodiment in which the present invention is applied to an electro-optical device using liquid crystal as an electro-optical material will be described. FIG. 1 is a block diagram illustrating a configuration of the electro-optical device according to the present embodiment. As shown in the figure, the electro-optical device 10 includes a liquid crystal panel 100, a control circuit 400, and a voltage generation circuit 500. Among these, the liquid crystal panel 100 has m scanning lines 312 extending in the X direction (row direction) and n (n is a natural number of 2 or more) extending in the Y direction (column direction). ) Data lines 212. A pixel 116 is formed at each point where the scanning line 312 and the data line 212 intersect. Therefore, these pixels 116 are arranged in a matrix of vertical m rows × horizontal n columns. As shown in FIG. 1, each pixel 116 includes a TFD (Thin Film Diode) element 220 that is a two-terminal switching element, and a liquid crystal capacitor 118 connected in series to the TFD element 220. Note that the liquid crystal panel 100 according to the present embodiment is a normally white mode panel that performs white display when no voltage is applied.

  Next, FIG. 2 is an enlarged view showing the vicinity of the portion where the data line 212 and the scanning line 312 intersect in the liquid crystal panel 100. As shown in the figure, the liquid crystal panel 100 includes an element substrate 200 and a counter substrate 300 facing each other. These substrates are bonded together by a sealing material (not shown) at a constant interval. In a gap between the element substrate 200 and the counter substrate 300, for example, a TN (Twisted Nematic) type liquid crystal 160 is sealed. Note that a polarizing plate or the like that polarizes incident light is attached to the surface of the element substrate 200 or the counter substrate 300 opposite to the liquid crystal 160, but the illustration thereof is omitted in FIG.

  Each of the data lines 212 described above is formed on the plate surface of the element substrate 200 facing the liquid crystal 160. Furthermore, pixel electrodes 234 having a substantially section shape are formed in a matrix on the plate surface of the element substrate 200, and are connected to the data lines 212 through the TFD elements 220 similarly formed on the plate surface of the element substrate 200. Has been. As shown in FIG. 2, each TFD element 220 includes a first conductor 221 branched from the data line 212, an insulator 222 formed by anodizing the surface of the first conductor 221, and a pixel electrode 234. The second conductor 223 connected to the substrate is stacked in this order from the element substrate 200 side. Therefore, each TFD element 220 has a diode switching characteristic in which the current-voltage characteristic is nonlinear in both positive and negative directions. On the other hand, each of the scanning lines 312 described above is formed on the plate surface of the counter substrate 300 facing the liquid crystal 160. Each scanning line 312 is a strip-shaped electrode facing a plurality (n) of pixel electrodes 234 arranged in the X direction on the plate surface of the element substrate 200. The liquid crystal capacitor 118 shown in FIG. 1 includes a liquid crystal 160 sandwiched between the scanning line 312 and the pixel electrode 234 at the intersection of the data line 212 and the scanning line 312. The plate surfaces on the liquid crystal 160 side of the element substrate 200 and the counter substrate 300 are each covered with an alignment film, but the illustration thereof is omitted in FIG.

  As shown in FIG. 1, each scanning line 312 is connected to a scanning line driving circuit 350. The scanning line driving circuit 350 is a circuit that supplies scanning signals Y1, Y2,..., Ym to the scanning lines 312 in the first row, the second row,. More specifically, the scanning line driving circuit 350 sequentially selects any one of the total m scanning lines 312 for each horizontal scanning period (1H), and applies a selection voltage to the selected scanning line 312. A non-selection voltage is applied to each of the other scanning lines 312. Among these, the selection voltage is a voltage that turns on the TFD element 220 regardless of the voltage applied to the data line 212. On the other hand, the non-selection voltage is a voltage that turns off the TFD element 220 regardless of the voltage applied to the data line 212. On the other hand, each data line 212 is connected to the data line driving circuit 250. The data line driving circuit 250 applies data signals X1, X2,... Corresponding to the display contents (gradation) to the pixels 116 for one row corresponding to the scanning line 312 selected by the scanning line driving circuit 350. Xn is output to the data line 212 in the first column, the second column,. 1 illustrates a configuration in which the scanning line driving circuit 350 and the data line driving circuit 250 are arranged in the liquid crystal panel 100, a flexible wiring board connected to the liquid crystal panel 100 or another wiring board (whichever (Not shown) may also be adopted.

  A control circuit 400 shown in FIG. 1 is a circuit that controls each part of the electro-optical device 10. The control circuit 400 receives a video signal Sv from a control unit (hereinafter referred to as “upper control unit”) of an electronic device in which the electro-optical device 10 is mounted. The video signal Sv includes image data Dg indicating the display gradation of each image and various clock signals. The control circuit 400 generates a signal for horizontally scanning the liquid crystal panel 100 based on the clock signal included in the video signal Sv and supplies the signal to the data line driving circuit 250, while performing the vertical scanning of the liquid crystal panel 100. A signal is generated and supplied to the scanning line driving circuit 350. Further, the control circuit 400 outputs the image data Dg included in the video signal Sv to the data line driving circuit 250 in synchronization with vertical scanning and horizontal scanning. This image data Dg is 3-bit data that indicates the gradation of the pixel 116 in eight stages. Specifically, when the 3 bits of the image data Dg is [000], the brightest white gradation is instructed, and the gradation is gradually decreased as the numerical value of the image data Dg increases. When the image data Dg is [111] which is the maximum value, the darkest black gradation is instructed.

  The control circuit 400 also receives a display stop signal Soff for instructing to stop display (that is, stop supply of image data) from the host control unit. The display stop signal Soff is maintained at the L level during a period during which image display using the pixels 116 is to be executed (hereinafter referred to as “normal drive period”), while the timing at which image display should be stopped (see FIG. 7), the transition to the H level occurs. Specifically, the display stop signal Sof f is at the L level at the timing when the pixel 116 is driven and the image is actually displayed to shift to the standby state, or when the electronic device is turned off. To H level.

  In the present embodiment, the charge accumulated in the liquid crystal capacitor 118 and the TFD element 220 is removed in a plurality of vertical scanning periods (hereinafter referred to as “off-sequence period”) after the display stop signal Soff transitions to the H level. Processing is executed. More specifically, in the off-sequence period, each of the total m scanning lines 312 is sequentially selected as in the normal driving period, while the data signal Xj supplied to each of all the data lines 212 is , A signal corresponding to the image data Dg ([000]) indicating white. However, the selection voltage in the off sequence period is set to a level lower than the selection voltage in the normal driving period. That is, the voltage ± Vs0 is applied as a selection voltage to each scanning line 312 during the normal driving period, whereas the voltage ± Vs1 or the voltage ± Vs2 having an absolute value smaller than the voltage ± Vs0 is applied during the off-sequence period. A selection voltage is applied to each scanning line 312. As shown in FIGS. 6 and 7, the voltage ± Vs2 has a smaller absolute value than the voltage ± Vs1. In the following description, the voltages ± Vs0, ± Vs1, and ± Vs2 used as the selection voltages are collectively referred to when there is no particular need to distinguish them (that is, when they are simply expressed as voltages applied to the scanning line 312). And expressed as “voltage ± Vs”. In the present embodiment, it is assumed that the three vertical scanning periods after the normal driving period have elapsed are off-sequence periods.

  The voltage generation circuit 500 is a circuit that generates a voltage ± Vs (± Vs 0, ± Vs1, or ± Vs2) and a voltage ± Vn used for driving the pixel 116 under the control of the control circuit 400. Among these, the voltage ± Vs is a voltage used as a selection voltage in the scanning signal Yi (i is an integer satisfying 1 ≦ i ≦ m) as described above, and is supplied from the voltage generation circuit 500 to the scanning line driving circuit 350. . On the other hand, the voltage ± Vn is a voltage used not only as a non-selection voltage in the scanning line driving circuit 350 but also as a voltage of the data signal Xj (j is an integer satisfying 1 ≦ j ≦ n). 350 and the data line driving circuit 250 are supplied. The voltages + Vs0, + Vs1, + Vs2, and + Vn and the voltages -Vs0, -Vs1, -Vs2, and -Vn are voltages having opposite polarities with respect to a predetermined reference voltage (for example, the lower potential of the power supply) and absolute values. Are equal.

  Next, specific configurations of the control circuit 400 and the voltage generation circuit 500 will be described with reference to FIG. As shown in the figure, the control circuit 400 includes a CPU (Central Processing Unit) 410 and a signal generation circuit 420. Among these, the signal generation circuit 420 is a circuit that generates various signals for driving the pixels 116 based on the video signal Sv and the display stop signal Soff supplied from the host control unit via the CPU 410. Hereinafter, signals generated by the signal generation circuit 420 will be described.

  First, signals supplied to the scanning line driving circuit 350 for vertical scanning are as follows. First, as shown in FIGS. 6 and 7, the start pulse DY is a pulse output at the beginning of each vertical scanning period (1F). The start pulse DY is also output to the data line driving circuit 250 in order to define the read timing of the image data Dg. Second, the shift clock signal YSCK is a clock signal serving as a reference for vertical scanning, and has a period corresponding to one horizontal scanning period as shown in FIG. Third, the polarity instruction signal POL is a signal that indicates the polarity of the selection voltage to be applied to the selected scanning line 312. More specifically, if the polarity instruction signal POL is at the H level, the positive voltage + Vs is designated as the selection voltage, while if the polarity instruction signal POL is at the L level, the negative voltage −Vs is designated as the selection voltage. Instructed. As shown in FIG. 6 and FIG. 7, the polarity instruction signal POL has its logic level inverted every horizontal scanning period preceding and following on the time axis in one vertical scanning period and moving back and forth on the time axis. In the horizontal scanning period in which the same scanning line 312 is selected in each of the vertical scanning periods, the logic levels are reversed. Fourth, the control signal INH is a signal for defining a period during which a selection voltage is to be applied to each scanning line 312 in each horizontal scanning period. As will be described later, in this embodiment, a selection voltage is applied to each scanning line 312 in the latter half of the first half period and the second half period obtained by dividing each horizontal scanning period into two on the time axis. For this reason, the control signal INH becomes H level in the latter half of each horizontal scanning period. Fifth, the selection instruction signal Ssel is a signal for defining whether or not each scanning line 312 can be selected. That is, while the selection instruction signal Ssel is at the H level, each scanning line 312 is selected by the scanning line driving circuit 350, while each scanning by the scanning line driving circuit 350 is performed when the selection instruction signal Ssel transits to the L level. Selection of line 312 is stopped. As described above, in the present embodiment, selection of each scanning line 312 is performed not only in the normal driving period but also in the off-sequence period after the normal driving period. For this reason, the selection instruction signal Ssel maintains the H level in the normal driving period as shown in FIG. 6, and also three vertical scanning periods (off-sequence periods) after the normal driving period as shown in FIG. The H level is maintained for a time length corresponding to), and when the end point of the off-sequence period arrives, the H level transitions to the L level.

  Next, signals supplied to the data line driving circuit 250 for horizontal scanning will be described. First, the latch pulse LP is a pulse that rises at the beginning of each horizontal scanning period (1H), as shown in FIG. Second, the reset signal RES is a pulse that rises at the beginning of the first half period and the beginning of the second half period of each horizontal scanning period, as shown in FIG. Third, the AC drive signal MX is a signal for AC driving of the pixel 116, and has a phase advanced by 90 degrees from the polarity instruction signal POL as shown in FIG. That is, the AC drive signal MX becomes H level in the first half period in the horizontal scanning period in which the positive voltage + Vs is designated as the selection voltage (that is, the horizontal scanning period in which the polarity instruction signal POL becomes H level). On the other hand, in the horizontal scanning period in which the negative voltage −Vs is designated as the selection voltage (that is, the horizontal scanning period in which the polarity instruction signal POL is at the L level), Becomes H level. Fourth, as shown in FIG. 8, the gray level control pulse GCP has a gray level (image data Dg [110] other than white or black) in each of the first half period and the second half period of the horizontal scanning period. ], [101], [100], [011], [010], and a pulse corresponding to a pulse that rises at a timing corresponding to [001]. 8 illustrates the case where the gradation control pulses GCP are arranged at equal intervals on the time axis, the timing at which the gradation control pulses GCP are actually output is the voltage applied to the liquid crystal capacitor 118. -It is selected in consideration of density (transmittance) characteristics (so-called VT characteristics), and is not necessarily equidistant. The above is the outline of the signal generated by the signal generation circuit 420.

  The CPU 410 shown in FIG. 3 supplies the video signal Sv and the display stop signal Soff to the signal generation circuit 420, and instructs the voltage generation circuit 500 of the level of the selection voltage output to the scanning line driving circuit 350. Is responsible. More specifically, the CPU 410 outputs voltage data Bdata indicating the level of the selection voltage to be applied to each scanning line 312 to the voltage generation circuit 500 in the off sequence period. The content of the voltage data Bdata is determined such that the selection voltage applied to each scanning line 312 decreases with time in the off-sequence period. That is, as shown in FIG. 7, the CPU 410 sets the voltage ± Vs1 at the timing when one vertical scanning period (the first vertical scanning period constituting the off-sequence period) has elapsed after the display stop signal Soff has transitioned to the H level. The voltage data Bdata indicating the voltage ± Vs2 is output at the timing when one vertical scanning period (the second vertical scanning period constituting the off-sequence period) has passed since the output time.

  On the other hand, the voltage generation circuit 500 includes an interface (I / F) 510, an EPROM (Erasable Programmable Read Only Memory) 520, and four voltage generation units 530 (530a, 530b, 530c, and 530d), as shown in FIG. Have Each voltage generation unit 530 is a circuit for generating a voltage used for driving the pixel 116, and includes a booster that generates a voltage according to an instruction from the interface 510. Among these four voltage generation units 530, the uppermost voltage generation unit 530a in FIG. 3 generates a voltage + Vs (+ Vs0, + Vs1 or + Vs2) used as a positive selection voltage, and a second-stage voltage generation unit 530b. Generates a voltage + Vn as a positive non-selection voltage, a voltage generation unit 530c at the third stage generates a voltage -Vn as a negative non-selection voltage, and a voltage generation unit 530d at the lowermost stage generates a negative selection voltage. Is generated as a voltage + Vs (-Vs0, -Vs1 or -Vs2).

  The EPROM 520 is a non-volatile memory that stores voltage data Bdata indicating the level of the voltage to be generated by each voltage generation unit 530 in a rewritable manner. In this EPROM 520, in addition to voltage data Bdata indicating initial values of the voltage ± Vs and voltage ± Vn, temperature compensation data for performing voltage compensation according to the environmental temperature in which the electro-optical device 10 is used is written. It is. On the other hand, the interface 510 is a circuit for instructing each voltage generation unit 530 to indicate the voltage level indicated by the voltage data Bdata supplied from the CPU 410 or the voltage data Bdata stored in the EPROM 520. That is, when driving of the pixel 116 is started, the interface 510 corrects the voltage level indicated by the voltage data Bdata stored in the EPROM 520 based on the environmental temperature and temperature compensation data detected by a temperature sensor (not shown). Then, each voltage generation unit 530 is instructed. Thus, in the normal driving period, the voltage ± Vs0 is generated as the selection voltage and output to the scanning line driving circuit 350, and the voltage ± Vn is generated as the non-selection voltage and the voltage of the data signal Xj. 350 and the data line driving circuit 250. On the other hand, when the off sequence period comes and voltage data Bdata is input from CPU 410, interface 510 instructs voltage generation units 530a and 530d to indicate the voltage level indicated by voltage data Bdata. Thereby, in the normal driving period, the voltage ± Vs1 or ± Vs2 lower than the voltage ± Vs0 is generated as the selection voltage and output to the scanning line driving circuit 350. The voltage ± Vn maintains a common level throughout both the normal driving period and the off sequence period. Note that the voltage level instructed to the voltage generation circuit 500 during the off-sequence period may be subjected to temperature compensation as in the normal driving period. As described above, the CPU 410 and the voltage generation circuit 500 illustrated in FIG. 3 function as the voltage control circuit 400 that lowers the selection voltage applied to each scanning line 312 over time in the off-sequence period.

  Next, the configuration of the scanning line driving circuit 350 will be described with reference to FIG. The shift register 352 shown in the figure has an m-bit stage number corresponding to the total number of scanning lines 312. As shown in FIGS. 6 and 7, the shift register 352 performs one vertical scan in a period during which the selection instruction signal Ssel supplied from the control circuit 400 maintains the H level (that is, a normal driving period and an off-sequence period). The start pulse DY supplied at the beginning of the period is sequentially shifted by the shift clock signal YSCK to be output as transfer signals Ys1, Ys2,. When any transfer signal Ysi becomes H level, it indicates that the horizontal scanning period in which the i-th scanning line 312 is to be selected. On the other hand, when the selection instruction signal Ssel supplied from the control circuit 400 transitions to the L level, the shift register 352 stops the output operation of the transfer signal Ysi. For example, when the selection instruction signal Ssel transitions to the L level, the input of the start pulse DY to the shift register 352 is stopped.

  On the other hand, the voltage selection signal forming circuit 354 generates voltage selection signals a, b, c, and d that specify the applied voltage to each scanning line 312 based on the transfer signal Ysi, the polarity instruction signal POL, and the control signal INH. . The voltage selection signals a, b, c, and d are exclusively at the active level (H level). Among these, when the voltage selection signal a becomes H level, the positive selection voltage is designated as the voltage applied to the scanning line 312. Similarly, when the voltage selection signals b, c, and d are at the H level, the positive non-selection voltage, the negative non-selection voltage, and the negative selection voltage are designated as the voltages applied to the scanning line 312, respectively. . In the present embodiment, as described above, the selection voltage is applied in the latter half of each horizontal scanning period (indicated as “1 / 2H” in FIGS. 6 and 7). Further, the non-selection voltage applied during the period from the lapse of the latter half period in which the selection voltage is applied to the lapse of one vertical scanning period (non-selection period) is the voltage after the positive selection voltage is applied. It is + Vn and is −Vn after the negative selection voltage is applied, and is uniquely determined according to the polarity of the immediately preceding selection voltage. The details are as follows.

  First, the voltage selection signal forming circuit 354 operates as follows based on the transfer signal Ys1 output from the shift register 352 in the normal driving period and the off sequence period in which the display stop signal Soff is at the L level. First, it is indicated that the transfer signal Ysi is in the H level and the horizontal scanning period in which the i-th scanning line 312 is to be selected, and the control signal INH is in the H level and the horizontal scanning period is selected. In the latter half period, the voltage selection signal forming circuit 354 causes the voltage level of the scanning signal Yi to become a selection voltage having a polarity corresponding to the signal level of the polarity instruction signal POL in the latter half period. After the elapse of time, the levels of the voltage selection signals a, b, c, and d are determined so that the non-selection voltage has a polarity corresponding to the selection voltage. Specifically, the voltage selection signal forming circuit 354 is a voltage corresponding to the positive selection voltage (+ Vs) if the polarity instruction signal POL is at the H level during the period when the control signal INH is at the H level (second half period). When the selection signal a is set to the H level in the latter half period and the control signal INH transitions to the L level after the latter half period has elapsed, the voltage selection signal b corresponding to the positive non-selection voltage (+ Vn) is set to the H level. . On the other hand, the voltage selection signal formation 354 sets the voltage selection signal d corresponding to the negative selection voltage (−Vs) to the H level if the polarity instruction signal POL is the L level during the period in which the control signal INH is at the H level. When the second half period elapses and the control signal INH transitions to the L level, the voltage selection signal c corresponding to the negative non-selection voltage (−Vn) is set to the H level.

  The selector group 358 has four switches 3581 to 3584 for each scanning line 312. One end of each of these switches 3581 to 3584 is connected to a wiring to which a selection voltage (voltage ± Vs) of each polarity and a non-selection voltage (± Vn) of each polarity are supplied, and the other end is connected to one scanning line 312. They are connected in common. Further, voltage selection signals a, b, c and d are supplied to the gates of the switches 3581 to 3584, respectively. Each of switches 3581 to 3584 becomes conductive between one end and the other end when voltage selection signals a, b, c, and d inputted to the gates become H level. Therefore, either one of the selection voltage and the non-selection voltage is applied to each scanning line 312 via one of the switches 3581 to 3584 that is in a conductive state.

  Next, the waveform of the scanning signal Yi output from the scanning line driving circuit 350 will be described with reference to FIGS. First, in the normal drive period, as shown in FIG. 6, in the second half of the horizontal scanning period in which the polarity instruction signal POL is at the H level, the scanning signal Yi is set to the voltage + Vs0, which is the positive selection voltage, and then the positive polarity The non-selective voltage + Vn is maintained. On the other hand, in the horizontal scanning period in which the scanning line 312 is selected next, the level of the polarity instruction signal POL becomes the L level which is inverted from the previous selection, so that the scanning signal Yi to the scanning line 312 is negative. The selected voltage is -Vs0, which is then maintained at the negative non-selection voltage -Vn. Further, since the logic level of the polarity instruction signal POL is inverted every horizontal scanning period, the polarity of the scanning signal Yi supplied to each scanning line 312 is changed every horizontal scanning period (that is, every row of the scanning line 312). Inverts alternately.

  Further, as shown in FIG. 7, the scanning signal Yi in the off sequence period is inverted in polarity at the same timing as in the normal driving period based on the control signal INH and the polarity instruction signal POL, while the selection voltage is normal. The level is equal to or lower than the selection voltage during the driving period. As shown in the figure, the selection voltage of the scanning signal Yi in the first vertical scanning period in the off-sequence period is set to the voltage ± Vs0 as in the normal driving period. On the other hand, at the beginning of the second vertical scanning period in the off-sequence period, voltage data Bdata specifying the voltage ± Vs1 as the selection voltage is input from the CPU 410 to the voltage generation circuit 500. Accordingly, in each horizontal scanning period of the vertical scanning period, the selection voltage of the scanning signal Yi is set to a voltage ± Vs1 lower than the voltage ± Vs0, and then set to a non-selection voltage ± Vn having the same polarity as the selection voltage. . Further, voltage data Bdata specifying voltage ± Vs2 as a selection voltage is input to voltage generation circuit 500 at the beginning of the third (last) vertical scanning period in the off-sequence period. Therefore, in the horizontal scanning period of the vertical scanning period, the selection voltage of the scanning signal Yi is set to a lower voltage ± Vs2, and then to the non-selection voltage ± Vn having the same polarity as the selection voltage. On the other hand, since the output of the transfer signal Ysi by the shift register 352 stops when the selection sequence signal Ssel transitions to the L level after the off sequence period has elapsed, the voltage selection signal generation operation by the voltage selection signal forming circuit 354 is also stopped. The voltage applied to each scanning line 312 is the voltage Vc.

  Next, the configuration of the data line driving circuit 250 will be described with reference to FIG. The address control circuit 252 shown in the figure is a circuit for generating an address Rad used for reading the image data Dg. The address control circuit 252 resets the row address Rad by a start pulse DY supplied at the beginning of the horizontal scanning period, and The step is advanced by the latch pulse LP supplied every scanning period. The display data RAM 254 is a dual-port RAM having a storage area corresponding to the pixels 116 of m rows × n columns. On the writing side, the image data Dg supplied from the control circuit 400 is written from the control circuit 400. It is written at the address specified by the embedded address Wad. However, in the off sequence period, the image data Dg corresponding to all the pixels 116 is set to [000] indicating white display.

  Next, the decoder 256 resets the voltage selection signals e and f for selecting the voltages of the data signals X1, X2,..., Xn according to the n pieces of image data Dg read from the display data RAM 254. This is a circuit exclusively generating from the signal RES, the AC drive signal MX, and the gradation control pulse GCP. Here, the voltage selection signal e instructs selection of the voltage + Vn, and the voltage selection signal f instructs selection of the voltage −Vn. On the other hand, the selector group 258 has two switches 2581 and 2582 for each column of data lines 212. One end of each of these switches 2581 and 2582 is connected to a wiring to which a voltage + Vn and a voltage −Vn are supplied, and the other end is connected in common to one data line 212. Voltage selection signals e and f are supplied to the gates of the switches 2581 and 2582, respectively. Each of switches 2581 and 2582 is rendered conductive between one end and the other end when voltage selection signals e and f input to the gate are at the H level. Therefore, each of the data lines 212 is applied with either the voltage + Vn or the voltage −Vn through the switch 2581 and 2582 which are in the conductive state.

  Next, the waveform of the data signal Xj supplied to the data line driving circuit 250 will be described with particular attention to the operation of the decoder 256. FIG. 8 is a diagram showing the relationship between the binary display of the image data Dg input to the decoder 256 and the data signal Xj obtained by decoding it. As shown in the figure, the decoder 256 has an intermediate gradation (image data Dg [110], [101]) in which the image data Dg excludes white and black in one horizontal scanning period in which the polarity instruction signal POL is at the H level. , [100], [011], [010] and [001] are gray gradations), first, the AC drive signal MX is generated by the reset signal RES supplied at the beginning of the horizontal scanning period. The level is reset to the opposite level. Second, the gradation control pulse GCP corresponding to the image data Dg is set to the same level as the AC drive signal MX at the falling edge. Third, the horizontal scanning is performed. The reset signal RES supplied at the beginning of the second half of the period is ignored, and fourthly, the fall of the gradation control pulse GCP corresponding to the image data Dg falls. Voltage selection signals e and f that are reset to the same level as the AC drive signal MX are generated. On the other hand, in the horizontal scanning period in which the polarity instruction signal POL is at the H level, the decoder 256 sets the image data Dg to a level obtained by inverting the AC drive signal MX if the image data Dg is [000] indicating white. If Dg is [111] indicating black, the voltage selection signals e and f are generated so as to be at the same level as the AC drive signal MX, respectively. In addition, the decoder 256 has voltage selection signals e and f in which the logic level is inverted in the horizontal scanning period in which the polarity instruction signal POL is at the L level as compared with the horizontal scanning period in which the polarity instruction signal POL is at the H level. Is generated.

  Next, FIG. 9 shows a scanning signal Yi to the scanning line 312 in the i-th row, a scanning signal Yi + 1 to the scanning line 312 one row lower than this, and a data signal to the data line 212 in the j-th column. It is a figure which shows each waveform of Xj. For this data signal Xj, the pixel 116 arranged at the intersection of the scanning line 312 in the i-th row and the (i + 1) -th row and the data line 212 in the j-th column is displayed in white, black, and in between. Each case is shown in gray.

  As shown in FIGS. 8 and 9, the data signal Xj in the second half of each horizontal scanning period has a longer period for taking on the lighting voltage as the gray level of the pixel 116 becomes darker. Here, if the selection voltage is positive (voltage + Vs), the lighting voltage is negative voltage -Vn. Conversely, if the selection voltage is negative (voltage -Vs), the positive voltage is positive. Voltage + Vn. On the other hand, the data signal Xj in the first half period immediately before the second half period has a relationship in which the voltage is reversed from that in the second half period. Therefore, the time length for the data signal Xj to become the voltage + Vn and the time length for the voltage −Vn to be equal in one horizontal scanning period. For this reason, no matter what pattern the gradation of the pixel 116 is continuous, the total length of time that the data signal Xj becomes the voltage + Vn and the total length of time that becomes the voltage −Vn in one vertical scanning period are the same. It becomes. This means that the effective voltage value applied to the pixels 116 in the non-selection period is the same across all the pixels 116. According to this configuration, when displaying a checkered pattern in which white pixels and black pixels are alternately arranged in the row direction and the column direction, a zebra pattern in which white pixels and black pixels are alternately arranged in each row, and the like are displayed. Crosstalk in the column (vertical) direction, which is a problem, can be suppressed. This vertical crosstalk is also disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-147671 (in particular, refer to FIG. 10).

  On the other hand, since the image data Dg is set to [000] indicating white display in the off-sequence period, the voltage applied to the data line 212 in each horizontal scanning period is a voltage (non- Lighting voltage). Therefore, in the off-sequence period, charges (residual charges) accumulated in the liquid crystal capacitor 118 and the TFD element 220 in the normal driving period immediately before that are removed. In addition, in the present embodiment, the selection voltage applied to each scanning line 312 is reduced with the passage of time in the off-sequence period, so that the voltage applied to the liquid crystal capacitor 118 and the TFD element 220 also decreases with time. To go. According to this configuration, residual charges are efficiently removed as compared with a configuration in which the selection voltage is constant during the off sequence period. On the other hand, in the present embodiment, the configuration for driving the pixel 116 is also used for the removal of residual charges. Therefore, the configuration for removing the residual charges is separated from the configuration for driving the pixels 116. The configuration of the electro-optical device 10 is simplified as compared with the case where it is provided.

<B: Modification>
Various modifications can be made to the above embodiments. Specific modifications are as follows.

(1) In the above-described embodiment, the configuration in which the scanning lines 312 are selected one by one in the off-sequence period as in the normal driving period is exemplified. However, in the off-sequence period, the plurality of scanning lines 312 are selected collectively. Configurations that are also possible may be employed. For example, if the configuration shown in FIG. 10 is adopted as the configuration prior to the voltage selection signal forming circuit 354 in the scanning line driving circuit 350, the four scanning lines 312 can be selected at once in the off-sequence period. The shift register 352 shown in the figure is a circuit having the same configuration as that of the above embodiment, and has a total of m stages (here, m = 320 for convenience) of unit circuits (registers) 352a. These unit circuits 352a are divided into blocks B1 to B2 every 80 pieces. That is, the unit circuits 352a from the first stage to the 80th stage are in the block B1, the unit circuits 352a from the 81st stage to the 160th stage are in the block B2, and the unit circuits from the 161st stage to the 240th stage are shown. 352a is divided into blocks B3, and unit circuits 352a from the 241nd stage to the 320th stage are divided into blocks B4. A switch circuit 356 is provided in front of the shift register 352. The switch circuit 356 includes a switch 356a corresponding to the blocks B2 to B4 except the uppermost block. The start pulse DY is supplied from the control circuit 400 to the input terminal of each switch 356a, while the output terminal is connected to the first stage unit circuit 352a (the 81st stage, the 161st stage) belonging to the block corresponding to the switch 356a. Unit circuit 352a) of the first and 241st stages. Each switch 356a is turned on only when the display stop signal Soff is at the H level, and outputs the start pulse DY input from the control circuit 400 to the first stage unit circuit 352a of each block. Note that the switch 356a is not provided in the previous stage of the block B1, and the start pulse DY is directly input from the control circuit 400 to the unit circuit 352a in the first stage.

  Under this configuration, in the normal driving period, the display stop signal Soff maintains the L level, so that each switch 356a is turned off. In this case, the shift register 352 sequentially shifts the start pulse DY in accordance with the shift clock signal YSCK and outputs it as transfer signals Ys1, Ys2,. On the other hand, in the off sequence period, the display stop signal Soff becomes H level and each switch 356a is turned on. Therefore, the start pulse DY is collectively input to the first stage unit circuit 352a belonging to each of the blocks B1 to B4, and the shift according to the shift clock signal YSCK is executed for each block. Therefore, the transfer signals Ysi output from one unit circuit 352a belonging to the blocks B1 to B4 are simultaneously set to the H level. More specifically, in the first horizontal scanning period of one vertical scanning period, the scanning lines 312 of the first row, the 81st row, the 161st row, and the 241st row are selected, and the second In the second horizontal scanning period, the scanning lines 312 of the second row, the 82nd row, the 162nd row, and the 242nd row are selected. As a result, the voltages of the scanning signals supplied to the four scanning lines 312 out of the 320 scanning lines 312 simultaneously become the selection voltage. By adopting a configuration in which a plurality of scanning lines 312 are simultaneously selected in the off-sequence period as described above, the time length of the off-sequence period can be shortened compared to a configuration in which each scanning line 312 is selected one by one. . For example, according to the configuration shown in FIG. 10, the time length of the off-sequence period is shortened to ¼ of the time length in the above embodiment. Note that the number of scanning lines 312 that are simultaneously selected in the off-sequence period is arbitrary. For example, a configuration in which all the scanning lines 312 are selected at once can be adopted.

(2) In the above embodiment, the period corresponding to the three vertical scanning periods is the off-sequence period, but the time length of the off-sequence period is arbitrary. In short, a configuration in which each scanning line 312 is selected a plurality of times in the off-sequence period is sufficient. In the above embodiment, the configuration in which the level of the selection voltage is switched every vertical scanning period belonging to the off-sequence period is exemplified, but the timing for changing the selection voltage is not limited to this. For example, a configuration in which the level of the selection voltage is switched every horizontal scanning period belonging to the off sequence period may be employed. Furthermore, a configuration for changing the selection voltage stepwise is not always necessary. For example, a configuration in which the level of the selection voltage is continuously decreased with the passage of time in the off sequence period may be employed.

(3) In the above embodiment, the configuration in which the selection voltage itself generated by the voltage generation circuit 500 is changed in the off-sequence period is illustrated, but the configuration for reducing the selection voltage applied to the scanning line 312 is limited to this. I can't. For example, the voltage generation circuit 500 generates a plurality of types of selection voltages having different levels (voltages ± Vs0, ± Vs1 and ± Vs2 in the above embodiment), while the scanning line drive circuit 350 is at the level when the off-sequence period comes. A configuration in which the voltage applied to the scanning line 312 is sequentially switched from a high selection voltage toward a low level selection voltage may also be employed. As described above, in the present invention, it suffices if the selection voltage applied to each scanning line 312 is reduced with the passage of time in the off-sequence period, and the specific configuration for that is not questioned.

(4) In the above embodiment, the scanning line driving circuit 350, the data line driving circuit 250, the control circuit 400, and the voltage generation circuit 500 have been described as separate circuits. However, part or all of these circuits are integrated as a single unit. It may be configured as a circuit. In the above-described embodiment, the configuration in which the driving method (so-called pulse width modulation method) for controlling the gradation of the pixel 116 by adjusting the time length during which the data signal Xj becomes the lighting voltage is exemplified. Other driving methods may be employed. For example, a driving method for controlling the gradation of the pixel 116 by setting the data signal Xj to a voltage level corresponding to the gradation of the pixel 116 may be employed. In the above embodiment, the active matrix type liquid crystal panel 100 using the TFD element 220 as an active element is illustrated. However, a passive matrix type in which the liquid crystal 160 is sandwiched by the intersection of strip-like electrodes without using the active element. The present invention can also be applied to the electro-optical device 10. Further, in the above-described embodiment, the configuration in which the TFD element 220 is connected to the data line 212 and the liquid crystal capacitor 118 is connected to the scanning line 312 is illustrated. On the contrary, the TFD element 220 is connected to the scanning line 312. In addition, a configuration in which the liquid crystal capacitor 118 is connected to the data line 212 may be employed.

(5) The present invention can also be applied to an electro-optical device using an electro-optical material other than liquid crystal. In other words, the present invention can be applied to any device having a plurality of pixels using an electro-optic material that converts electrical energy such as current and voltage into optical effects such as changes in luminance and transmittance. For example, a display device using an OLED (Organic Light Emitting Diode) element such as an organic EL (Electro Luminescent) or a light emitting polymer as an electro-optical material, or a micro that includes a colored liquid and white particles dispersed in the liquid. Electrophoretic display device using capsule as electro-optic material, twist ball display using twist ball painted in different colors for each region with different polarity as electro-optic material, toner using black toner as electro-optic material The present invention can be applied to various electro-optical devices such as a display or a plasma display panel using a high-pressure gas such as helium or neon as an electro-optical material.

<C: Electronic equipment>
Next, an electronic apparatus including the electro-optical device 10 according to the present invention as a display unit will be described. FIG. 11 is a perspective view showing a configuration of a mobile phone having the electro-optical device 10 according to the embodiment. As shown in this figure, a mobile phone 1100 includes a plurality of operation buttons 1102 operated by a user, a earpiece 1104 that outputs voice received from another terminal device, and voice transmitted to the other terminal device. In addition to the mouthpiece 1106 for inputting, the electro-optical device 10 for displaying various images is provided.

  In addition to the mobile phone shown in FIG. 11, examples of electronic equipment that can use the electro-optical device 10 according to the present invention include a notebook personal computer, a liquid crystal television, a viewfinder type (or a monitor direct view type). Video recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like.

1 is a block diagram illustrating an overall configuration of an electro-optical device according to an embodiment of the invention. It is a perspective view which expands and shows the structure of a liquid crystal panel among electro-optical devices. It is a block diagram which shows the structure of a control circuit and a voltage generation circuit among electro-optical apparatuses. It is a block diagram showing a configuration of a scanning line driving circuit in the electro-optical device. It is a block diagram which shows the structure of a data line drive circuit among electro-optical apparatuses. 6 is a timing chart illustrating an operation of the scanning line driving circuit in a normal driving period. 6 is a timing chart illustrating an operation of the scanning line driving circuit in an off sequence period. 3 is a timing chart showing the operation of the data line driving circuit. It is a timing chart which shows the waveform of the voltage applied to each pixel. It is a block diagram which shows the structure of a part of scanning line drive circuit which concerns on a modification. It is a perspective view which shows the structure of the mobile telephone which is an example of the electronic device which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical device, 100 ... Liquid crystal panel, 200 ... Element substrate, 300 ... Opposite substrate, 160 ... Liquid crystal, 116 ... Pixel, 118 ... Liquid crystal capacity, 220 ... TFD element, 212 ... Data line, 234... Pixel electrode, 250... Data line drive circuit, 254... Display data RAM, 256... Decoder, 258 and 358. 352, shift register, 352a, unit circuit, 354, voltage selection signal formation circuit, 400, control circuit, 410, CPU, 420, signal generation circuit, 500, voltage generation circuit, 510. Interface, 520 ... EPROM, 530 ... Voltage generation unit, Yi ... Scan signal, Xj ... Data signal, Dg ... Image data, Soff ... Display stop signal, sel ...... selection instruction signal, Sv ...... video signal.

Claims (6)

A pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines;
A circuit that sequentially selects each of the plurality of scanning lines and applies a selection voltage, and each of the scanning lines is applied a plurality of times in an off-sequence period after a display stop signal instructing display stop is input. A scanning line driving circuit for selecting and applying a selection voltage;
A voltage control circuit for reducing a selection voltage applied to each scanning line by the scanning line driving circuit with the passage of time in the off-sequence period;
A voltage corresponding to the gray level of the pixel corresponding to the intersection of the data line and the scanning line selected by the scanning line driving circuit is applied to each of the plurality of data lines, while in the off-sequence period. An electro-optical device comprising: a data line driving circuit that applies a non-lighting voltage to each of the data lines. The scanning line driving circuit selects each scanning line a plurality of times with a plurality of vertical scanning periods after the display stop signal is input as the off-sequence period,
The electro-optical device according to claim 1, wherein the voltage control circuit decreases a selection voltage applied to each of the scanning lines for each vertical scanning period of the off-sequence period. The voltage control circuit includes:
A control circuit for instructing a level of a selection voltage applied to each scanning line in the off-sequence period;
The electro-optical device according to claim 1, further comprising: a voltage generation circuit that generates a selection voltage at a level instructed by the control circuit and outputs the selection voltage to the scanning line driving circuit.   An electronic apparatus comprising the electro-optical device according to claim 1 as a display device. In a drive circuit of an electro-optical device having pixels provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines,
A circuit that sequentially selects each of the plurality of scanning lines and applies a selection voltage, and each of the scanning lines is applied a plurality of times in an off-sequence period after a display stop signal instructing display stop is input. A scanning line driving circuit for selecting and applying a selection voltage;
A drive circuit for an electro-optical device, comprising: a voltage control circuit that reduces a selection voltage applied to each scan line by the scan line drive circuit as time passes in the off-sequence period. In a method for driving an electro-optical device having a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines,
Each of the plurality of scanning lines is sequentially selected and a selection voltage is applied, and each of the scanning lines is selected a plurality of times in an off-sequence period after a display stop signal instructing display stop is input. Apply selection voltage,
Decreasing the selection voltage applied to each scanning line over time in the off-sequence period,
A voltage corresponding to the gray level of the pixel corresponding to the intersection of the data line and the selected scan line is applied to each of the plurality of data lines, while the data line is applied to each data line during the off-sequence period. A non-lighting voltage is applied to the electro-optical device.

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