JP2005197354A - Semiconductor module and its manufacturing method - Google Patents

Semiconductor module and its manufacturing method Download PDF

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Publication number
JP2005197354A
JP2005197354A JP2004000390A JP2004000390A JP2005197354A JP 2005197354 A JP2005197354 A JP 2005197354A JP 2004000390 A JP2004000390 A JP 2004000390A JP 2004000390 A JP2004000390 A JP 2004000390A JP 2005197354 A JP2005197354 A JP 2005197354A
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cavity
semiconductor module
electronic component
multilayer substrate
mounting surface
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Japanese (ja)
Inventor
Kenji Koyama
賢治 小山
Reiichi Arai
令一 荒井
Jun Sakazume
順 坂爪
Toshiyuki Handa
利幸 半田
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Renesas Technology Corp
Hitachi Information Technology Co Ltd
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Renesas Technology Corp
Hitachi Hybrid Network Co Ltd
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Priority to JP2004000390A priority Critical patent/JP2005197354A/en
Publication of JP2005197354A publication Critical patent/JP2005197354A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the positional deviation of an electronic component disposed on the end of a multilayer board. <P>SOLUTION: In the semiconductor module of electronic components mounted on a component mounting surface of a multilayer board with a seal covering the component mounting surface, the multilayer board has a cavity formed in its component mounting surface end for housing the electronic components. The side face of the cavity is narrower than the width of the electronic component housed therein and opened on the side face of the multilayer board. This constitution prevents the positional deviation of the electronic component in the cavity, thereby allowing the semiconductor module to be miniaturized. The side face of the cavity is opened to ensure a strength of the multilayer board. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体モジュールに関し、特に、高周波用の半導体モジュールに適用して有効な技術に関するものである。   The present invention relates to a semiconductor module, and more particularly to a technique effective when applied to a high-frequency semiconductor module.

移動体通信の端末機器いわゆる携帯電話では、カメラ機能の搭載に見られる多機能化が進められており、今後更に多くの機能を携帯電話に内蔵することが予想される。このため、携帯電話に用いられる構成要素については、更なる小型化が求められている。   In mobile communication terminal devices, so-called mobile phones, the multi-functionality found in camera functions has been promoted, and it is expected that more functions will be built into mobile phones in the future. For this reason, further miniaturization is required for the components used in the mobile phone.

例えば、携帯電話の構成要素の一つである高周波増幅器に用いられる半導体モジュールでは、シート状の絶縁層と銅或いは銀等を用いた金属薄膜の導体層とを交互に積層して構成された多層基板の表側となる部品搭載面には、受動素子であるインダクタ、コンデンサ、抵抗等の電子部品を実装し、多層基板の裏側となる基板実装面には、配線基板等の基板実装のための外部端子を形成し、金属キャップ或いは樹脂封止体によって部品搭載面を覆ってある。   For example, in a semiconductor module used for a high-frequency amplifier, which is one of the components of a mobile phone, a multilayer formed by alternately laminating sheet-like insulating layers and conductive layers of metal thin films using copper, silver, or the like Electronic components such as inductors, capacitors, and resistors, which are passive elements, are mounted on the component mounting surface, which is the front side of the board. A terminal is formed, and the component mounting surface is covered with a metal cap or a resin sealing body.

多層基板の最上層の配線端部には、インダクタ、コンデンサ、抵抗等の電子部品をハンダ等により実装するためのパッドを設け、多層基板の最下層の配線端部には基板実装のための外部端子を形成し、最上層の配線と最下層の配線とは、中間層の配線及び層間を連絡するビア配線によって電気的に接続されている。   Pads for mounting electronic components such as inductors, capacitors, resistors, etc. with solder etc. are provided at the wiring end of the uppermost layer of the multilayer board, and external wiring for board mounting is provided at the lowermost wiring end of the multilayer board. A terminal is formed, and the uppermost layer wiring and the lowermost layer wiring are electrically connected by an intermediate layer wiring and a via wiring connecting the layers.

多層基板には、能動素子である電子部品として、増幅用のＦＥＴ等が内部に形成された半導体装置が実装されているが、半導体装置の接続端子であるボンディングパッドと多層基板のパッドとを電気的に接続するボンディングワイヤのループの高さを吸収するために、多層基板に設けた凹部であるキャビティに半導体装置を収容し、半導体装置は中間層の配線にハンダ等により取り付けられている。   A semiconductor device having an amplifying FET or the like formed therein is mounted on the multilayer substrate as an electronic component that is an active element. The bonding pads that are connection terminals of the semiconductor device and the pads of the multilayer substrate are electrically connected. In order to absorb the height of the bonding wire loop to be connected, the semiconductor device is accommodated in a cavity which is a recess provided in the multilayer substrate, and the semiconductor device is attached to the wiring of the intermediate layer by solder or the like.

こうした半導体モジュールを小型化するために、下記特許文献１には、インダクタ、コンデンサ、分布定数線路、共振器、フィルタおよびバランなどを含むＲＦ用受動部品３６を多層基板の中間層に形成する技術が記載されている。   In order to reduce the size of such a semiconductor module, the following Patent Document 1 discloses a technique for forming an RF passive component 36 including an inductor, a capacitor, a distributed constant line, a resonator, a filter, a balun, and the like in an intermediate layer of a multilayer substrate. Has been described.

特開２００２−９２２５号公報JP 2002-9225 A

前記多層基板の周縁部には、従来は２００μｍ〜２５０μｍ程度の幅に部品搭載禁止領域が設けられていた。前記電子装置の小型化に対応させて、高周波用半導体モジュールを小型化するために、この部品搭載禁止領域の幅を１００μｍ〜１５０μｍ程度に縮小することが考えられる。本発明者等は、部品搭載禁止領域を縮小した半導体モジュールの試作を行なってみたが、部品搭載禁止領域を縮小したことにより、多層基板の部品搭載禁止領域直近の端部に配置された電子部品が、取り付け時の位置ずれ等により部品搭載禁止領域を越えて取り付けられ、電子部品の一部分が部品搭載面を覆う樹脂封止体から露出してしまう事態が発生した。   Conventionally, a component mounting prohibition region has been provided in the peripheral portion of the multilayer substrate with a width of about 200 μm to 250 μm. In order to reduce the size of the high-frequency semiconductor module in accordance with the downsizing of the electronic device, it is conceivable to reduce the width of the component mounting prohibited area to about 100 μm to 150 μm. The inventors have made a prototype of a semiconductor module in which the component mounting prohibited area is reduced, but by reducing the component mounting prohibited area, the electronic component disposed at the end of the multilayer board in the immediate vicinity of the component mounting prohibited area However, due to a positional deviation at the time of attachment, the electronic component is mounted beyond the component mounting prohibited area, and a part of the electronic component is exposed from the resin sealing body that covers the component mounting surface.

本発明の課題は、これらの問題点を解決し、多層基板の端部に配置された電子部品の位置ずれを防止することが可能な技術を提供することにある。
本発明の前記ならびにその他の課題と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。 An object of the present invention is to provide a technique capable of solving these problems and preventing the displacement of electronic components arranged at the end of a multilayer substrate.
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。
多層基板の部品搭載面に電子部品を実装し、封止体によって前記部品搭載面を覆った半導体モジュールにおいて、前記多層基板の部品搭載面端部に、電子部品を収容するキャビティを形成し、このキャビティの側面が、収容する電子部品の幅よりも狭い幅で、前記多層基板の側面に開放されている。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
In a semiconductor module in which an electronic component is mounted on a component mounting surface of a multilayer board and the component mounting surface is covered with a sealing body, a cavity for housing the electronic component is formed at an end of the component mounting surface of the multilayer board. The side surface of the cavity has a width narrower than the width of the electronic component to be accommodated, and is open to the side surface of the multilayer substrate.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
（１）本発明によれば、キャビティによって電子部品の位置ずれを防止することができるという効果がある。
（２）本発明によれば、上記効果（１）により、部品搭載禁止領域を縮小して半導体モジュールを小型化することができるという効果がある。
（３）本発明によれば、上記効果（１）により、半導体モジュールを低背化することができるという効果がある。
（４）本発明によれば、キャビティの側面を開放することにより、多層基板の強度を確保することができるという効果がある。
（５）本発明によれば、より下層の導体層に電子部品を接続して、電気的な安定性を向上させることができるという効果がある。
（６）本発明によれば、放熱経路となる電子部品の実装面から基板実装面までの距離が短くなるので、放熱性を向上させることができるという効果がある。 The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, there is an effect that displacement of the electronic component can be prevented by the cavity.
(2) According to the present invention, the effect (1) has an effect that the component mounting prohibited area can be reduced to reduce the size of the semiconductor module.
(3) According to the present invention, the effect (1) has an effect that the semiconductor module can be reduced in height.
(4) According to the present invention, there is an effect that the strength of the multilayer substrate can be secured by opening the side surface of the cavity.
(5) According to the present invention, there is an effect that an electrical component can be connected to a lower conductor layer to improve electrical stability.
(6) According to the present invention, since the distance from the mounting surface of the electronic component serving as a heat dissipation path to the substrate mounting surface is shortened, there is an effect that heat dissipation can be improved.

（実施の形態１）
以下、本発明の実施の形態を説明する。
なお、実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。 (Embodiment 1)
Embodiments of the present invention will be described below.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

図１は、本発明の一実施の形態である半導体モジュールを示す平面図であり、図２は、その正面図であり、図３は、図１中のａ‐ａ線に沿った縦断面図である。   FIG. 1 is a plan view showing a semiconductor module according to an embodiment of the present invention, FIG. 2 is a front view thereof, and FIG. 3 is a longitudinal sectional view taken along line aa in FIG. It is.

本実施の形態の高周波用半導体モジュールで用いる多層基板１は、銅或いは銀等を用いた０．０１ｍｍ程度の金属薄膜の導体層２とセラミックス等を用いた厚さが０．１５ｍｍ程度のシート状の絶縁層３とを交互に積層して構成されている。この多層基板１では、６層の導体層２と５層の絶縁層３とを交互に積層したものを、低温焼成によって焼結させてある。   The multilayer substrate 1 used in the high-frequency semiconductor module of the present embodiment is a sheet-like shape having a thickness of about 0.15 mm using a conductive layer 2 of a metal thin film of about 0.01 mm using copper or silver and ceramics. The insulating layers 3 are alternately stacked. In this multilayer substrate 1, a structure in which six conductor layers 2 and five insulating layers 3 are alternately laminated is sintered by low-temperature firing.

本実施の形態では、最上層の導体層２ａを１層目とし、中間層の導体層２ｂ，２ｃ，２ｄ，２ｅを上から順に２層目乃至５層目とし、最下層の導体層２ｆを６層目として説明する。絶縁層３についても、同様に上から順に１層目の絶縁層３ａ，２層目の絶縁層３ｂ，３層目の絶縁層３ｃ，４層目の絶縁層３ｄ，５層目の絶縁層３ｅと数えて説明する。多層基板１の最上層の導体層２ａと最下層の導体層２ｆとは、中間層の導体層２ｂ，２ｃ，２ｄ，２ｅ及び層間を連絡するビア配線４によって電気的に接続されている。   In the present embodiment, the uppermost conductor layer 2a is the first layer, the intermediate conductor layers 2b, 2c, 2d, and 2e are the second to fifth layers in order from the top, and the lowermost conductor layer 2f is The description will be made on the sixth layer. Similarly for the insulating layer 3, the first insulating layer 3a, the second insulating layer 3b, the third insulating layer 3c, the fourth insulating layer 3d, and the fifth insulating layer 3e are sequentially arranged from the top. Count and explain. The uppermost conductor layer 2a and the lowermost conductor layer 2f of the multilayer substrate 1 are electrically connected by the intermediate conductor layers 2b, 2c, 2d, and 2e and via wiring 4 that connects the layers.

多層基板１の表側となる部品搭載面に形成された最上層の導体層２ａの端部には、実装する電子部品を接続するためのパッド５を設け、受動素子であるコンデンサ６、抵抗７、インダクタ８等の電子部品をハンダ９等により接続し、シリコーンレジンを用いた封止体１０によって部品搭載面を覆い、多層基板１の裏側となる基板実装面に形成された最下層の導体層２ｆの端部には、配線基板等の基板実装のための外部端子１１を形成してある。なお、図１及び図２では、説明のために封止体１０を透過させて示した。   A pad 5 for connecting an electronic component to be mounted is provided at the end of the uppermost conductor layer 2a formed on the component mounting surface on the front side of the multilayer substrate 1, and a capacitor 6, a resistor 7, An electronic component such as an inductor 8 is connected by solder 9 or the like, the component mounting surface is covered with a sealing body 10 using a silicone resin, and the lowermost conductor layer 2f formed on the substrate mounting surface on the back side of the multilayer substrate 1 An external terminal 11 for mounting on a substrate such as a wiring board is formed at the end portion. In FIGS. 1 and 2, the sealing body 10 is shown through for the sake of explanation.

多層基板には、能動素子の電子部品として高周波増幅用のＦＥＴ等が内部に形成された半導体装置１２が実装されているが、半導体装置１２の接続端子であるボンディングパッドと多層基板のパッド５とを電気的に接続するボンディングワイヤ１３のループの高さを吸収するために、多層基板１には、１層目及び２層目の絶縁層３ａ，３ｂを部分的に除去して設けた凹部であるキャビティ１４を設け、このキャビティ１４に半導体装置１２を収容し、半導体装置１２は３層目の導体層２ｃにハンダ９等により取り付けられている。   On the multilayer substrate, a semiconductor device 12 having a high frequency amplification FET or the like formed therein as an electronic component of an active element is mounted. A bonding pad which is a connection terminal of the semiconductor device 12, a pad 5 of the multilayer substrate, and the like. In order to absorb the height of the loop of the bonding wire 13 that electrically connects the first and second insulating layers 3a and 3b in the multilayer substrate 1, a recess is provided. A cavity 14 is provided, and the semiconductor device 12 is accommodated in the cavity 14. The semiconductor device 12 is attached to the third conductor layer 2 c by solder 9 or the like.

半導体装置１２の取り付けられた導体層２ｃは、接地配線となっており、半導体装置１２の発生した熱は、導体層２ｃからサーマルビアと呼ばれる複数のビア配線４と直下に位置する中間の導体層２ｄ，２ｅによって伝達され、最下層の導体層２ｆを利用した放熱板まで運ばれている。   The conductor layer 2c to which the semiconductor device 12 is attached is a ground wiring, and the heat generated by the semiconductor device 12 is an intermediate conductor layer located immediately below the plurality of via wirings 4 called thermal vias from the conductor layer 2c. 2d, 2e is transmitted to the heat sink using the lowermost conductor layer 2f.

本実施の形態の半導体モジュールでは、多層基板１の部品搭載面端部に、多層基板１を構成する１層目の絶縁層３ａを部分的に除去した凹部であるキャビティ１５を設け、このキャビティ１５に電子部品を収容し、キャビティが収容する電子部品は２層目の導体層２ｂの端部となるパッド５に接続されている。ここでは、キャビティ１５を設けて収容するのは、多層基板１の部品搭載禁止領域直近に配置された電子部品に限定した。   In the semiconductor module of the present embodiment, a cavity 15 which is a recess obtained by partially removing the first insulating layer 3a constituting the multilayer substrate 1 is provided at the end of the component mounting surface of the multilayer substrate 1. The electronic component accommodated in the cavity is connected to the pad 5 which is the end of the second conductor layer 2b. Here, the cavity 15 is provided and accommodated only for electronic components arranged in the immediate vicinity of the component mounting prohibited area of the multilayer substrate 1.

このキャビティ１５の側面は、収容する電子部品の幅よりも狭い幅で、多層基板１の側面に開放されている。このため、キャビティ１５によって電子部品の移動が規制され、電子部品が位置ずれにより多層基板１の部品搭載禁止領域を越えて接続され、封止体１０から部分的に露出するのを防止することができる。   The side surface of the cavity 15 is narrower than the width of the electronic component to be accommodated, and is open to the side surface of the multilayer substrate 1. For this reason, the movement of the electronic component is regulated by the cavity 15, and the electronic component is prevented from being partially exposed from the sealing body 10 by being connected beyond the component mounting prohibited area of the multilayer substrate 1 due to the displacement. it can.

図４に示すのは、従来の半導体モジュールを示す縦断面図であり、多層基板１の部品搭載面はキャビティ１５が設けられていない平坦面となっており、リフロー時等に電子部品が位置ずれを起こした場合には、電子部品の移動を規制することができなかった。このため、部品搭載禁止領域の幅を縮小することが困難であった。   FIG. 4 is a longitudinal sectional view showing a conventional semiconductor module. The component mounting surface of the multilayer substrate 1 is a flat surface not provided with the cavity 15, and the electronic component is misaligned during reflow or the like. When this occurs, the movement of the electronic component cannot be regulated. For this reason, it has been difficult to reduce the width of the component mounting prohibited area.

また、現在では半導体装置は様々な電子装置に用いられており、電子装置の小型化・携帯化に伴い、その使用環境も多様化しており、携帯電話端末機等では、使用中に誤って落下させた場合でも製品に異常が生じるのを防止するために、製品を所定の高さから落下させ、異常の発生の有無を調べる落下試験が行なわれている。   In addition, semiconductor devices are currently used in various electronic devices. As electronic devices become smaller and more portable, their usage environments have diversified. In mobile phone terminals, etc., they are accidentally dropped during use. In order to prevent the product from becoming abnormal even if it is made to drop, a drop test is performed in which the product is dropped from a predetermined height to check whether or not an abnormality has occurred.

本実施の形態の半導体モジュールでは、キャビティ１５の側面を開放してあるため、落下試験等の衝撃力が加えられた場合にも、多層基板１の強度を確保することができる。即ち、側面を開放しない場合には、落下試験等の際に衝撃の加わる多層基板１の端部に薄く絶縁層３ａが壁状に残ることとなり、この部分がクラック等の損傷を発生させる要因となってしまう。本実施の形態の半導体モジュールでは、キャビティ１５の側面を開放しているので、多層基板１の端部に薄く絶縁層３ａが壁状に残ることがない。   In the semiconductor module of the present embodiment, since the side surface of the cavity 15 is opened, the strength of the multilayer substrate 1 can be ensured even when an impact force such as a drop test is applied. That is, when the side surface is not opened, the thin insulating layer 3a remains in the shape of a wall at the end of the multilayer substrate 1 to which an impact is applied during a drop test or the like, and this part causes damage such as cracks. turn into. In the semiconductor module of the present embodiment, since the side surface of the cavity 15 is open, the insulating layer 3a does not remain thin at the end of the multilayer substrate 1 in a wall shape.

また、本実施の形態の半導体モジュールでは、部品搭載面の導電層２ａに変えてより下層の導体層２ｂに電子部品を接続することから、バイパスコンデンサ等は、直接或いはより短い経路で接地配線に接続することが可能になり、電気的な安定性を向上させることができる。   In the semiconductor module of the present embodiment, since the electronic component is connected to the lower conductor layer 2b instead of the conductive layer 2a on the component mounting surface, the bypass capacitor or the like can be connected to the ground wiring directly or through a shorter path. It becomes possible to connect, and electrical stability can be improved.

加えて、本実施の形態の半導体モジュールでは、素子が発生した熱を多層基板１から実装基板に伝熱させて発熱に対処しているが、放熱経路となる電子部品の実装面から基板実装面までの距離が短くなるので、放熱性を向上させることができる。   In addition, in the semiconductor module according to the present embodiment, heat generated by the element is transferred from the multilayer substrate 1 to the mounting substrate to cope with heat generation. However, the electronic component mounting surface serving as a heat dissipation path is changed from the mounting surface to the substrate mounting surface. Therefore, the heat dissipation can be improved.

また、多層基板１の部品搭載面の内方に配置されている電子部品については、位置ずれが生じても、封止体１０から露出することはないが、通常のキャビティを形成して内方に配置されている電子部品を収容することによって、半導体モジュールの部品搭載面からの電子部品突出量が減少するため、半導体モジュールを厚さ方向に小型化する低背化が可能になる。   In addition, the electronic component arranged on the inner side of the component mounting surface of the multilayer substrate 1 is not exposed from the sealing body 10 even if the position shift occurs, but the inner side is formed by forming a normal cavity. By accommodating the electronic components arranged in the housing, the amount of protrusion of the electronic components from the component mounting surface of the semiconductor module is reduced, so that it is possible to reduce the height of the semiconductor module in the thickness direction.

なお、電子部品について、例えばコンデンサ６は、１００５と呼称される１ｍｍ×０．５ｍｍ，ｔ＝０．５ｍｍのサイズのものが用いられており、インダクタも同等のサイズになっている。これに対して抵抗７は、０６０３と呼称される０．６ｍｍ×０．３ｍｍ，ｔ＝０．３ｍｍのサイズの比較的小さなものが用いられている。部品搭載面の内方に配置されている電子部品について、前記キャビティに収容するのは、比較的大きなサイズの電子部品に限定してもよい。   As the electronic component, for example, the capacitor 6 having a size of 1 mm × 0.5 mm and t = 0.5 mm called 1005 is used, and the inductor has the same size. On the other hand, the resistor 7 is a relatively small resistor having a size of 0.6 mm × 0.3 mm and t = 0.3 mm called 0603. The electronic components arranged on the inner side of the component mounting surface may be accommodated in the cavity in an electronic component having a relatively large size.

図５に示すのは、本実施の形態の半導体モジュールの変形例であり、この例では、多層基板１を構成する１層目及び２層目の絶縁層３ａ，３ｂを部分的に除去してキャビティ１５を形成し、収容する電子部品を３層目の導体層に接続している。この構成によって、多層基板１の部品搭載面からの電子部品突出量が更に減少するため、より一層の低背化が可能になる。   FIG. 5 shows a modification of the semiconductor module according to the present embodiment. In this example, the first and second insulating layers 3a and 3b constituting the multilayer substrate 1 are partially removed. A cavity 15 is formed, and the electronic component to be accommodated is connected to the third conductor layer. With this configuration, the amount of protrusion of the electronic component from the component mounting surface of the multilayer substrate 1 is further reduced, so that the height can be further reduced.

この場合には、コンデンサ６或いはインダクタ８のような比較的大きなサイズの電子部品を１層目及び２層目の絶縁層３ａ，３ｂを部分的に除去して形成したキャビティ１５に収容し、抵抗７のような比較的小さなサイズの電子部品については、図５に示すように１層目の絶縁層３ａを部分的に除去して形成したキャビティ１５に収容してもよい。もちろん、１層目及び２層目の絶縁層３ａ，３ｂを部分的に除去して形成したキャビティ１５に収容する、或いはキャビティに収容せずに部品搭載面に接続することも可能である。   In this case, an electronic component having a relatively large size such as the capacitor 6 or the inductor 8 is accommodated in a cavity 15 formed by partially removing the first and second insulating layers 3a and 3b, 7 may be accommodated in a cavity 15 formed by partially removing the first insulating layer 3a as shown in FIG. Of course, the insulating layers 3a and 3b of the first layer and the second layer may be partially removed and accommodated in the cavity 15 or may be connected to the component mounting surface without being accommodated in the cavity.

この半導体モジュールの製造工程では、複数の多層基板１が縦横に連続して形成してあり、コンデンサ６、抵抗７或いはインダクタ８といった電子部品をハンダ９によってパッド５に接続する電子部品の実装、或いは半導体装置１２の実装を夫々の多層基板１について行なった後に、全体を一体に樹脂封止して封止体１０が形成される。一体に封止体１０が形成された状態から、多層基板１及び封止体１０を切断して、夫々の半導体モジュールに分割するが、この分割の際に、切断の位置がずれた場合であっても、キャビティ１５によって電子部品の移動が規制されているので、電子部品が位置ずれにより封止体１０から部分的に露出するのを防止することができる。   In this semiconductor module manufacturing process, a plurality of multilayer substrates 1 are continuously formed vertically and horizontally, and an electronic component such as a capacitor 6, a resistor 7 or an inductor 8 is connected to the pad 5 by solder 9, or After the semiconductor device 12 is mounted on each multilayer substrate 1, the whole is integrally sealed with resin to form the sealing body 10. From the state in which the sealing body 10 is integrally formed, the multilayer substrate 1 and the sealing body 10 are cut and divided into respective semiconductor modules. This is the case where the cutting position is shifted during the division. However, since the movement of the electronic component is regulated by the cavity 15, it is possible to prevent the electronic component from being partially exposed from the sealing body 10 due to the displacement.

以上、本発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   Although the present invention has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention. It is.

本発明の一実施の形態である半導体モジュールを示す平面図である。It is a top view which shows the semiconductor module which is one embodiment of this invention. 本発明の一実施の形態である半導体モジュールを示す正面図である。It is a front view which shows the semiconductor module which is one embodiment of this invention. 図１中のａ‐ａ線に沿った縦断面図である。It is a longitudinal cross-sectional view along the aa line in FIG. 従来の半導体モジュールを示す正面図である。It is a front view which shows the conventional semiconductor module. 本発明の一実施の形態である半導体モジュールの変形例を示す正面図である。It is a front view which shows the modification of the semiconductor module which is one embodiment of this invention.

符号の説明Explanation of symbols

１…多層基板、２…導体層、３…絶縁層、４…ビア配線、５…パッド、６…コンデンサ、７…抵抗、８…インダクタ、９…ハンダ、１０…封止体、１１…外部端子、１２…半導体装置、１３…ボンディングワイヤ、１４，１５…キャビティ。
DESCRIPTION OF SYMBOLS 1 ... Multilayer substrate, 2 ... Conductive layer, 3 ... Insulating layer, 4 ... Via wiring, 5 ... Pad, 6 ... Capacitor, 7 ... Resistance, 8 ... Inductor, 9 ... Solder, 10 ... Sealing body, 11 ... External terminal , 12 ... Semiconductor device, 13 ... Bonding wire, 14, 15 ... Cavity.

Claims (5)

多層基板の部品搭載面に電子部品を実装し、封止体によって前記部品搭載面を覆った半導体モジュールにおいて、
前記多層基板の部品搭載面端部に、電子部品を収容するキャビティを形成し、このキャビティの側面が、収容する電子部品の幅よりも狭い幅で、前記多層基板の側面に開放されていることを特徴とする半導体モジュール。 In a semiconductor module in which an electronic component is mounted on a component mounting surface of a multilayer board and the component mounting surface is covered with a sealing body,
A cavity for accommodating an electronic component is formed at an end of the component mounting surface of the multilayer substrate, and a side surface of the cavity is narrower than a width of the electronic component to be accommodated and is open to the side surface of the multilayer substrate. A semiconductor module characterized by the following. 前記キャビティが多層基板を構成する１層目の絶縁層を除去して形成され、収容する電子部品が２層目の導体層に接続されていることを特徴とする請求項１に記載の半導体モジュール。 2. The semiconductor module according to claim 1, wherein the cavity is formed by removing a first insulating layer constituting a multilayer substrate, and an electronic component to be accommodated is connected to a second conductor layer. . 前記キャビティが多層基板を構成する１層目及び２層目の絶縁層を除去して形成され、収容する電子部品が３層目の導体層に接続されている
ことを特徴とする請求項１又は請求項２に記載の半導体モジュール。 The cavity is formed by removing the first and second insulating layers constituting the multilayer substrate, and the electronic component to be accommodated is connected to the third conductor layer. The semiconductor module according to claim 2. 前記多層基板の部品搭載面端部に加えて、部品搭載面の内方にも電子部品を収容するキャビティを形成したことを特徴とする請求項１乃至請求項３の何れか一項に記載の半導体モジュール。 4. The cavity according to claim 1, wherein a cavity for accommodating an electronic component is formed inward of the component mounting surface in addition to the end portion of the component mounting surface of the multilayer substrate. Semiconductor module. 多層基板の部品搭載面に電子部品を実装し、封止体によって前記部品搭載面を覆う半導体モジュールの製造方法において、
前記多層基板の部品搭載面端部には、電子部品を収容するキャビティを形成し、このキャビティの側面が、収容する電子部品の幅よりも狭い幅で、前記多層基板の側面に開放されており、このキャビティに電子部品を配置し、ハンダ等により多層基板のパッドに接続することを特徴とする半導体モジュールの製造方法。
In a method for manufacturing a semiconductor module, mounting electronic components on a component mounting surface of a multilayer substrate and covering the component mounting surface with a sealing body,
A cavity for accommodating an electronic component is formed at the end of the component mounting surface of the multilayer substrate, and a side surface of the cavity is narrower than a width of the electronic component to be accommodated and is open to the side surface of the multilayer substrate. A method of manufacturing a semiconductor module, wherein an electronic component is disposed in the cavity and connected to a pad of a multilayer substrate by solder or the like.
JP2004000390A 2004-01-05 2004-01-05 Semiconductor module and its manufacturing method Pending JP2005197354A (en)

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