JP2004128192A - Laminated module - Google Patents

Laminated module Download PDF

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Publication number
JP2004128192A
JP2004128192A JP2002289773A JP2002289773A JP2004128192A JP 2004128192 A JP2004128192 A JP 2004128192A JP 2002289773 A JP2002289773 A JP 2002289773A JP 2002289773 A JP2002289773 A JP 2002289773A JP 2004128192 A JP2004128192 A JP 2004128192A
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JP
Japan
Prior art keywords
substrate
substrates
laminated
signal terminals
laminated module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002289773A
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Japanese (ja)
Inventor
Shinichi Kodama
児玉　真一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electronic Components Co Ltd
Sanyo Electric Co Ltd
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Publication date
Application filed by Sanyo Electronic Components Co Ltd, Sanyo Electric Co Ltd filed Critical Sanyo Electronic Components Co Ltd
Priority to JP2002289773A priority Critical patent/JP2004128192A/en
Publication of JP2004128192A publication Critical patent/JP2004128192A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Combinations Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated module to which a flip chip of a bare chip can be mounted, and which is smaller than the prior art. <P>SOLUTION: The laminated module is structured by joining a first lamination substrate 1 to a second lamination substrate 2, a cavity 11 is dented on a surface of the first lamination substrate 1, and a sealing pattern 6 is formed so as to surround the cavity 11. On the other hand, a bare chip 4 is mounted as a flip chip on a reverse surface of the second lamination substrate 2. Further, a sealing pattern 61 is formed at a position corresponding to the sealing pattern 6 of the first lamination substrate 1 on the reverse surface of the second lamination substrate 2. The first lamination substrate 1 and the second lamination substrate 2 are integrated by joining the sealing patterns 6, 61 to each other by a solder. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、携帯電話機などの電子機器に装備される電子部品としての積層モジュールに関するものである。
【０００２】
【従来の技術】
従来、携帯電話機などの小型の電子機器においては、複数の回路素子を１チップの積層モジュールに集積化して、該積層モジュールを回路基板上に実装することが行なわれている。
積層モジュールにおいては、図１３に示す如く、複数のセラミックス層が積層されて積層基板（９）が構成され、該積層基板（９）中に、コンデンサやインダクターを構成すべき内蔵回路パターン（５４）を作り込み、積層基板（９）の表面には、基板中に作り込むことが出来ない大型パッケージ部品（３４）や小型部品（３５）を実装する（非特許文献１参照）。
【０００３】
しかしながら、近年、携帯電話機などの電子機器の小型化に伴って、積層モジュールに対する小型化の要求が高まっており、この様な要求に応じて、図１４に示す如く、大型パッケージ部品に内蔵されていたベアチップ（４１）を積層基板（９）に埋め込んだ積層モジュールが開発されている。
【０００４】
該積層モジュールにおいては、積層基板（９）の表面に第１キャビティ部（９２）及び第２キャビティ部（９３）からなる段付きのキャビティ（９１）が凹設されており、第１キャビティ部（９２）の底面にベアチップ（４１）が設置されると共に、第２キャビティ部（９３）の底面には、複数の信号端子（９５）が設けられており、ベアチップ（４）と信号端子（９５）（９５）とがワイヤー（９６）によって互いに接続されている。
積層基板（９）の表面には、キャビティ（９１）を包囲して、金などからなる封止パターン（９４）が形成されており、該封止パターン（９４）にリッド（９７）の外周部を半田によって接合することにより、キャビティ（９１）を気密状態に封止している。又、積層基板（９）の表面には、小型部品（３６）が実装されている。
【０００５】
しかしながら、図１４に示す積層モジュールにおいては、リッド（９７）が積層基板（９）の表面を大きく覆うために、実装面積が減少するばかりでなく、段付きのキャビティ（９１）が積層基板（９）内で大きなスペースを占めるため、内蔵回路パターン（５４）を形成するためのスペースが減少する問題があった。
【０００６】
そこで、図１５に示す如く、積層基板（９）のキャビティ（９１）にベアチップ（４１）を設置し、該ベアチップ（４１）を端子（９８）（９８）に直接にフリップチップ搭載することが考えられる。該構造によれば、キャビティ（９１）を段付き形状とする必要がないため、リッド（９７）の小型化、キャビティ（９１）の小容積化を図ることが出来る。
【０００７】
【特許文献１】
特許第３０４８５９２号公報
【特許文献２】
特許第３０６７６１２号公報
【非特許文献１】
「日経エレクトロニクス」１９９９年７月２６日（ｎｏ．７４８）、ｐ．１４０−１５２
【０００８】
【発明が解決しようとする課題】
ところが、図１５に示す積層モジュールにおいては、キャビティ（９１）の底面を精度の高い平面に仕上げることが困難であるために、ベアチップ（４１）のフリップチップ搭載が困難である問題があった。
【０００９】
そこで本発明の目的は、上記の問題を一挙に解決して、ベアチップのフリップチップ搭載が可能であり、然も従来よりも小型の積層モジュールを提供することである。
【００１０】
【課題を解決する為の手段】
本発明に係る積層モジュールは、積層構造を有して回路パターンが内蔵されると共に表面にキャビティが凹設された第１基板と、第１基板の表面に接合された第２基板とを具え、第２基板の第１基板との対向面には、チップ部品が搭載され、該チップ部品は第１基板のキャビティに収容されている。
【００１１】
具体的構成において、第２基板は積層構造を有して回路パターンが内蔵されている。
又、第１基板と第２基板の内、少なくとも何れか一方の基板には、他方の基板とは反対側に露出する面に、１或いは複数の電子部品が搭載されている。
【００１２】
上記本発明の積層モジュールにおいては、第２基板の第１基板との対向面が平面に形成されており、該対向面にチップ部品が搭載されているので、該対向面を高い平面度に仕上げることは容易であり、これによってチップ部品のフリップチップ搭載が可能となる。
【００１３】
具体的構成において、第１基板と第２基板の対向面にはそれぞれ、前記キャビティを包囲する封止パターンが形成され、両基板の封止パターンが互いに接合されて、前記キャビティが封止されている。
これによって、キャビティ内は外部雰囲気と完全に遮断されるので、チップ部品をベアチップとした場合の外部雰囲気によるチップの劣化が防止される。
【００１４】
又、具体的構成において、第１基板と第２基板の対向面にはそれぞれ、信号端子が設けられ、両基板の信号端子が互いに接触することによって、両基板が互いに電気的に接続されている。
ここで、両基板の対向面間には、両基板の互いに接触する封止パターンと信号端子との間に、絶縁性樹脂層が形成されている。これによって、封止パターンと信号端子の間の短絡が防止される。
【００１５】
或いは、第１基板と第２基板にはそれぞれ信号端子が内蔵され、両基板の信号端子が互いに対向して、両信号端子の電界的若しくは磁界的な結合によって、両基板が互いに電気的に接続されている。
ここで、両基板の対向面間には、両基板の互いに対向する信号端子の間に、絶縁性樹脂層が介在している。これによって、封止パターンどうしを半田接合する場合の半田の拡がりが防止され、この結果、信号端子どうしの電界的若しくは磁界的な結合が確保される。
【００１６】
又、具体的構成において、第１基板と第２基板の対向面にはそれぞれ、信号端子が設けられ、該信号端子の表面を覆うと共に該信号端子と封止パターンとの間に介在する絶縁性樹脂層が形成され、両基板の信号端子が絶縁性樹脂層を介して互いに対向し、両信号端子の電界的若しくは磁界的な結合によって、両基板が互いに電気的に接続されている。
これによって、封止パターンどうしを半田接合する場合の半田の拡がりが防止され、この結果、信号端子どうしの電界的若しくは磁界的な結合が確保されると共に、封止パターンと信号端子の間の短絡が防止される。
【００１７】
又、具体的構成において、外側に露出する第１基板と第２基板の表面にはそれぞれ、信号端子が設けられ、両基板の信号端子がワイヤーにより互いに連結されて、両基板が互いに電気的に接続されている。
或いは、第１基板と第２基板の同一方向に露出する面に跨って、チップ部品が搭載され、該チップ部品の一対の端子が両基板に設けられた端子部にそれぞれ接合されて、両基板が互いに電気的に接続されている。
【００１８】
【発明の効果】
本発明に係る積層モジュールによれば、第２基板の平坦な面にチップ部品が搭載されているので、該チップ部品のフリップチップ搭載が可能であると共に、第１基板のキャビティを段付きに形成する必要がないので、従来の積層モジュールよりも小型化が可能である。
【００１９】
【発明の実施の形態】
以下、本発明の実施の形態につき、図面に沿って具体的に説明する。
図１及び図２に示す本発明の積層モジュールは、複数のセラミックス層からなる第１積層基板（１）と、複数のセラミックス層からなる第２積層基板（２）とを接合して構成され、両基板（１）（２）中に、コンデンサやインダクター等を構成すべき内蔵回路パターン（５）（５１）が作り込まれている。
【００２０】
第１積層基板（１）の表面には、段差部を有しないキャビティ（１１）が凹設されると共に、該キャビティ（１１）を包囲して、表面に金メッキを施した封止パターン（６）が形成されている。又、第１積層基板（１）の表面には、内蔵回路パターン（５）に繋がる信号端子（７）が形成されている。
【００２１】
一方、第２積層基板（２）の第１積層基板（１）との対向面（裏面）には、ベアチップ（４）がフリップチップ搭載され、表面には、複数の小型部品（３）が実装されている。又、第２積層基板（２）の裏面には、第１積層基板（１）の封止パターン（６）と対応する位置に、表面に金メッキを施した封止パターン（６１）が形成されている。更に、第２積層基板（２）の裏面には、第１積層基板（１）の信号端子（７）と対向する位置に、内蔵回路パターン（５１）に繋がる信号端子（７１）が形成されている。
又、第２積層基板（２）の表面には、複数の小型部品（３）が実装されている。
【００２２】
上記第１積層基板（１）と第２積層基板（２）とを図１の如く互いに対向せしめ、封止パターン（６）（６１）どうし並びに信号端子（７）（７１）どうしを半田によって接合することにより、積層モジュールが組み立てられる。この結果、キャビティ（１１）が気密状態に封止され、該キャビティ（１１）内に、第２積層基板（２）のベアチップ（４）が収容されることになる。又、第１積層基板（１）の信号端子（７）と第２積層基板（２）の信号端子（７１）とが互いに接続されて、第１積層基板（１）と第２積層基板（２）とが電気的に接続されることになる。
【００２３】
上記積層モジュールにおいては、平板状を呈する第２積層基板（２）の裏面にベアチップ（４）が搭載されており、該裏面は高い平面度を有しているので、ベアチップ（４）をフリップチップ搭載することに問題はない。
又、該ベアチップ（４）は、キャビティ（１１）内に収容されて、外部雰囲気に晒されることはないので、長期間に亘って高い信頼性を維持する。
【００２４】
又、上記積層モジュールにおいては、第２積層基板（２）の全表面を小型部品（３）の実装に利用することが出来るので、広い実装面積を確保することが出来る。
更に、第１積層基板（１）には、段差部のないキャビティ（１１）が凹設されているので、キャビティ（１１）の容積を必要最小限の大きさとすることが出来、これによって、第１積層基板（１）内には内蔵回路パターン（５）を形成するための大きなスペースを確保することが出来る。
【００２５】
図３及び図４に示す積層モジュールは、基本的には図１及び図２に示す積層モジュールと同一構造であるが、第１積層基板（１）と第２積層基板（２）の間の電気的接続の構造が異なっている。
即ち、第１積層基板（１）には内蔵回路パターン（５）に繋がる信号端子（５２）が内蔵されると共に、第２積層基板（２）には内蔵回路パターン（５１）に繋がる信号端子（５３）が内蔵されており、両信号端子（５２）（５３）が互いに対向して、両信号端子（５２）（５３）の電界的若しくは磁界的な結合により、コンデンサ若しくはトランスが構成されて、両基板（１）（２）が互いに電気的に接続されている。
【００２６】
図５及び図６に示す積層モジュールは、図１及び図２に示す積層モジュールと同一構造を有し、更に図５及び図６に示す如く、第１積層基板（１）の表面には、信号端子（７）と封止パターン（６）の間にレジスト層（８）が形成され、第２積層基板（２）の裏面には、信号端子（７１）と封止パターン（６１）の間にレジスト層（８１）が形成されている。
これによって、信号端子（７）（７１）と封止パターン（６）（６１）の間の短絡が防止される。
【００２７】
図７及び図８に示す積層モジュールは、図３及び図４に示す積層モジュールと同一構造を有し、更に図７及び図８に示す如く、第１積層基板（１）の表面には、信号端子（５２）と対応する位置にレジスト層（８２）が形成されると共に、第２積層基板（２）の裏面には、信号端子（５３）と対応する位置にレジスト層（８３）が形成されている。
従って、両基板（１）（２）の互いに対向する信号端子（５２）（５３）の間に、レジスト層（８２）（８３）が介在することとなって、封止パターン（６）（６１）どうしを半田接合する際に半田が信号端子（５２）（５３）の間に拡がることが防止され、この結果、信号端子（５２）（５３）どうしの電気的な結合が遮られることはない。
【００２８】
図９及び図１０に示す積層モジュールにおいては、第１積層基板（１）の表面と第２積層基板（２）の裏面に、互いに対向する信号端子（７）（７１）が設けられている。そして、第１積層基板（１）の信号端子（７）と封止パターン（６）の間にレジスト層（８）が形成されると共に、信号端子（７）を覆ってレジスト層（８４）が形成されている。又、第２積層基板（２）の信号端子（７１）と封止パターン（６１）の間にレジスト層（８１）が形成されると共に、信号端子（７１）を覆ってレジスト層（８５）が形成されている。
該積層モジュールにおいては、両基板（１）（２）の信号端子（７）（７１）がレジスト層（８４）（８５）を介して互いに対向し、両信号端子（７）（７１）の電界的若しくは磁界的な結合により、コンデンサ若しくはトランスが構成されて、両基板（１）（２）が互いに電気的に接続されている。
【００２９】
該積層モジュールによれば、封止パターン（６）（６１）どうしを半田接合する場合に半田が信号端子（７）（７１）の間に拡がることが防止され、この結果、信号端子（７）（７１）どうしの電気的な結合が遮られることが防止されると共に、信号端子（７）（７１）と封止パターン（６）（６１）の間の短絡が防止される。
【００３０】
図１１に示す積層モジュールにおいては、第１積層基板（１）の表面に信号端子（７４）が設けられると共に、第２積層基板（２）の表面に信号端子（７５）が設けられ、両信号端子（７４）（７５）がワイヤー（７６）により互いに連結されて、両基板（１）（２）が互いに電気的に接続されている。
【００３１】
更に図１２に示す積層モジュールにおいては、第１積層基板（１）の表面と第２積層基板（２）の表面とが同一面に揃えられ、両表面に跨って、小型部品（３１）が搭載され、該小型部品（３１）の一対の端子（３２）（３３）が、両基板（１）（２）上のパッドにそれぞれ接合されて、両基板（１）（２）が互いに電気的に接続されている。
【００３２】
上記の何れの積層モジュールにおいても、第１積層基板（１）のキャビティ（１１）を段付きに形成する必要がなく、然もキャビティ（１１）は第２積層基板（２）によって覆われ、該第２積層基板（２）の表面に複数の電子部品を搭載することが出来るので、従来の積層モジュールよりも大幅な小型化が可能である。
【図面の簡単な説明】
【図１】本発明に係る積層モジュールの断面図である。
【図２】該積層モジュールを分解して示す断面図である。
【図３】本発明に係る他の積層モジュールの断面図である。
【図４】該積層モジュールを分解して示す断面図である。
【図５】本発明に係る更に他の積層モジュールの断面図である。
【図６】該積層モジュールを分解して示す断面図である。
【図７】本発明に係る更に他の積層モジュールの断面図である。
【図８】該積層モジュールを分解して示す断面図である。
【図９】本発明に係る更に他の積層モジュールの断面図である。
【図１０】該積層モジュールを分解して示す断面図である。
【図１１】本発明に係る更に他の積層モジュールの断面図である。
【図１２】本発明に係る更に他の積層モジュールの断面図である。
【図１３】従来の積層モジュールの断面図である。
【図１４】従来の他の積層モジュールを分解して示す断面図である。
【図１５】従来の更に他の積層モジュールを分解して示す断面図である。
【符号の説明】
（１）　第１積層基板
（１１）　キャビティ
（２）　第２積層基板
（３）　小型部品
（３１）　小型部品
（４）　ベアチップ
（５）　内蔵回路パターン
（５１）　内蔵回路パターン
（５２）　信号端子
（５３）　信号端子
（６）　封止パターン
（６１）　封止パターン
（７）　信号端子
（７１）　信号端子
（７６）　ワイヤー
（８）　レジスト層
（８１）　レジスト層[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a laminated module as an electronic component mounted on an electronic device such as a mobile phone.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a small electronic device such as a mobile phone, a plurality of circuit elements are integrated in a one-chip laminated module, and the laminated module is mounted on a circuit board.
In the laminated module, as shown in FIG. 13, a plurality of ceramic layers are laminated to form a laminated substrate (9). In the laminated substrate (9), a built-in circuit pattern (54) for forming a capacitor or an inductor is formed. And a large package component (34) or a small component (35) that cannot be formed in the substrate is mounted on the surface of the laminated substrate (9) (see Non-Patent Document 1).
[0003]
However, in recent years, with the downsizing of electronic devices such as mobile phones, there has been an increasing demand for miniaturization of stacked modules. In response to such demands, as shown in FIG. A laminated module in which the bare chip (41) is embedded in a laminated substrate (9) has been developed.
[0004]
In the laminated module, a stepped cavity (91) including a first cavity portion (92) and a second cavity portion (93) is recessed on the surface of the laminated substrate (9), and the first cavity portion (91) is formed. A bare chip (41) is installed on the bottom surface of 92), and a plurality of signal terminals (95) are provided on the bottom surface of the second cavity (93). The bare chip (4) and the signal terminal (95) are provided. (95) are connected to each other by a wire (96).
A sealing pattern (94) made of gold or the like is formed on the surface of the laminated substrate (9) so as to surround the cavity (91), and the sealing pattern (94) has an outer peripheral portion of the lid (97). Are bonded by solder to seal the cavity (91) in an airtight state. A small component (36) is mounted on the surface of the multilayer board (9).
[0005]
However, in the laminated module shown in FIG. 14, since the lid (97) largely covers the surface of the laminated substrate (9), not only the mounting area is reduced, but also the stepped cavity (91) is formed in the laminated substrate (9). ) Occupies a large space, so that there is a problem that the space for forming the built-in circuit pattern (54) is reduced.
[0006]
Therefore, as shown in FIG. 15, a bare chip (41) is installed in the cavity (91) of the laminated substrate (9), and the bare chip (41) is directly flip-chip mounted on the terminals (98) (98). Can be According to this structure, since the cavity (91) does not need to have a stepped shape, the size of the lid (97) and the volume of the cavity (91) can be reduced.
[0007]
[Patent Document 1]
Japanese Patent No. 3048592 [Patent Document 2]
Japanese Patent No. 3067612 [Non-Patent Document 1]
"Nikkei Electronics" July 26, 1999 (No. 748), p. 140-152
[0008]
[Problems to be solved by the invention]
However, the stacked module shown in FIG. 15 has a problem in that it is difficult to finish the bottom surface of the cavity (91) with a highly accurate flat surface, and thus it is difficult to mount the bare chip (41) on the flip chip.
[0009]
Therefore, an object of the present invention is to solve the above-mentioned problems at once, and to provide a stacked module that can be mounted on a flip chip of a bare chip and is smaller than a conventional one.
[0010]
[Means for solving the problem]
A laminated module according to the present invention includes a first substrate having a laminated structure, in which a circuit pattern is embedded, and a cavity is formed in the surface, and a second substrate joined to the surface of the first substrate, A chip component is mounted on a surface of the second substrate facing the first substrate, and the chip component is housed in a cavity of the first substrate.
[0011]
In a specific configuration, the second substrate has a laminated structure and has a built-in circuit pattern.
Further, at least one of the first substrate and the second substrate has one or a plurality of electronic components mounted on a surface exposed on the side opposite to the other substrate.
[0012]
In the laminated module of the present invention, the opposing surface of the second substrate to the first substrate is formed in a flat surface, and the chip component is mounted on the opposing surface, so that the opposing surface is finished to a high flatness. This is easy, and this allows flip-chip mounting of chip components.
[0013]
In a specific configuration, a sealing pattern surrounding the cavity is formed on each of the opposing surfaces of the first substrate and the second substrate, and the sealing patterns of both substrates are joined to each other to seal the cavity. I have.
As a result, since the inside of the cavity is completely shut off from the external atmosphere, deterioration of the chip due to the external atmosphere when the chip component is a bare chip is prevented.
[0014]
In a specific configuration, a signal terminal is provided on each of the opposing surfaces of the first substrate and the second substrate, and the signal terminals of the two substrates are in contact with each other, so that the two substrates are electrically connected to each other. .
Here, an insulating resin layer is formed between the opposing surfaces of the two substrates and between the signal terminals and the sealing patterns of the two substrates that are in contact with each other. This prevents a short circuit between the sealing pattern and the signal terminal.
[0015]
Alternatively, the first substrate and the second substrate each have a signal terminal built therein, and the signal terminals of the two substrates are opposed to each other, and the two substrates are electrically connected to each other by an electric or magnetic coupling between the two signal terminals. Have been.
Here, an insulating resin layer is interposed between the opposing surfaces of the two substrates and between the signal terminals of the two substrates that oppose each other. This prevents the spread of the solder when the sealing patterns are joined by soldering. As a result, electric or magnetic coupling between the signal terminals is ensured.
[0016]
In a specific configuration, a signal terminal is provided on each of opposing surfaces of the first substrate and the second substrate. The signal terminal covers a surface of the signal terminal and has an insulating property interposed between the signal terminal and the sealing pattern. A resin layer is formed, and the signal terminals of both substrates are opposed to each other via an insulating resin layer, and both substrates are electrically connected to each other by electric or magnetic coupling between the signal terminals.
This prevents the spread of solder when the sealing patterns are joined to each other by soldering. As a result, electric or magnetic coupling between the signal terminals is ensured, and a short circuit between the sealing pattern and the signal terminals is achieved. Is prevented.
[0017]
In a specific configuration, a signal terminal is provided on each of the surfaces of the first substrate and the second substrate that are exposed to the outside, and the signal terminals of the two substrates are connected to each other by wires, so that the two substrates are electrically connected to each other. It is connected.
Alternatively, a chip component is mounted on a surface of the first substrate and the second substrate that are exposed in the same direction, and a pair of terminals of the chip component are respectively joined to terminal portions provided on the two substrates. Are electrically connected to each other.
[0018]
【The invention's effect】
According to the laminated module of the present invention, since the chip component is mounted on the flat surface of the second substrate, the chip component can be flip-chip mounted, and the cavity of the first substrate is formed stepwise. Since there is no need to perform this, it is possible to reduce the size of the conventional laminated module.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
The laminated module of the present invention shown in FIGS. 1 and 2 is configured by joining a first laminated substrate (1) composed of a plurality of ceramic layers and a second laminated substrate (2) composed of a plurality of ceramic layers, In both substrates (1) and (2), built-in circuit patterns (5) and (51) for forming capacitors, inductors and the like are formed.
[0020]
A cavity (11) having no step is formed in the surface of the first laminated substrate (1), and the sealing pattern (6) surrounding the cavity (11) and having its surface plated with gold. Is formed. On the surface of the first laminated substrate (1), signal terminals (7) connected to the built-in circuit pattern (5) are formed.
[0021]
On the other hand, a bare chip (4) is flip-chip mounted on a surface (back surface) of the second multilayer substrate (2) facing the first multilayer substrate (1), and a plurality of small components (3) are mounted on the surface. Have been. On the back surface of the second laminated substrate (2), a sealing pattern (61) whose surface is plated with gold is formed at a position corresponding to the sealing pattern (6) of the first laminated substrate (1). I have. Further, a signal terminal (71) connected to the built-in circuit pattern (51) is formed on a back surface of the second laminated substrate (2) at a position facing the signal terminal (7) of the first laminated substrate (1). I have.
A plurality of small components (3) are mounted on the surface of the second laminated substrate (2).
[0022]
The first laminated substrate (1) and the second laminated substrate (2) are opposed to each other as shown in FIG. 1, and the sealing patterns (6) and (61) and the signal terminals (7) and (71) are joined by soldering. By doing so, a laminated module is assembled. As a result, the cavity (11) is hermetically sealed, and the bare chip (4) of the second laminated substrate (2) is accommodated in the cavity (11). Further, the signal terminals (7) of the first laminated substrate (1) and the signal terminals (71) of the second laminated substrate (2) are connected to each other, so that the first laminated substrate (1) and the second laminated substrate (2) are connected. ) Are electrically connected.
[0023]
In the laminated module, the bare chip (4) is mounted on the back surface of the second laminated substrate (2) having a flat shape, and since the back surface has high flatness, the bare chip (4) is flip-chip mounted. There is no problem with mounting.
Further, since the bare chip (4) is housed in the cavity (11) and is not exposed to the external atmosphere, high reliability is maintained for a long period of time.
[0024]
Further, in the laminated module, since the entire surface of the second laminated substrate (2) can be used for mounting the small component (3), a large mounting area can be secured.
Further, since the cavity (11) having no step is recessed in the first laminated substrate (1), the volume of the cavity (11) can be reduced to a necessary minimum. A large space for forming the built-in circuit pattern (5) can be secured in one laminated substrate (1).
[0025]
The laminated module shown in FIGS. 3 and 4 has basically the same structure as the laminated module shown in FIGS. 1 and 2, but the electric power between the first laminated substrate (1) and the second laminated substrate (2). Connection structure is different.
That is, the first laminated substrate (1) has a built-in signal terminal (52) connected to the built-in circuit pattern (5), and the second laminated substrate (2) has a signal terminal (52) connected to the built-in circuit pattern (51). 53) are built in, and both signal terminals (52) and (53) are opposed to each other, and a capacitor or a transformer is formed by electric or magnetic coupling between the two signal terminals (52) and (53). Both substrates (1) and (2) are electrically connected to each other.
[0026]
The laminated module shown in FIGS. 5 and 6 has the same structure as the laminated module shown in FIGS. 1 and 2, and further has a signal on the surface of the first laminated substrate (1) as shown in FIGS. A resist layer (8) is formed between the terminal (7) and the sealing pattern (6), and on the back surface of the second laminated substrate (2), between the signal terminal (71) and the sealing pattern (61). A resist layer (81) is formed.
This prevents a short circuit between the signal terminals (7) (71) and the sealing patterns (6) (61).
[0027]
The laminated module shown in FIGS. 7 and 8 has the same structure as the laminated module shown in FIGS. 3 and 4, and further has a signal on the surface of the first laminated substrate (1) as shown in FIGS. A resist layer (82) is formed at a position corresponding to the terminal (52), and a resist layer (83) is formed at a position corresponding to the signal terminal (53) on the back surface of the second laminated substrate (2). ing.
Therefore, the resist layers (82) and (83) are interposed between the signal terminals (52) and (53) of the substrates (1) and (2) facing each other, so that the sealing patterns (6) and (61) are formed. ) When soldering together, the spread of the solder between the signal terminals (52) and (53) is prevented, and as a result, the electrical connection between the signal terminals (52) and (53) is not interrupted. .
[0028]
In the laminated module shown in FIGS. 9 and 10, signal terminals (7) (71) facing each other are provided on the front surface of the first laminated substrate (1) and the back surface of the second laminated substrate (2). Then, a resist layer (8) is formed between the signal terminal (7) of the first laminated substrate (1) and the sealing pattern (6), and the resist layer (84) covers the signal terminal (7). Is formed. Further, a resist layer (81) is formed between the signal terminal (71) of the second laminated substrate (2) and the sealing pattern (61), and the resist layer (85) covers the signal terminal (71). Is formed.
In the laminated module, the signal terminals (7) and (71) of the two substrates (1) and (2) face each other via the resist layers (84) and (85), and the electric field of the signal terminals (7) and (71). A capacitor or a transformer is formed by a magnetic or magnetic coupling, and the two substrates (1) and (2) are electrically connected to each other.
[0029]
According to the laminated module, when the sealing patterns (6) and (61) are joined by soldering, the solder is prevented from spreading between the signal terminals (7) and (71). As a result, the signal terminals (7) are prevented. (71) It is possible to prevent the electrical coupling between them from being interrupted, and to prevent a short circuit between the signal terminals (7) (71) and the sealing patterns (6) (61).
[0030]
In the laminated module shown in FIG. 11, signal terminals (74) are provided on the surface of the first laminated substrate (1), and signal terminals (75) are provided on the surface of the second laminated substrate (2). The terminals (74) and (75) are connected to each other by a wire (76), and the substrates (1) and (2) are electrically connected to each other.
[0031]
Further, in the laminated module shown in FIG. 12, the surface of the first laminated substrate (1) and the surface of the second laminated substrate (2) are aligned on the same plane, and the small component (31) is mounted on both surfaces. Then, the pair of terminals (32) and (33) of the small component (31) are respectively bonded to pads on both substrates (1) and (2), and the two substrates (1) and (2) are electrically connected to each other. It is connected.
[0032]
In any of the above-mentioned laminated modules, it is not necessary to form the cavity (11) of the first laminated substrate (1) stepwise, and the cavity (11) is covered with the second laminated substrate (2). Since a plurality of electronic components can be mounted on the surface of the second laminated substrate (2), the size can be significantly reduced as compared with the conventional laminated module.
[Brief description of the drawings]
FIG. 1 is a sectional view of a laminated module according to the present invention.
FIG. 2 is an exploded sectional view showing the laminated module.
FIG. 3 is a cross-sectional view of another laminated module according to the present invention.
FIG. 4 is an exploded sectional view showing the laminated module.
FIG. 5 is a cross-sectional view of still another laminated module according to the present invention.
FIG. 6 is an exploded sectional view of the laminated module.
FIG. 7 is a sectional view of still another laminated module according to the present invention.
FIG. 8 is an exploded sectional view showing the laminated module.
FIG. 9 is a cross-sectional view of still another laminated module according to the present invention.
FIG. 10 is an exploded sectional view showing the laminated module.
FIG. 11 is a cross-sectional view of still another laminated module according to the present invention.
FIG. 12 is a sectional view of still another laminated module according to the present invention.
FIG. 13 is a sectional view of a conventional laminated module.
FIG. 14 is an exploded cross-sectional view showing another conventional laminated module.
FIG. 15 is an exploded cross-sectional view showing another conventional laminated module.
[Explanation of symbols]
(1) First laminated substrate (11) Cavity (2) Second laminated substrate (3) Small component (31) Small component (4) Bare chip (5) Built-in circuit pattern (51) Built-in circuit pattern (52) Signal terminal ( 53) signal terminal (6) sealing pattern (61) sealing pattern (7) signal terminal (71) signal terminal (76) wire (8) resist layer (81) resist layer

Claims (11)

積層構造を有して回路パターンが内蔵されると共に表面にキャビティが凹設された第１基板と、第１基板の表面に接合された第２基板とを具え、第２基板の第１基板との対向面には、チップ部品が搭載され、該チップ部品は第１基板のキャビティに収容されている積層モジュール。A first substrate having a laminated structure, in which a circuit pattern is embedded, and a cavity formed in a surface thereof, and a second substrate bonded to a surface of the first substrate; The chip module is mounted on the opposing surface of the first module, and the chip component is housed in the cavity of the first substrate. 第２基板は積層構造を有して回路パターンが内蔵されている請求項１に記載の積層モジュール。The laminated module according to claim 1, wherein the second substrate has a laminated structure and has a built-in circuit pattern. 第１基板と第２基板の対向面にはそれぞれ、前記キャビティを包囲する封止パターンが形成され、両基板の封止パターンが互いに接合されて、前記キャビティが封止されている請求項２に記載の積層モジュール。The sealing pattern surrounding the cavity is formed on each of the opposing surfaces of the first substrate and the second substrate, and the sealing patterns of both substrates are bonded to each other to seal the cavity. The laminated module as described in the above. 第１基板と第２基板の対向面にはそれぞれ、信号端子が設けられ、両基板の信号端子が互いに接触することによって、両基板が互いに電気的に接続されている請求項３に記載の積層モジュール。4. The lamination according to claim 3, wherein signal terminals are provided on opposing surfaces of the first substrate and the second substrate, respectively, and the signal terminals of the two substrates are electrically connected to each other by contacting the signal terminals of the two substrates. module. 第１基板と第２基板にはそれぞれ信号端子が内蔵され、両基板の信号端子が互いに対向して、両信号端子の電界的若しくは磁界的な結合によって、両基板が互いに電気的に接続されている請求項３に記載の積層モジュール。The first substrate and the second substrate have built-in signal terminals, respectively. The signal terminals of the two substrates are opposed to each other, and the two substrates are electrically connected to each other by electric or magnetic coupling between the two signal terminals. The laminated module according to claim 3. 両基板の対向面間には、両基板の互いに接触する封止パターンと信号端子との間に、絶縁性樹脂層が形成されている請求項４に記載の積層モジュール。5. The laminated module according to claim 4, wherein an insulating resin layer is formed between the opposing surfaces of the two substrates and between the sealing pattern and the signal terminal of the two substrates that are in contact with each other. 両基板の対向面間には、両基板の互いに対向する信号端子の間に、絶縁性樹脂層が介在している請求項５に記載の積層モジュール。The laminated module according to claim 5, wherein an insulating resin layer is interposed between the opposing surfaces of the two substrates and between the signal terminals of the two substrates facing each other. 第１基板と第２基板の対向面にはそれぞれ、信号端子が設けられ、該信号端子の表面を覆うと共に該信号端子と封止パターンとの間に介在する絶縁性樹脂層が形成され、両基板の信号端子が絶縁性樹脂層を介して互いに対向し、両信号端子の電界的若しくは磁界的な結合によって、両基板が互いに電気的に接続されている請求項３に記載の積層モジュール。A signal terminal is provided on each of the opposing surfaces of the first substrate and the second substrate, and an insulating resin layer that covers a surface of the signal terminal and is interposed between the signal terminal and the sealing pattern is formed. 4. The laminated module according to claim 3, wherein the signal terminals of the substrates are opposed to each other via the insulating resin layer, and the two substrates are electrically connected to each other by electric or magnetic coupling between the signal terminals. 外側に露出する第１基板と第２基板の表面にはそれぞれ、信号端子が設けられ、両基板の信号端子がワイヤーにより互いに連結されて、両基板が互いに電気的に接続されている請求項３に記載の積層モジュール。4. A signal terminal is provided on each of the surfaces of the first substrate and the second substrate exposed to the outside, and the signal terminals of the two substrates are connected to each other by a wire, and the two substrates are electrically connected to each other. A laminated module according to item 1. 第１基板と第２基板の同一方向に露出する面に跨って、チップ部品が搭載され、該チップ部品の一対の端子が両基板に設けられた端子部にそれぞれ接合されて、両基板が互いに電気的に接続されている請求項３に記載の積層モジュール。A chip component is mounted over the surfaces of the first substrate and the second substrate that are exposed in the same direction, and a pair of terminals of the chip component are respectively joined to terminal portions provided on the two substrates, so that the two substrates are separated from each other. The laminated module according to claim 3, which is electrically connected. 第１基板と第２基板の内、少なくとも何れか一方の基板には、他方の基板とは反対側に露出する面に、１或いは複数の電子部品が搭載されている請求項１乃至請求項１０の何れかに記載の積層モジュール。11. The electronic device according to claim 1, wherein at least one of the first substrate and the second substrate has one or more electronic components mounted on a surface exposed to a side opposite to the other substrate. The laminated module according to any one of the above.
JP2002289773A 2002-10-02 2002-10-02 Laminated module Pending JP2004128192A (en)

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US7380337B2 (en) 2005-03-18 2008-06-03 Alps Electric Co., Ltd. Holder for electronic component, holding sheet for electronic component, electronic module using holder, electronic module using holding sheet, lamination of electronic modules, method for manufacturing electronic module, and method for testing electronic module
US7679920B2 (en) 2008-05-09 2010-03-16 Solarflare Communications, Inc. Cooling air distribution scheme for communication boards
US8345418B2 (en) 2008-05-09 2013-01-01 Marvell International Ltd. Cooling configuration for communication boards

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