JP2005191174A - Fuse, semiconductor device having the same and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fuse on a semiconductor substrate which prevents short-circuit from occurring after weld cutting, a semiconductor device having the fuse and a method of manufacturing the fuse. <P>SOLUTION: In the fuse composed of a fuse layer on a semiconductor substrate and a first and second electrodes connected to the fuse layer, a high resistance region having a high resistance value partly is formed between the first and second electrodes and located nearer either the first or second electrode disposed at the low-potential side. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a fuse formed on a semiconductor substrate, a semiconductor device having the fuse, and a method for manufacturing the fuse.

  Conventionally, in a semiconductor device having a programmable gate array structure, a semiconductor device capable of repairing a defect in a memory cell, or an analog device semiconductor device capable of adjusting characteristics, a fuse composed of a fuse layer provided on a semiconductor substrate Are provided, and programming, defect repair, or characteristic adjustment is performed by selectively cutting the fuse (see, for example, Patent Document 1).

  As shown in FIG. 2, such a fuse has an insulating film 200 formed on the upper surface of the semiconductor substrate 100, and a fuse layer 300 made of polysilicon is formed on the upper surface of the insulating film 200. After the impurity is implanted into the fuse layer 300 so as to have the resistivity, the fuse layer 300 is patterned into a predetermined shape.

Thereafter, a coating insulating film 400 made of silicon nitride for covering the fuse layer 300 is provided on the upper surface of the fuse layer 300, and the first electrode opening 500 and the first electrode opening 500 are spaced apart from each other at predetermined positions of the coating insulating film 400. A second electrode opening 600 is provided, a metal film is formed on the upper surface of the semiconductor substrate 100 by sputtering or the like, and the metal film is patterned into a predetermined shape to form a first electrode 700 and a second electrode 800.
JP-A-10-335594

  However, when the fuse layer is blown by passing a high current between the first electrode and the second electrode connected to the fuse layer, the first electrode and the second electrode are generally formed in the uniformly formed fuse layer. One where the first electrode and the second electrode have a higher potential than the middle part of the electrode, and fusing is likely to occur near the electrode, and the potential is lower due to the potential difference after the fusing. The fused end of the fuse layer connected to the other electrode is attracted to the electrode with the higher potential, and the fuse layer rises and the fused end contacts the higher potential electrode to cause a short circuit. There was a problem that there was.

  Therefore, the end of the blown fuse layer is in contact with the electrode by providing a sufficient gap between the fusing position of the fuse layer and the electrode by increasing the arrangement interval between the first electrode and the second electrode. However, when the arrangement interval between the first electrode and the second electrode is increased, the working efficiency is reduced because more current and time are required for fusing the fuse layer. There is a problem that the improvement of the integration degree is obstructed.

  Therefore, in the fuse of the present invention, in the fuse configured by connecting the first electrode and the second electrode to the fuse layer provided on the semiconductor substrate, a part is provided between the first electrode and the second electrode. A high resistance region having a high resistance value was formed. Furthermore, the high resistance region is also characterized in that it is formed near the electrode on the low potential side of the first electrode and the second electrode.

  In the semiconductor device of the present invention, in the semiconductor device having a fuse formed by connecting the first electrode and the second electrode to the fuse layer provided on the semiconductor substrate, the fuse layer includes the first electrode and A high resistance region having a partially increased resistance value was formed between the second electrode and the second electrode.

  In the fuse manufacturing method of the present invention, a fuse layer is formed on a semiconductor substrate, and a first electrode and a second electrode connected to the fuse layer are formed. A mask is provided in a part of the fuse layer between the formation part and the formation part of the second electrode, and impurities are injected into the fuse layer, thereby forming a high resistance region having a partially increased resistance value in the fuse layer. It was decided to. Further, the present invention is characterized in that the formation position of the high resistance region is adjusted by adjusting the arrangement position of the mask between the formation portion of the first electrode and the formation portion of the second electrode. Of the first electrode formation portion and the second electrode formation portion, a mask is provided near the formation portion of the electrode having a low potential.

  According to the first aspect of the present invention, in the fuse configured by connecting the first electrode and the second electrode to the fuse layer provided on the semiconductor substrate, the fuse is interposed between the first electrode and the second electrode. By forming the high resistance region having a partially increased resistance value, the fusing position of the fuse layer can be adjusted by the formation position of the high resistance region, so the distance between the first electrode and the second electrode can be adjusted. Short circuit can be prevented without spreading.

  According to the second aspect of the present invention, the high resistance region is formed near the electrode on the low potential side of the first electrode and the second electrode, so that the first electrode and the second electrode Even if the interval is narrowed, the occurrence of a short circuit can be reliably prevented.

  According to a third aspect of the present invention, in the semiconductor device having the fuse formed by connecting the first electrode and the second electrode to the fuse layer provided on the semiconductor substrate, the fuse layer includes the first electrode. Since the high resistance region having a partially increased resistance value is formed between the first electrode and the second electrode, the fusing position of the fuse layer can be adjusted by the formation position of the high resistance region. The occurrence of a short circuit can be prevented without increasing the distance between the first electrode and the second electrode. Therefore, since the formation region of the fuse in the semiconductor device can be reduced, the semiconductor device can be reduced in size.

  According to a fourth aspect of the present invention, in the method for manufacturing a fuse, a fuse layer is formed on a semiconductor substrate, and a first electrode and a second electrode connected to the fuse layer are formed. A mask is provided in a part of the fuse layer between the part and the second electrode formation part, and an impurity is implanted into the fuse layer, thereby forming a high resistance region having a partially increased resistance value in the fuse layer. As a result, the fusing position of the fuse layer can be adjusted depending on the position where the high resistance region is formed, so that the occurrence of a short circuit can be prevented without increasing the distance between the first electrode and the second electrode.

  According to the fifth aspect of the present invention, the position where the high resistance region is formed can be very easily adjusted by adjusting the arrangement position of the mask between the first electrode forming portion and the second electrode forming portion. And it can be adjusted reliably.

  According to the sixth aspect of the present invention, the first electrode and the second electrode are formed by providing the mask near the formation portion of the first electrode formation portion and the formation portion of the second electrode that is at a low potential. The occurrence of a short circuit can be reliably prevented even when the distance between the two electrodes is narrowed.

  In the fuse of the present invention, the semiconductor device having the fuse, and the method of manufacturing the fuse, a high resistance region having a partially increased resistance value is formed in a part of the fuse layer provided on the semiconductor substrate. is there.

  By providing a high resistance region in the fuse layer in this manner, when a high current is passed between the first electrode and the second electrode connected to the fuse layer so as to sandwich the high resistance region, Since the high resistance region becomes a high heat generation region and fusing occurs, the fuse layer can be surely blown in the high resistance region.

  Therefore, since the fusing position of the fuse layer can be adjusted by the formation position of the high resistance region, adjusting the formation position of the high resistance region without increasing the interval between the first electrode and the second electrode. Short circuit can be prevented from occurring.

  In particular, the high-resistance region is formed by forming a high-resistance region near the low-potential-side electrode in current conduction for fusing, between the first electrode and the second electrode, so that the low-potential in the fuse layer after fusing. The fusing end of the fuse layer connected to the side electrode can be reliably prevented from reaching the electrode on the high potential side, and even if the distance between the first electrode and the second electrode is narrowed, the occurrence of a short circuit is ensured Can be prevented.

  In addition, by installing a recombination prevention layer next to the fuse layer to prevent recombination of the blown fuse layer, when the fuse layer is blown, recombination of the fuse layer from which the recombination prevention layer has blown By preventing the reaction, the fusing state may be reliably maintained. In this case, a layer containing silicon is used for the fuse layer, and a layer containing carbon is used for the recombination prevention layer, so that when the fuse layer is blown, the reaction between the fuse layer and the recombination prevention layer occurs. Since stable silicon oxide (SiC) can be formed as a material, the blown state of the fuse layer can be reliably maintained by this silicon carbide, and recombination of the blown fuse layer can be reliably prevented. Such a recombination prevention layer can reliably prevent recombination of the fuse layer by being laminated on the upper surface or the lower surface of the fuse layer, or both upper and lower surfaces.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing the manufacturing process of the fuse of this embodiment.

  As shown in FIG. 1A, the fuse is formed on the semiconductor substrate 10, an insulating film 20 is formed on the upper surface of the semiconductor substrate 10, and a polysilicon film 30 is formed on the upper surface of the insulating film 20. Then, necessary conductivity is ion-implanted into the polysilicon film 30 to adjust the electrical conductivity, that is, the resistivity of the polysilicon film 30. The adjustment of the resistivity of the polysilicon film 30 by ion implantation here is referred to as “primary resistivity adjustment”.

  Next, a resist is applied to the upper surface of the polysilicon film 30, and this resist is patterned into a required pattern. As shown in FIG. 1B, the resist is applied only at a required position on the upper surface of the polysilicon film 30. The mask 40 is formed, and necessary impurities are ion-implanted into the polysilicon film 30 again to adjust the electrical conductivity, that is, the resistivity of the polysilicon film 30. The adjustment of the resistivity of the polysilicon film 30 by ion implantation here is referred to as “secondary resistivity adjustment”.

  In this secondary resistivity adjustment, the impurity is not implanted in the region covered with the resist mask 40 of the polysilicon film 30, so that the resistivity can be made higher than the region implanted with the impurity in the secondary resistivity adjustment. it can. A region in which the resistivity is partially adjusted to be high by adjusting the impurity implantation amount is referred to as a high resistance region 31.

  Since it is preferable that the high resistance region 31 is close to the electrode having a low potential among the electrodes having a high potential and the electrode having a low potential for fusing when a fuse is formed, the fuse layer 30 is used as described later. Of the first electrode formation region 51 ′ and the second electrode formation region 52 ′ for forming the first electrode 51 and the second electrode 52 connected to the first electrode 51, the first electrode 51 on the low potential side in this embodiment. A resist mask 40 is formed in the vicinity of the first electrode formation region 51 ′ where is formed.

  After the formation of the high resistance region 31, the resist mask 40 is removed, and the polysilicon film 30 is patterned into a predetermined shape, thereby forming a fuse layer 30 ′ as shown in FIG.

  Next, a coating insulating film 60 made of a silicon nitride film or the like is formed on the upper surface of the semiconductor substrate 10 to cover the fuse layer 30 ′.

  After covering the fuse layer 30 'with the covering insulating film 60, as shown in FIG. 1D, a first electrode opening 71 and a second electrode opening 72 are provided at required positions of the covering insulating film 60, respectively. After that, a metal film such as an aluminum film is formed on the upper surface of the semiconductor substrate 10 by sputtering or the like, this metal film is patterned into a predetermined shape, and the first electrode 51 and the second electrode connected to the fuse layer 30 ′ 52 is formed.

  In this way, by forming the high resistance region 31 in the fuse layer 30 ′, when a high current for fusing is supplied to the fuse layer 30 ′, the highest heat generation in the high resistance region 31 results in the highest resistance. The resistance region 31 can surely cause fusing. Therefore, by adjusting the position where the high resistance region 31 is formed, it is possible to prevent a short circuit with the electrode on the high potential side due to the fusing end portion after fusing.

  In addition, since the formation position of the high resistance region 31 can be adjusted by the formation position of the resist mask 40, the high resistance region 31 can be formed at a predetermined position very easily.

  In particular, the high resistance region 31 is formed close to the first electrode 51 by providing the resist mask 40 close to the first electrode forming region 51 ′, so that the fuse layer 30 ′ is blown as in the present embodiment. In some cases, when the first electrode 51 is an electrode having a lower potential than the second electrode 52, the second electrode 52 and the high resistance having a high potential even if the interval between the first electrode 51 and the second electrode 52 is narrowed. The distance from the region 31 can be made relatively large, and a short circuit between the fused end of the fuse layer 30 ′ and the second electrode 52 can be reliably prevented. Therefore, it is possible to reduce the size of the semiconductor device provided with such a fuse layer 30 ′.

  In the present embodiment, the amount of impurities injected into the polysilicon film 30 in the primary resistivity adjustment is set to be about half of the amount of impurities injected into portions other than the high resistance region 31 of the fuse layer 30 ′. Thereafter, the remaining amount of impurities is implanted into the polysilicon film 30 not covered with the resist mask 40 in the secondary resistivity adjustment. For example, as another embodiment, the high resistivity is adjusted in the primary resistivity adjustment. Impurities are implanted in the polysilicon film 30 in such an amount that a desired fuse resistance value can be obtained in the region 31 so as to reduce the resistivity in regions other than the high resistance region 31 in the secondary resistivity adjustment. It may be.

  As described above, by implanting the polysilicon film 30 with an amount of impurities capable of obtaining a desired fuse resistance value in the high resistance region 31 in the primary resistivity adjustment, a fuse having a desired resistance value is easily formed. be able to.

It is manufacturing process explanatory drawing which showed the manufacturing process of the fuse which concerns on this invention. It is a schematic explanatory drawing of the conventional fuse.

Explanation of symbols

10 Semiconductor substrate
20 Insulating film
30 Polysilicon film
30 'fuse layer
31 High resistance region
40 resist mask
51 First electrode
51 '1st electrode formation area
52 Second electrode
52 'Second electrode formation region
60 Insulation film for coating
71 First electrode opening
72 Second electrode opening

Claims (6)

In a fuse configured by connecting a first electrode and a second electrode to a fuse layer provided on a semiconductor substrate,
A fuse, wherein a high resistance region having a partially increased resistance value is formed between the first electrode and the second electrode.   2. The fuse according to claim 1, wherein the high resistance region is formed closer to an electrode on a low potential side of the first electrode and the second electrode. In a semiconductor device having a fuse configured by connecting a first electrode and a second electrode to a fuse layer provided on a semiconductor substrate,
The semiconductor device according to claim 1, wherein a high resistance region having a partially increased resistance value is formed between the first electrode and the second electrode in the fuse layer. In a fuse manufacturing method for forming a fuse layer on a semiconductor substrate and forming a first electrode and a second electrode connected to the fuse layer,
A mask is provided in a part of the fuse layer between the first electrode formation portion and the second electrode formation portion, and an impurity is implanted into the fuse layer, thereby partially in the fuse layer. A method for manufacturing a fuse, comprising forming a high resistance region having a high resistance value.   The formation position of the high resistance region is adjusted by adjusting the arrangement position of the mask between the formation portion of the first electrode and the formation portion of the second electrode. 4. The method for producing a fuse according to 4.   6. The method of manufacturing a fuse according to claim 5, wherein the mask is provided near an electrode forming portion having a low potential among the forming portion of the first electrode and the forming portion of the second electrode.

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