TWI441225B - Electrical fuse structure - Google Patents

Description

Electric fuse structure

The present invention relates to an electrical fuse structure, and more particularly to an electrical fuse structure that enhances the blowing window of a blown electrical fuse.

As the semiconductor process is miniaturized and the complexity is increased, semiconductor components are also more susceptible to various types of defects or impurities, and failure of a single metal wiring, diode or transistor tends to constitute the entire wafer. defect. Therefore, in order to solve this problem, the current technology forms fusible links, that is, fuses, in the integrated circuit to ensure the availability of the integrated circuit.

In general, a fuse is a redundancy circuit that is connected to an integrated circuit. Once a portion of the circuit is found to be defective, the connection can be used to repair or replace the defective circuit. In addition, the current fuse design can provide programming elements, so that various customers can program the circuit according to different functions. In terms of operation mode, the fuse is roughly classified into two types: a thermal fuse and an electric fuse (eFuse). The so-called thermal fuse is cut by a laser zip process; as for the electric fuse, the fuse is broken by the principle of electro-migration to achieve the repair effect. Or stylized features. Further, the electric fuse in the semiconductor element may be, for example, a poly efuse, a MOS capacitor anti-fuse, a diffusion fuse, a contact plug electric fuse ( Contact efuse), contact anti-fuse, etc.

Typically, the breaking mechanism of the electric fuse is as shown in FIG. 1, the cathode of an electric fuse structure 1 is electrically connected to the drain of the transistor of a blowing device 2, and the structure of the electric fuse structure 1 is A voltage Vfs is applied to the anode, a voltage Vg is applied to the gate of the transistor, a voltage Vd is applied to the drain of the transistor, and the source of the transistor is grounded. The current (I) flows from the anode of the electric fuse structure 1 to the cathode of the electric fuse structure 1, and the electron flow (e ^- ) flows from the cathode of the electric fuse structure 1 to the anode of the electric fuse structure 1. The current used in the fusing has a preferred range. When the current is too low, the resulting resistance is too low, which may result in incomplete electrical migration. When the current is too high, the electrical fuse may be thermally broken. Typically, the fusing current for an electrical fuse structure of the 65 nm process is about 13 milliamperes (mA). The fuse position of the electric fuse may be different according to the structural design. For example, the disconnection of the contact plug fuse is located at the contact plug on the cathode, and the disconnection of the polysilicon fuse is located in the polysilicon layer.

It should be noted that it is conventional to first set a predetermined voltage value when fusing the electric fuse structure, and then to fuse the electric fuse structure over the range of the voltage value. However, taking the above-described polycrystalline silicon electric fuse structure as an example, when the electric fuse is blown, it is generally impossible to obtain a voltage value of the fully fusible electric fuse structure that is above a predetermined voltage value and does not exceed a predetermined voltage value. The poor blowing window required to make the electrical fuse structure. Therefore, how to improve the current electric fuse structure to produce an electric fuse structure having a better breaking voltage range is an important issue today.

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide an electrical fuse structure that provides the disadvantage of a poor open voltage range when fuses are currently blown.

The present invention discloses an electrical fuse structure comprising a fuse body disposed on a surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse body, and an anode electrically connected to the other end of the fuse body. In accordance with a preferred embodiment of the present invention, at least a portion of the fuse body is provided with a compressive stress layer.

Another embodiment of the present invention discloses an electrical fuse structure including a semiconductor substrate having an oxide region and an electrical fuse region thereon; a transistor disposed on the semiconductor substrate of the transistor region; and a fuse body The semiconductor substrate is disposed on the electric fuse region; a cathode and an anode are respectively connected to the two ends of the fuse body; and a compressive stress layer covers the transistor of the transistor region and the fuse body, the cathode and the anode of the electric fuse region on.

The present invention mainly provides a compressive stress layer on the fuse body of the electric fuse structure, and thereby increases the breaking window of the blown electric fuse by compressing the stress of the stress layer. According to a preferred embodiment of the present invention, the fuse body, the cathode and the anode of the electric fuse structure are both formed on the surface of the semiconductor substrate to form a surface type electric fuse structure, and the compressive stress of the compressive stress layer is formed. It is preferably between -5 GPa and 0 GPa, and can completely cover the fuse body and the anode cathode of the electric fuse structure, covering only the fuse body or only covering the anode and the cathode.

Please refer to FIG. 2 and FIG. 3 . FIG. 2 is a top view of an electric fuse structure according to a preferred embodiment of the present invention, and FIG. 3 is a cross-sectional view along line BB′ in FIG. 2 . As shown in the figure, the present invention mainly provides a semiconductor substrate 30, such as a germanium substrate composed of carbon oxyhydroxide (SiCOH), germanium dioxide (SiO ₂ ) or tantalum nitride (Si ₃ N ₄ ). . A fuse body 36 composed of the patterned polysilicon layer 32 and the deuterated metal layer 34 and an anode 38 and a cathode 40 connected to both ends of the fuse body 36 are then formed on the semiconductor substrate 30. The patterned polysilicon layer 32 can be achieved by a photolithography and etching process, and the patterned deuterated metal layer can be completed by using a self-aligned metal germanide process. For example, a metal layer (not shown) may be overlaid on the polysilicon layer 32, followed by a heat treatment to react the metal layer with the exposed polysilicon layer 32 and wet etching to remove the unreacted metal layer to form the deuterated metal layer 34. In this embodiment, the fuse body 36 and the anode 38 and the cathode 40 are composed of both a polysilicon layer and a deuterated metal layer, but are not limited thereto, and the materials of the fuse body 36 and the anode 38 and the cathode 40 may further include Any electrically conductive material, such as polysilicon, metal, or a combination of both, and may be the same or different from each other.

A compressive stress layer 42 is then formed and overlies the fuse body 36 and the anode 38 and cathode 40. In accordance with a preferred embodiment of the present invention, the compressive stress layer 42 is comprised of a dielectric material having compressive stress, including tantalum nitride or tantalum oxide, and the compressive stress layer 42 has a compressive stress value between -5 GPa to 0 GPa. . The stress of the compressive material is achieved by adjusting the process conditions at the time of formation such as temperature, pressure, precursor type, flow rate, etc., or by forming an additional annealing treatment or UV irradiation after forming the compressed material. It should be noted that, in this embodiment, the compressive stress layer 42 is simultaneously covered on the fuse body 36 and the anode 38 and the cathode 40. However, the present invention is not limited to this design, and the present invention can adjust the compressive stress layer 42 according to the process requirements. The covered area, for example, may cover the compressive stress layer 42 only on the anode 38 and the cathode 40, or only over the fuse body 36, which is within the scope of the present invention. Further, a thin dielectric material such as hafnium oxide may be formed as a liner layer before the formation of the compressive stress layer.

Then, a dielectric layer (not shown) may be overlaid on the compressive stress layer 42 and the semiconductor substrate 30, and a lithography and etching process may be performed to remove portions of the dielectric layer and the compressive stress layer 42 for the dielectric layer and A plurality of contact holes 44 are formed in the compressive stress layer 42 and expose the anode 38 and the cathode 40. Next, a metal material made of tungsten, aluminum, copper, tantalum, tantalum nitride, titanium or titanium nitride is filled in the contact hole 44 to form a plurality of conductive plugs 46 connecting the anode 38 and the cathode 40. Thus, an electric fuse structure of a preferred embodiment of the present invention has been completed.

It should also be noted that the conductive plugs 46 connecting the cathodes 40 in this embodiment (as in Fig. 2) each have an approximately circular cross section. However, without being limited to this design, the present invention can further provide conductive plugs having different cross-sectional shapes on the cathode 40 pattern. For example, the present invention can form a conductive plug 47 having an elliptical cross-section in the opposite intermediate portion of the cathode 40, as shown in FIG. Wherein, the elliptical conductive plug 47 has a long axis 48 and a short axis 49, and the long axis 48 is approximately twice the diameter of each circular conductive plug 46, and the short axis 49 is approximately equal to each circular conductive The diameter of the plug 46.

The above embodiment of the present invention only forms an electric fuse structure on a semiconductor substrate, but is not limited to the above design. The invention can also integrate the MOS transistor process while fabricating the electric fuse structure according to the process requirements. The scope covered by the invention. Please refer to FIG. 5 to FIG. 6 . FIG. 5 to FIG. 6 are schematic diagrams showing the process of integrating a MOS transistor and an electric fuse structure according to the present invention. As shown in FIG. 5, a semiconductor substrate 50 is first provided having an oxide region 102 and an electrical fuse region 104 defined thereon. An isolation process is then performed to form a shallow trench isolation (STI) isolation structure 52 in the semiconductor substrate 50 between the transistor region 102 and the electrical fuse region 104, and simultaneously in the electrical fuse region 104. Another shallow trench isolation 54 is simultaneously formed in the semiconductor substrate 50. Then, a dielectric layer (not shown) composed of an oxide is deposited on the surface of the semiconductor substrate 50, and a gate material layer (not shown) composed of polysilicon is formed on the dielectric layer. Then, a lithography and etching process is performed to remove a portion of the gate material layer and the dielectric layer to form a gate electrode 56 and a gate dielectric layer 58 disposed thereon on the semiconductor substrate 50 of the transistor region 102. At the same time, an electric fuse pattern layer 60 having a fuse body, a cathode block and an anode block is formed on the shallow trench isolation 54 of the electric fuse region 104. The gate material layer of the present embodiment is composed of polycrystalline germanium, but is not limited thereto. The gate material layer may be composed of a metal, a metal, and a polycrystalline germanium stacked on top of each other, which are all covered by the present invention.

A sidewall 66 is then formed on the gate electrode 56 of the transistor region 102 and the sidewall of the EMF pattern layer 60, and an ion implantation process is performed to form the semiconductor substrate 50 on both sides of the sidewall 66 of the transistor region 102. A source/drain region 62, 64 is formed. It should be noted that, in this embodiment, a single sidewall 66 and a source/drain region 62, 64 are taken as an example, but a plurality of sidewalls may be formed on the sidewall of the gate electrode 56 according to process requirements, and At the same time, it is made with lightly doped bungee. For example, a bias sidewall may be formed on the sidewall of the gate electrode, and then a lightly doped ion implantation is performed to form a lightly doped drain in the semiconductor substrate on both sides of the bias sidewall. A main sidewall is then formed around the bias sidewalls and a heavily doped ion implantation is performed to form a source/drain region in the semiconductor substrate on either side of the main sidewall. In addition, the order of forming the lateral sidewalls, the main sidewalls, the lightly doped drains, and the source/drain regions can be arbitrarily adjusted according to the process requirements, and is not limited thereto.

Then, as shown in FIG. 6, a self-aligned germanium metal process is performed to form a germanium metal layer 68 on the surface of the electric fuse pattern layer 60 and the source/drain regions 62, 64. The deuterated metal layer 68 may include tungsten telluride, titanium telluride, cobalt telluride, nickel telluride or an alloy of the above with other metals such as platinum, but is not limited thereto. Thus, a MOS transistor is completed in the transistor region 102. Next, a contact hole etch stop layer 88 composed of yttrium oxide or tantalum nitride and having compressive stress is deposited and completely covers the MOS transistor of the transistor region 102 and the electric fuse pattern layer covering the electric fuse region 104 in whole or in part. 60, and then a dielectric layer 70 is deposited over the contact hole etch stop layer 88. As described above, a thin dielectric material backing layer may be formed before or after the formation of the compressive material; the stress of the compressive material is determined by adjusting process conditions such as temperature, pressure, precursor type, flow rate, etc. This is achieved or achieved by additional annealing or UV irradiation after the formation of the compressed material. A lithography and etching process is then performed to remove portions of the dielectric layer 70 and the contact hole etch stop layer 88 to form a plurality of contact holes and expose the top and source/drain regions 62, 64 of the gate electrode 56 of the MOS transistor. And a portion of the deuterated metal layer 68 of the electrical fuse region 104. It should be noted here that there are NMOS and PMOS transistors in the general logic circuit area. In order to respond to the different conductive carriers of the two transistors (the NMOS is an electron and the PMOS is a hole), the compressive stress may not be covered on the NMOS. The contact hole etch stop layer or the extension stress contact hole etch stop layer covers the PMOS over the compressive stress contact hole etch stop layer. Therefore, the method of the present invention may further comprise: covering the etch stop layer of the tensile stress contact hole before or after depositing the etch stop layer of the compressive stress contact hole, and removing the tensile stress contact hole on the PMOS and the electric fuse region 104. Floor.

Then, a metal material composed of tungsten, aluminum, copper, tantalum, tantalum nitride, titanium or titanium nitride is filled in the contact hole to form a plurality of through layers in the transistor region 102 and the electric fuse region 104, respectively. The electrical layer 70 and the contact hole etch stop layer 88 are electrically connected to the conductive plugs 72, 74, 76, 78, 80 of the MOS transistor and the electric fuse pattern layer 60. A metal interconnect process can then be performed, such as forming a metal interconnect 82 connecting the conductive plug 74 on the cathode to the conductive plug 76 on the source/drain region 62 and a metal interconnect 84 to the anode. The conductive plug 72 is connected to the surrounding logic circuit. Thus, the integrated MOS transistor and the electric fuse structure of another embodiment of the present invention are completed.

In summary, the present invention mainly provides a compressive stress layer on the fuse body of the electric fuse structure, and thereby increases the breaking voltage range when the electric fuse is blown by compressing the stress of the stress layer. . According to a preferred embodiment of the present invention, the fuse body, the cathode and the anode of the electric fuse structure are both formed on the surface of the semiconductor substrate to form a surface type electric fuse structure, and the compressive stress of the compressive stress layer is formed. It is preferably between -5 GPa and 0 GPa, and can completely cover the fuse body and the anode cathode of the electric fuse structure, covering only the fuse body or only covering the anode and the cathode.

According to another embodiment of the present invention, the compressive stress layer overlying the surface of the electrical fuse structure may in turn employ a contact hole etch stop layer in the MOS transistor process. In other words, the present invention can divide a transistor region and an electrical fuse region on the semiconductor substrate, and then cover the contact hole with a compressive stress to form an etch stop layer in the MOS transistor after the fabrication of the MOS transistor is completed. On the layer of electric fuse pattern. Finally, a dielectric layer is covered and a plurality of conductive plugs connecting the MOS transistor and the electric fuse are formed in the dielectric layer to complete an integrated structure of the MOS transistor and the electric fuse.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

1. . . Electric fuse structure

2. . . Fuse device

10. . . Polycrystalline germanium electric fuse structure

12. . . anode

14. . . cathode

16. . . Fuse body

18, 20. . . Tungsten plug

twenty two. . . Polycrystalline layer

twenty four. . . Deuterated metal layer

30. . . Semiconductor substrate

32. . . Polycrystalline layer

34. . . Deuterated metal layer

36. . . Fuse body

38. . . anode

40. . . cathode

42. . . Compressive stress layer

44. . . Contact hole

46. . . Conductive plug

47. . . Conductive plug

48. . . Long axis

49. . . Short axis

50. . . Semiconductor substrate

52, 54. . . Shallow trench isolation structure

56. . . Gate electrode

58. . . Gate dielectric layer

60. . . Electric fuse pattern layer

62, 64. . . Source/drain region

66. . . Side wall

68. . . Deuterated metal layer

70. . . Dielectric layer

72, 74, 76, 78, 80. . . Contact plug

82, 84. . . Metal interconnect

88. . . Contact hole etch stop layer

102. . . Transistor region

104. . . Electric fuse area

Figure 1 is a schematic diagram of the breaking mechanism of a conventional electric fuse device.

Figure 2 is a top plan view of an electrical fuse structure in accordance with a preferred embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view taken along line BB' in Fig. 2.

Figure 4 is a top plan view of an electrical fuse structure in accordance with another embodiment of the present invention.

5 to 6 are schematic views showing the process of integrating a MOS transistor and an electric fuse structure according to the present invention.

36. . . Fuse body

38. . . anode

40. . . cathode

42. . . Compressive stress layer

46. . . Conductive plug

Claims (18)

An electric fuse structure includes: a fuse body disposed on a surface of a semiconductor substrate, and at least a portion of the fuse body is covered with a compressive stress layer; a cathode is electrically connected to the fuse body One end; and an anode electrically connected to the other end of the fuse body, wherein the compressive stress layer covers the cathode or the anode. The electrical fuse structure of claim 1, wherein the compressive stress layer is a tantalum nitride layer. The electric fuse structure of claim 1, wherein the fuse body comprises a polysilicon layer and a deuterated metal layer. The electric fuse structure according to claim 1, wherein the compressive stress layer has a stress value of from -5 GPa to 0 Pa. The electrical fuse structure of claim 1, further comprising a plurality of conductive plugs electrically connecting the cathode and the anode via the compressive stress layer. The electrical fuse structure of claim 5, wherein the conductive plugs connecting the cathodes comprise a plurality of circular conductive plugs and at least one elliptical conductive plug. The electric fuse structure of claim 6, wherein the elliptical conductive plug has a major axis and a minor axis, and the major axis is greater than twice the diameter of each of the circular conductive plugs. The electrical fuse structure of claim 1, further comprising a thin dielectric liner layer disposed between the fuse body and the compressive stress layer. An electric fuse structure comprising: a semiconductor substrate having an oxide region and an electrical fuse region; an transistor disposed on the semiconductor substrate of the transistor region; a fuse body disposed on the semiconductor device a semiconductor substrate on the electric fuse region; a cathode and an anode are respectively connected to both ends of the fuse body; and a compressive stress layer covers the transistor of the transistor region and the fuse body of the electric fuse region The cathode and the anode. The electrical fuse structure of claim 9, wherein the transistor comprises a gate region of the transistor region disposed on the semiconductor substrate. The electrical fuse structure of claim 10, wherein the transistor comprises a source/drain region disposed in the semiconductor substrate on both sides of the gate structure. The electric fuse structure of claim 9, wherein the compressive stress layer is a tantalum nitride layer. The electric fuse structure of claim 9, wherein the fuse body comprises a polysilicon layer and a deuterated metal layer. The electric fuse structure according to claim 9, wherein the stress of the compressive stress layer is between -5 GPa and 0 GPa. The electrical fuse structure of claim 9, further comprising a plurality of conductive plugs electrically connecting the cathode and the anode via the compressive stress layer. The electrical fuse structure of claim 15, wherein the conductive plugs connecting the cathodes comprise a plurality of circular conductive plugs and at least one elliptical conductive plug. The electric fuse structure of claim 16, wherein the elliptical conductive plug has a major axis and a minor axis, and the major axis is greater than twice the diameter of each of the circular conductive plugs. The electrical fuse structure of claim 9, further comprising a thin dielectric liner layer disposed between the fuse body and the compressive stress layer.