TWI767850B - Anti-fuse device and manufacturing method thereof - Google Patents

Abstract

An anti-fuse device including a substrate, a doped region, a dielectric layer, a first contact, an anti-fuse material layer, and a second contact is provided. The doped region is located in the substrate. The dielectric layer is located on the substrate and has a first opening and a second opening. The first opening and the second opening respectively expose the doped region. The first contact is located in the first opening. The anti-fuse material layer is located between the first contact and the doped region. The second contact is located in the second opening and is electrically connected to the doped region.

Description

Antifuse element and method of making the same

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly, to an anti-fuse device and a method for fabricating the same.

An antifuse element has been developed that has a layer of antifuse material. In the initial state, the anti-fuse material layer has a high resistance value, and the anti-fuse element is in an open state. When the anti-fuse element is operated, the anti-fuse material layer breaks down to form a conductive path, and the anti-fuse element is in a short-circuit state. The current common anti-fuse element operates through the gate. However, since the contact area between the gate electrode and the antifuse material layer is large, the uncertainty of the position where the collapse of the antifuse material layer occurs is high. As a result, after the anti-fuse material layer collapses, the uncertainty of the resistance value of the anti-fuse element is high, so that misjudgment of data is likely to occur.

The present invention provides an anti-fuse element and a manufacturing method thereof, which can prevent misjudgment of data.

The present invention provides an anti-fuse element, which includes a substrate, a doped region, a dielectric layer, a first contact window, an anti-fuse material layer and a second contact window. The doped regions are located in the substrate. The dielectric layer is located on the substrate and has a first opening and a second opening. The first opening and the second opening respectively expose the doped regions. The first contact window level is in the first opening. The antifuse material layer is located between the first contact window and the doped region. The second contact window level is in the second opening and is electrically connected to the doped region.

The present invention provides a method for manufacturing an anti-fuse element, which includes the following steps. Provide a base. A doped region is formed in the substrate. A dielectric layer is formed on the substrate. A first opening is formed in the dielectric layer. The first opening exposes the doped region. A layer of antifuse material is formed in the first opening. A first contact window is formed in the first opening. The first contact window level is on the layer of antifuse material. A second opening is formed in the dielectric layer. The second opening exposes the doped region. A second contact window is formed in the second opening. The second contact window is electrically connected to the doped region.

Based on the above, in the anti-fuse element and the manufacturing method thereof proposed by the present invention, since the first contact window is formed in the first opening, the size of the first opening can be controlled to reduce the size of the first contact window and the anti-fuse. The contact area of the fuse material layer. Therefore, when the anti-fuse element is operated, the collapsed portion of the anti-fuse material layer can be converged and concentrated in a small range, thereby reducing the uncertainty of the resistance value of the anti-fuse element, so as to prevent data misjudgment. In addition, since the anti-fuse element operates by applying a voltage to the first contact window and the second contact window, the anti-fuse element may not have a gate, whereby the anti-fuse element may have a smaller element area, Thus, the component density can be increased.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

1A to 1I are top views of a manufacturing process of an antifuse element according to an embodiment of the present invention. 2A to 2I are cross-sectional views along the line I-I' in FIGS. 1A to 1I . Referring to FIG. 1A and FIG. 2A , a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Additionally, well regions 102 may be formed in the substrate 100 . The formation method of the well region 102 is, for example, an ion implantation method. Additionally, isolation structures 104 may be formed in the substrate 100 . The isolation structure 104 is, for example, a shallow trench isolation structure. The material of the isolation structure 104 is, for example, oxide (eg, silicon oxide). Next, doped regions 106 are formed in the substrate 100 . Isolation structures 104 may surround doped regions 106 (FIG. 1A). In some embodiments, doped region 106 may be formed in well region 102 . The formation method of the doped region 106 is, for example, an ion implantation method. The doped region 106 and the well region 102 may have different conductivity types. For example, the doped region 106 and the well region 102 may be of one and the other of an N-type conductivity type and a P-type conductivity type, respectively.

Referring to FIG. 1B and FIG. 2B , a dielectric layer 108 is formed on the substrate 100 . The material of the dielectric layer 108 is, for example, oxide (eg, silicon oxide). The formation method of the dielectric layer 108 is, for example, a chemical vapor deposition method. In some embodiments, a chemical mechanical polishing process may be performed on the dielectric layer 108 to planarize the surface of the dielectric layer 108 .

Referring to FIGS. 1C and 2C , a patterned hard mask layer 110 may be formed on the dielectric layer 108 . The patterned hard mask layer 110 may expose portions of the dielectric layer 108 . The material of the patterned hard mask layer 110 is, for example, nitride (eg, silicon nitride). The patterned hard mask layer 110 can be formed by a deposition process, a lithography process and an etching process.

Next, a portion of the dielectric layer 108 exposed by the patterned hard mask layer 110 may be removed by using the patterned hard mask layer 110 as a mask. Thereby, the opening OP1 can be formed in the dielectric layer 108 . The opening OP1 exposes the doped region 106 . In this embodiment, an over etching process may be performed to remove part of the doped region 106 , so that the cross-sectional shape of the bottom of the opening OP1 becomes an arc shape ( FIG. 2C ). In other embodiments, the over-etching process may not be performed, and the cross-sectional shape of the bottom of the opening OP1 may be flat. The removal method of the portion of the dielectric layer 108 exposed by the patterned hard mask layer 110 is, for example, dry etching.

Referring to FIG. 1D and FIG. 2D, an anti-fuse material layer 112 is formed in the opening OP1. Antifuse material layer 112 may be formed directly on doped region 106 . The material of the antifuse material layer 112 is, for example, oxide (eg, silicon oxide). The formation method of the antifuse material layer 112 is, for example, a thermal oxidation method or a plasma oxidation method.

Referring to FIGS. 1E and 2E , a patterned hard mask layer 114 may be formed on the patterned hard mask layer 110 . The patterned hard mask layer 114 may fill the opening OP1. The material of the patterned hard mask layer 114 is, for example, nitride (eg, silicon nitride). The patterned hard mask layer 114 can be formed by a deposition process, a lithography process, and an etching process. In some embodiments, portions of the patterned hard mask layer 110 exposed by the patterned hard mask layer 114 may be removed to expose portions of the dielectric layer 108 . Next, the part of the dielectric layer exposed by the patterned hard mask layer 114 and the patterned hard mask layer 110 can be removed by using the patterned hard mask layer 114 and the patterned hard mask layer 110 as masks. 108. Thereby, the opening OP2 can be formed in the dielectric layer 108 . The opening OP2 exposes the doped region 106 . In this embodiment, an over-etching process may be performed to remove part of the doped region 106, so that the cross-sectional shape of the bottom of the opening OP2 becomes an arc shape (FIG. 2E). In other embodiments, the over-etching process may not be performed, and the bottom of the opening OP2 may be flat. The removal method of the portion of the dielectric layer 108 exposed by the patterned hard mask layer 114 and the patterned hard mask layer 110 is, for example, dry etching.

Referring to FIGS. 1F and 2F, a metal silicide layer 116 may be directly formed on the doped region 106 exposed by the opening OP2. The material of the metal silicide layer 116 is, for example, cobalt silicide (CoSi) or nickel silicide (NiSi). The formation method of the metal silicide layer 116 is, for example, a self-aligned metal silicide process.

Referring to FIGS. 1G and 2G , the patterned hard mask layer 114 and the patterned hard mask layer 110 can be removed. The removal method of the patterned hard mask layer 114 and the patterned hard mask layer 110 is, for example, a wet etching method.

Referring to FIG. 1H and FIG. 2H , a contact window 118 is formed in the opening OP1 . Contacts 118 are located on layer 112 of antifuse material. The contact window 118 may directly contact the antifuse material layer 112 . In this embodiment, since the cross-sectional shape of the bottom of the opening OP1 is an arc shape, the cross-sectional shape of the interface between the contact window 118 and the anti-fuse material layer 112 can be an arc shape. In other embodiments, when the cross-sectional shape of the bottom of the opening OP1 is flat, the cross-sectional shape of the interface between the contact window 118 and the anti-fuse material layer 112 may be flat. The contact window 118 may be a single-layer structure or a multi-layer structure. In this embodiment, the contact window 118 is a multi-layer structure including the conductor layer 120 and the barrier layer 122 as an example. The conductor layer 120 is located in the opening OP1. The material of the conductor layer 120 is, for example, tungsten or aluminum. The barrier layer 122 is located between the conductor layer 120 and the antifuse material layer 112 and between the conductor layer 120 and the dielectric layer 108 . The material of the barrier layer 122 is, for example, titanium, titanium nitride, or a combination thereof.

In addition, a contact window 124 is formed in the opening OP2. Contacts 124 may be formed on metal silicide layer 116 . The contact window 124 may directly contact the metal silicide layer 116 . The contact window 124 is electrically connected to the doped region 106 . In this embodiment, the contact window 124 can be electrically connected to the doped region 106 through the metal silicide layer 116 . The contact window 118 may be a single-layer structure or a multi-layer structure. In this embodiment, the contact window 124 is a multi-layer structure including the conductor layer 126 and the barrier layer 128 as an example. The conductor layer 126 is located in the opening OP2. The material of the conductor layer 126 is, for example, tungsten. The barrier layer 128 is located between the conductor layer 126 and the metal silicide layer 116 and between the conductor layer 126 and the dielectric layer 108 . The material of the barrier layer 128 is, for example, titanium, titanium nitride, or a combination thereof.

In this embodiment, the contact windows 118 and the contact windows 124 can be formed simultaneously by the same process. In some embodiments, the contact window 118 and the contact window 124 are formed by, for example, firstly forming a contact window material layer (not shown) filled in the opening OP1 and the opening OP2, and then removing the contact window material layer (not shown) by chemical mechanical polishing. A contact window material layer on the outside of the opening OP1 and the opening OP2.

Referring to FIG. 1I and FIG. 2I , wires 130 and wires 132 may be formed on the dielectric layer 108 . The wire 130 and the wire 132 are electrically connected to the contact window 118 and the contact window 124, respectively. The wire 130 and the wire 132 may be a single-layer structure or a multi-layer structure. In this embodiment, the wires 130 and the wires 132 are multi-layered structures as an example. For example, the wire 130 may include a conductor layer 134 and a barrier layer 136 , and the wire 132 may include a conductor layer 138 and a barrier layer 140 . The conductor layer 134 is located on the dielectric layer 108 and the contact window 118 . The barrier layer 136 is located between the conductor layer 134 and the dielectric layer 108 and between the conductor layer 134 and the contact window 118 . The conductor layer 138 is located on the dielectric layer 108 and the contact window 124 . The barrier layer 140 is located between the conductor layer 138 and the dielectric layer 108 and between the conductor layer 138 and the contact window 124 . The material of the conductor layer 134 and the conductor layer 138 is, for example, tungsten or aluminum. The material of the barrier layer 136 and the barrier layer 140 is, for example, titanium, titanium nitride or a combination thereof. The wires 130 and 132 can be formed by a deposition process, a lithography process and an etching process.

Hereinafter, the antifuse element 10a of this embodiment will be described with reference to FIG. 1I and FIG. 2I. In addition, although the method for forming the antifuse element 10a is described by taking the above method as an example, the present invention is not limited thereto.

Referring to FIGS. 1I and 2I , the anti-fuse element 10 a includes a substrate 100 , a doped region 106 , a dielectric layer 108 , a contact window 118 , an anti-fuse material layer 112 and a contact window 124 . In this embodiment, the anti-fuse element 10a can be applied to a one time programmable (OTP) memory. The doped regions 106 are in the substrate 100 . The dielectric layer 108 is located on the substrate 100 and has an opening OP1 and an opening OP2. The openings OP1 and OP2 respectively expose the doped regions 106 . The contact window 118 is located in the opening OP1. A layer 112 of antifuse material is located between the contact window 118 and the doped region 106 . The antifuse material layer 112 may be directly on the doped region 106 . The contact window 124 is located in the opening OP2 and is electrically connected to the doped region 106 . The vertical projection of the contact window 118 and the vertical projection of the contact window 124 may be aligned on the doped region 106 . In addition, the antifuse element 10a may further include at least one of the well region 102 , the isolation structure 104 , the metal silicide layer 116 , the wires 130 and the wires 132 . The well region 102 is located in the substrate 100 . Doped region 106 may be located in well region 102 . The doped region 106 and the well region 102 may have different conductivity types. Isolation structures 104 are located in the substrate 100 and surround the doped regions 106 (FIG. 1A). The metal silicide layer 116 is located between the contact 124 and the doped region 106 . The metal silicide layer 116 may be directly on the doped region 106 . The wire 130 and the wire 132 are electrically connected to the contact window 118 and the contact window 124, respectively.

Based on the above embodiments, in the anti-fuse element 10a and the manufacturing method thereof, since the contact window 118 is formed in the opening OP1, the contact window 118 and the anti-fuse material layer 112 can be reduced by controlling the size of the opening OP1 contact area. Therefore, when the anti-fuse element 10a is operated, the collapsed portion of the anti-fuse material layer 112 can be converged and concentrated in a small range, thereby reducing the uncertainty of the resistance value of the anti-fuse element 10a, To prevent misjudgment of data. In addition, since the anti-fuse element 10a operates by applying a voltage to the contact window 118 and the contact window 124, the anti-fuse element 10a may not have a gate, whereby the anti-fuse element 10a may have a smaller device area , thereby increasing the component density. In some embodiments, when the cross-sectional shape of the interface between the contact window 118 and the antifuse material layer 112 is arc-shaped, the electric field can be more concentrated, thereby making the collapsed part of the antifuse material layer 112 more convergent and concentrated.

3 is a cross-sectional view of an antifuse element according to another embodiment of the present invention. 2I and FIG. 3, the difference between the anti-fuse element 10b of FIG. 3 and the anti-fuse element 10a of FIG. 2I is described as follows. In the embodiment of FIGS. 2A to 2I , the opening OP1 and the anti-fuse material layer 112 are formed first, and then the opening OP2 and the metal silicide layer 116 are formed. In the embodiment of FIG. 3 , the opening OP1 and the metal silicide layer 116 are formed first, and then the opening OP2 and the anti-fuse material layer 112 are formed. In addition, the same components in the antifuse element 10b of FIG. 3 and the antifuse element 10a of FIG. 2I are denoted by the same symbols, and the description thereof will be omitted.

4A to 4E are top views of a manufacturing process of an antifuse element according to another embodiment of the present invention. 4A to 4E are cross-sectional views of the manufacturing process following the steps of FIG. 1D . 5A to 5E are cross-sectional views along the line II-II' in FIGS. 4A to 4E . 5A to 5E are cross-sectional views of the manufacturing process following the steps of FIG. 2D .

Referring to FIGS. 1D , 2D, 4A and 5A, after forming the antifuse material layer 112 ( FIGS. 1D and 2D ), the patterned hard mask layer 110 ( FIGS. 1D and 2D ) may be removed. The removal method of the patterned hard mask layer 110 is, for example, a wet etching method. Next, the contact window 202 is formed in the opening OP1. Contact window 202 is located on layer 112 of antifuse material. The contact window 202 may directly contact the antifuse material layer 112 . In this embodiment, the contact window 202 may include a conductor layer 204 and a barrier layer 206 . In addition, for the details of the contact window 202 , reference may be made to the description of the contact window 118 ( FIG. 2H ) in the above-mentioned embodiment, which will not be described herein again.

Referring to FIGS. 4B and 5B , a patterned hard mask layer 208 may be formed on the dielectric layer 108 . The patterned hard mask layer 208 may expose portions of the dielectric layer 108 . The material of the patterned hard mask layer 208 is, for example, nitride (eg, silicon nitride). The patterned hard mask layer 208 can be formed by a deposition process, a lithography process, and an etching process.

Next, a portion of the dielectric layer 108 exposed by the patterned hard mask layer 208 may be removed by using the patterned hard mask layer 208 as a mask. Thereby, the opening OP2 can be formed in the dielectric layer 108 . The opening OP2 exposes the doped region 106 . The removal method of the portion of the dielectric layer 108 exposed by the patterned hard mask layer 208 is, for example, dry etching.

Referring to FIG. 4C and FIG. 5C , a metal silicide layer 210 may be directly formed on the doped region 106 exposed by the opening OP2 . The material of the metal silicide layer 210 is, for example, cobalt silicide or nickel silicide. The formation method of the metal silicide layer 210 is, for example, a self-aligned metal silicide process.

Referring to FIGS. 4D and 5D , the patterned hard mask layer 208 can be removed. The removal method of the patterned hard mask layer 208 is, for example, a wet etching method.

Next, a contact window 212 is formed in the opening OP2. In this embodiment, the contact window 202 and the contact window 212 are formed by different processes respectively. Contacts 212 may be formed on the metal silicide layer 210 . The contact window 212 can directly contact the metal silicide layer 210 . The contact window 212 is electrically connected to the doped region 106 . In this embodiment, the contact window 212 can be electrically connected to the doped region 106 through the metal silicide layer 210 . In this embodiment, the contact window 212 may include a conductor layer 214 and a barrier layer 216'. In addition, for the details of the contact window 212, reference may be made to the description of the contact window 124 (FIG. 2H) in the above-mentioned embodiment, which will not be described herein again.

Referring to FIGS. 4E and 5E , wires 218 and wires 220 may be formed on the dielectric layer 108 . The wire 218 and the wire 220 are electrically connected to the contact window 202 and the contact window 212, respectively. In this embodiment, the wire 218 may include a conductor layer 222 and a barrier layer 224 , and the wire 220 may include a conductor layer 226 and a barrier layer 228 . In addition, for the details of the wires 218 and 220, reference may be made to the descriptions of the wires 130 and 132 (FIG. 2I) in the above-mentioned embodiment, which will not be described herein again.

6 is a cross-sectional view of an antifuse element according to another embodiment of the present invention. Referring to FIGS. 5E and 6 , the difference between the anti-fuse element 30 a of FIG. 6 and the anti-fuse element 20 a of FIG. 5E is described as follows. In FIG. 6 , the anti-fuse element 30 a may further include a contact window 300 . The contact window 300 is located between the antifuse material layer 112 and the doped region 106 . The antifuse material layer 112 may be located directly on the contact window 300 . In addition, the manufacturing method of the anti-fuse element 30a may further include the following steps. The contact window 300 may be formed in the opening OP1 before forming the antifuse material layer 112 . The material of the contact window 300 is, for example, a silicon-containing material such as doped polysilicon. In the case where the material of the contact window 300 is a silicon-containing material such as doped polysilicon, since the resistance of the silicon-containing material is higher than that of metal, the operating current of the anti-fuse element 30a is small. Therefore, under the same bias voltage, the power loss of the antifuse element 30a is reduced. A method for forming the contact window 300 is, for example, forming a contact window material layer (not shown) in the opening OP1, and then performing an etch-back process on the contact window material layer. The antifuse material layer 112 may be formed directly on the contact window 300 . In this embodiment, the cross-sectional shape of the interface between the contact window 202 and the anti-fuse material layer 112 may be flat. In addition, the height of the contact window 300 may be greater or less than the height of the contact window 202 according to process requirements. In this embodiment, the height of the contact window 300 may be smaller than the height of the contact window 202 . In addition, the same components in the antifuse element 30a of FIG. 6 and the antifuse element 20a of FIG. 5E are denoted by the same symbols, and the description thereof is omitted.

7 is a cross-sectional view of an antifuse element according to another embodiment of the present invention. Please refer to FIG. 6 and FIG. 7 , the difference between the anti-fuse element 30 b of FIG. 7 and the anti-fuse element 30 a of FIG. 6 is described as follows. In the embodiment of FIG. 6 , the opening OP1 and the anti-fuse material layer 112 are formed first, and then the opening OP2 and the metal silicide layer 210 are formed. In the embodiment of FIG. 7 , the opening OP1 and the metal silicide layer 210 are formed first, and then the opening OP2 and the anti-fuse material layer 112 are formed. In the antifuse element 30b, the metal silicide layer 210 is located between the contact window 202 and the contact window 300. As shown in FIG. The metal silicide layer 210 may be directly on the contact window 300 . In addition, in the process of the anti-fuse element 30b, the metal silicide layer 210 is directly formed on the contact window 300. As shown in FIG. Contacts 202 may be formed on metal silicide layer 210 . In addition, the same components in the antifuse element 30b of FIG. 7 and the antifuse element 30a of FIG. 6 are denoted by the same symbols, and the description thereof is omitted.

To sum up, in the anti-fuse element and the manufacturing method thereof of the above-mentioned embodiments, the contact area between the contact window and the anti-fuse material layer can be reduced by controlling the size of the opening, so that the resistance of the anti-fuse element can be reduced. value uncertainty to prevent misjudgment of data. In addition, the anti-fuse element can have a smaller element area, thereby increasing element density.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10a, 10b, 20a, 30a, 30b: Antifuse elements 100: base 102: Well District 104: Isolation Structure 106: Doping region 108: Dielectric layer 110, 114, 208: Patterned hard mask layer 112: anti-fuse material layer 116,210: Metal silicide layer 118, 124, 202, 212, 300: Contact windows 120, 126, 134, 138, 204, 214, 222, 226: Conductor layer 122, 128, 136, 140, 206, 216, 224, 228: Barrier 130, 132, 218, 220: Wire OP1, OP2: Opening

1A to 1I are top views of a manufacturing process of an antifuse element according to an embodiment of the present invention. 2A to 2I are cross-sectional views along the line I-I' in FIGS. 1A to 1I . 3 is a cross-sectional view of an antifuse element according to another embodiment of the present invention. 4A to 4E are top views of a manufacturing process of an antifuse element according to another embodiment of the present invention. 5A to 5E are cross-sectional views along the line II-II' in FIGS. 4A to 4E . 6 and 7 are cross-sectional views of antifuse elements according to other embodiments of the present invention.

10a: Antifuse element

100: base

102: Well District

104: Isolation Structure

106: Doping region

108: Dielectric layer

112: anti-fuse material layer

116: metal silicide layer

118,124: Contact window

120, 126, 134, 138: Conductor layer

122, 128, 136, 140: Barrier Layers

130, 132: Wire

OP1, OP2: Opening

Claims (15)

An anti-fuse element comprising: base; a doped region in the substrate; a dielectric layer located on the substrate and having a first opening and a second opening, wherein the first opening and the second opening respectively expose the doped region; a first contact window located in the first opening; a layer of antifuse material between the first contact and the doped region; and A second contact window is located in the second opening and is electrically connected to the doped region. The antifuse element of claim 1, wherein the first contact window directly contacts the layer of antifuse material. The antifuse element according to claim 1, wherein a cross-sectional shape of the interface between the first contact window and the antifuse material layer includes an arc shape. The antifuse element of claim 1, wherein the material of the antifuse material layer includes an oxide. The anti-fuse element according to claim 1, further comprising: A metal silicide layer is located between the second contact window and the doped region, wherein the metal silicide layer is directly located on the doped region. The anti-fuse element according to claim 1, further comprising: A third contact window is located between the anti-fuse material layer and the doped region, wherein the material of the third contact window includes a silicon-containing material. The antifuse element of claim 1, wherein a vertical projection of the first contact window and a vertical projection of the second contact window are both positioned on the doped region. The anti-fuse element according to claim 1, further comprising: a third contact window, located between the second contact window and the doped region; and A metal silicide layer is located between the second contact window and the third contact window, wherein the metal silicide layer is directly located on the third contact window. The anti-fuse element according to claim 1, further comprising: an isolation structure in the substrate and surrounding the doped region; and A well region is located in the substrate, wherein the doped region is located in the well region, and the doped region and the well region have different conductivity types. A method of manufacturing an anti-fuse element, comprising: provide a base; forming a doped region in the substrate; forming a dielectric layer on the substrate; forming a first opening in the dielectric layer, wherein the first opening exposes the doped region; forming a layer of antifuse material in the first opening; forming a first contact window in the first opening, wherein the first contact window is located on the antifuse material layer; forming a second opening in the dielectric layer, wherein the second opening exposes the doped region; and A second contact window is formed in the second opening, wherein the second contact window is electrically connected to the doped region. The method for manufacturing an antifuse element according to claim 10, wherein the first opening and the antifuse material layer are formed first, and then the second opening is formed. The method for manufacturing an antifuse element according to claim 10, wherein the second opening is formed first, and then the first opening and the antifuse material layer are formed. The method for manufacturing an antifuse element according to claim 10, wherein the method for forming the antifuse material layer includes a thermal oxidation method or a plasma oxidation method. The method for manufacturing an antifuse element according to claim 10, wherein the first contact window and the second contact window are simultaneously formed by the same process. The method for manufacturing an antifuse element according to claim 10, wherein the first contact window and the second contact window are formed by different processes.

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