CN104064548A - Electrical programmable fuse device structure and manufacturing method thereof - Google Patents
Electrical programmable fuse device structure and manufacturing method thereof Download PDFInfo
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- CN104064548A CN104064548A CN201310089210.8A CN201310089210A CN104064548A CN 104064548 A CN104064548 A CN 104064548A CN 201310089210 A CN201310089210 A CN 201310089210A CN 104064548 A CN104064548 A CN 104064548A
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Abstract
The invention discloses an electrical programmable fuse device structure comprising a semiconductor substrate; an insulating oxide layer which is formed on the semiconductor substrate; a cathode, an anode and a fuse connecting the cathode and the anode of the electrical programmable fuse structure which are formed on the insulating oxide layer; and a virtual poly-silicon layer which is arranged on the two sides of the fuse. According to the manufacturing process, the electrical programmable fuse device structure provided with the fuse with uniform and small characteristic dimension is formed so that the requirement of more advanced technology nodes can be met by the electrical programmable fuse device structure.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of electrically programmable fuse (EFuse) device architecture and preparation method thereof.
Background technology
Along with the microminiaturization of semiconductor technology and the raising of complexity, semiconductor element also becomes and is more easily subject to the impact of various defects or impurity, and the inefficacy of plain conductor, diode or transistor etc. often forms the defect of whole chip, in order to address this problem, prior art just can form some fuses in integrated circuit, to guarantee the utilizability of integrated circuit.Electrically programmable fuse is the device that semiconductor integrated circuit is conventional, and electrically programmable fuse is the silicide polysilicon fuse of electrically programmable.Electrically programmable fuse can be with complementary metal oxide semiconductors (CMOS) (CMOS) technique of logic be completely compatible, simple to operate, volume is little and higher flexibility can be provided.Therefore, electrically programmable fuse is widely used in a lot of main integrated circuits, as One Time Programmable (one ?time ?programmable, OTP) memory.In order to meet the semiconductor fabrication process of development, electrically programmable fuse need to also can be programmed under the condition of lower voltage and current intensity, and its resistance value remains unchanged after electrically programmable fuse fusing.
A kind of common electrically programmable fuse device as shown in Figure 1.The SEM schematic diagram of the electrically programmable fuse device architecture that Fig. 1 (a) is prepared according to prior art, as can be seen from Figure 1, electrically programmable fuse device is comprised of anode, fuse and negative electrode.Single electrically programmable fuse and the programmable transistorized schematic diagram of Fig. 1 (b) for preparing according to prior art.
In the prior art for the technique of 90nm technology node, the Fuse link(fuse in conventional electrically programmable fuse device) length-width ratio (L/W) of size is less.Yet along with integrated circuit technique improves, device size constantly dwindles.For the technique of more advanced technology node, in desired electrically programmable fuse device, the length-width ratio of fuse dimension is more much larger than the length-width ratio of fuse dimension in prior art.Therefore, electrically programmable fuse device of the prior art can not meet the requirement of integrated circuit, and can produce a lot of defects, as resistance value distribution scope increase after electrically programmable fuse fusing etc., the high heat that the electric current that fuse passes into produces can cause that the device of chip surrounding is overheated, then reduces device stability.
Therefore, be badly in need of at present a kind of new electrically programmable fuse device architecture and preparation method thereof to meet the requirement of more advanced technology node.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of electrically programmable fuse device architecture, comprising: Semiconductor substrate; The insulating oxide forming in described Semiconductor substrate; The described negative electrode of negative electrode, anode and connection of the electrically programmable fuse structure forming on described insulating oxide and the fuse of described anode, and the virtual polysilicon layer that is positioned at described fuse both sides.
Preferably, described insulating oxide is shallow trench isolating oxide layer.
Preferably, the size of described negative electrode is greater than the size of described anode.
Preferably, described virtual polysilicon layer is connected with described negative electrode and is positioned at the both sides of described anode.
Preferably, described virtual polysilicon layer is not connected with described negative electrode and is positioned at the both sides of described anode.
Preferably, the disrupted configuration of described virtual polysilicon layer for being connected with described anode with described negative electrode respectively.
Preferably, described virtual polysilicon layer is the virtual polysilicon layer that is cut off formation.
Preferably, adopt P2-mask to cut off described virtual polysilicon layer.
According to a further aspect in the invention, the invention allows for a kind of manufacture method of manufacturing electrically programmable fuse device architecture, comprising: Semiconductor substrate is provided; In described Semiconductor substrate, form insulating oxide; On described insulating oxide, form polysilicon layer; Described in etching, polysilicon layer to be to form the described negative electrode of negative electrode, anode and connection of electrically programmable fuse device architecture and the fuse of described anode, and the virtual polysilicon layer that is positioned at described fuse both sides.
Preferably, also comprise the step of cutting off described virtual polysilicon layer.
Preferably, at virtual polysilicon layer described in described cut-out step, be completely removed.
Preferably, also be included on the polysilicon layer of described electrically programmable fuse device architecture and form successively self aligned polycide layer, contact hole etching stop-layer and interlayer dielectric layer, and the step that forms the contact hole that connects described negative electrode and described anode in described interlayer dielectric layer.
To sum up, according to manufacturing process of the present invention, form the electrically programmable fuse device architecture of the fuse with even, narrow and small-feature-size.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 (a) is according to the SEM schematic diagram of the electrically programmable fuse device architecture of prior art making;
Fig. 1 (b) is single electrically programmable fuse device and a programmable transistorized schematic diagram of making according to prior art;
Fig. 2 A is the top end view that first execution mode is made electrically programmable fuse device architecture according to the present invention;
Fig. 2 B is the sectional arrangement drawing view that first execution mode is made electrically programmable fuse device architecture according to the present invention;
Fig. 3 is second top end view that execution mode is made electrically programmable fuse device architecture according to the present invention;
The top end view of the device that the correlation step that Fig. 4 A-Fig. 4 C is the 3rd the execution mode making electrically programmable fuse device architecture according to the present invention obtains;
Fig. 5 makes the process chart of electrically programmable fuse device architecture according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that how explanation the present invention adopts a kind of new method to make electrically programmable fuse device architecture, to meet the more requirement of advanced technology node.Detailed being described below of obvious preferred embodiment of the present invention, however remove outside these detailed descriptions, and the present invention can also have other execution modes.
The present invention proposes a kind of electrically programmable fuse device architecture and manufacture method.Fig. 2 A-2B is top end view and the sectional arrangement drawing view that first execution mode is made electrically programmable fuse device architecture according to the present invention.
As shown in Figure 2 B, first semi-conductive substrate (not shown) is provided, described Semiconductor substrate can be silicon or silicon-on-insulator (SOI), in Semiconductor substrate, form insulating oxide 200, insulating oxide 200 can be shallow trench isolation from (STI) oxide layer or buried oxide (BOX), its preparation method can adopt the techniques such as region oxidizing process and shallow isolating trough.Preferred shallow trench isolating oxide layer, as an example, the step that forms described shallow trench isolating oxide layer comprises, forms the first silicon oxide layer and nitration case on the substrate of defined active area, the substrate of etching the first silicon oxide layer, silicon nitride layer and partial depth, to form shallow trench between described active area, in described shallow trench, form silicon dioxide layer, at silicon dioxide layer, cover nitration case, leveling the second silicon oxide layer, to expose the nitration case that is coated with source region, remove nitration case.Then, can adopt chemical vapor deposition (CVD) or other suitable method on shallow trench isolating oxide layer 200, to form polysilicon layer (not shown), the formation method of polysilicon layer is preferably used low-pressure chemical vapor phase deposition (LPCVD) technique.As an example, the process conditions that form described polysilicon layer comprise: reacting gas is silane (SiH
4), the range of flow of described silane can be 100～200 cc/min (sccm), as 150 cc/min (sccm); In reaction chamber, temperature range can be 700～750 degrees Celsius; Reaction chamber internal pressure can be 250～350 milli millimetress of mercury (mTorr), as 300mTorr; In described reacting gas, also can comprise buffer gas, described buffer gas can be helium (He) or nitrogen, and the range of flow of described helium and nitrogen can be 5～20 liters/min (slm), as 8slm, 10slm or 15slm.Then, can adopt reactive ion etching (RIE) or other suitable method optionally to remove part polysilicon layer, etching forms the polysilicon layer 201 of electrically programmable fuse as shown in Figure 2 A thus, it is the polysilicon layer 201 of bottleneck shape, the polysilicon layer 201 of electrically programmable fuse comprises: the polysilicon layer 201b of fuse, the polysilicon layer 201a of large fuse head at the polysilicon layer 201b two ends of fuse and the polysilicon layer 202c of little fuse head, wherein, the polysilicon layer of large fuse head 201a can be used as the negative electrode of electrically programmable fuse device architecture, the polysilicon layer of little fuse head 201c can be used as the anode of electrically programmable fuse device architecture, the size of negative electrode polysilicon layer is greater than the size of anode polysilicon layer.Meanwhile, be formed with virtual polysilicon (Dummy poly) layer 202 in the both sides of the polysilicon layer 201b of fuse, virtual polysilicon layer 202 and negative electrode polysilicon layer 201a are connected and are also positioned at the both sides of anode polysilicon simultaneously.Wherein, be positioned at the virtual polysilicon layer 202 of both sides of the polysilicon layer 201b of fuse, to its objective is in order preventing and to form in the process for making of polysilicon layer 201 of fuse because polysilicon layer density is too low through etching composition at polysilicon layer, the live width of fuse is smaller, affect size and the uniformity of the polysilicon layer of fuse, (technological factor of impact comprises photoetching to the structure of the polysilicon layer of damage fuse, etching etc.), therefore, the virtual polysilicon layer 202 of polysilicon layer 201 both sides of electrically programmable electric fuse structure be for realize there is even and narrow fuse electrically programmable electric fuse device structure to meet more advanced technology node.Wherein, polysilicon layer 201 can mix N-type or P type or undope.Or polysilicon layer 201 is adopted to three sections of different doping, as shown in Figure 2 A, at 201a, 201b and 201c, be three sections of different doped polycrystalline silicon, wherein, 201a is N-type (or P type), 201c is contrary with 201a dopant species is P type (or N-type), and 201b can be district or N-type doped region or P type doped region or the P Xing HeNXing co-doped district of undoping.They are all the polysilicons of same layer deposition, adopt ion implantation doping to form, can with CMOS integrated circuit in N
+inject and/or P
+inject and/or N-type drain electrode before prolong inject and/or the drain electrode of P type before prolong and inject mask plate and share, do not increase so any processing step and chip area, only depend on layout design to realize.
Then, on the polysilicon layer 201 of electrically programmable fuse, form self aligned polycide (salicide) layer 203.As an example, the technique that forms self aligned polycide layer comprises, depositing metal layers first, and it can comprise the material of tungstenic, titanium, nickel, cobalt, tantalum and platinum or its combination.Then heated substrate, causes metal level and the polysilicon layer generation silicification under it, to form metal silication layer region.Adopt erodable metal level, but the etchant in unlikely attack metal disilicide layer region, so that unreacted metal level is removed.Subsequently, on the polysilicon layer 201 of described electrically programmable fuse and the sidewall of self aligned polycide layer 203, form clearance wall structure 204.Then, on insulating oxide 200, self aligned polycide layer 203 and clearance wall structure 204, form contact hole etching stop-layer 205, the material preferred nitrogen compound of contact hole etching stop-layer 205.
Then, form interlayer dielectric layer (not shown) on contact hole etching stop-layer 205, it can be one deck or multilayer formation, and the material of interlayer dielectric layer can be a kind of in oxide, nitride, nitrogen oxide or constitute.The method of preparation can adopt ion injection method, heat or plasma oxidation or nitriding method, chemical gaseous phase depositing process and physical gas-phase deposite method.
Then, two ends in interlayer dielectric layer form through hole, described through hole exposes metal silicide layer 203, then adopt electric conducting material filling vias, electric conducting material and metal silicide layer 203 are contacted, form the contact hole 206 that connects described negative electrode and anode, the electric conducting material of filling in described through hole can be doped polycrystalline silicon, metal material etc., the preferred tungsten material of described electric conducting material.
After above-mentioned process implementing, forming electrically programmable fuse structure of the present invention comprises, Semiconductor substrate (not shown), in Semiconductor substrate, be formed with the polysilicon layer 201 of insulating oxide 200 and electrically programmable fuse, the polysilicon layer 201 of described electrically programmable fuse comprises: the polysilicon layer 201b of fuse, the negative electrode polysilicon layer 201a at the polysilicon layer 201b two ends of fuse and anode polysilicon layer 202c, that the both sides that are positioned at the polysilicon layer 201b of electrically programmable fuse on insulating oxide 200 are formed with virtual polysilicon layer 202 simultaneously, simultaneously, virtual polysilicon layer 202 is connected with negative electrode polysilicon layer 201a and is also positioned at the both sides of anode polysilicon layer 201c.On described polysilicon layer 201, be formed with self aligned polycide layer 203, on the sidewall of polysilicon layer 201 and self aligned polycide layer 203, be formed with clearance wall structure 204, then, on insulating oxide 200, self aligned polycide layer 203 and clearance wall structure 204, be formed with the contact hole 206 of contact hole etching stop-layer 205, interlayer dielectric layer (not shown) and the described negative electrode of the connection at interlayer dielectric layer two ends and described anode.
Fig. 3 is second top end view that execution mode is made electrically programmable fuse device architecture according to the present invention, is that with the difference of first embodiment virtual polysilicon layer 302 is not connected with the negative electrode polysilicon layer 301a in polysilicon layer 301.Wherein, the virtual polysilicon layer 302 forming in the polysilicon layer 301b both sides of fuse, to its objective is in order realizing and to have even and narrow electrically programmable electric fuse device structure to meet the requirement of more advanced technology node.
After process implementing based on identical with first embodiment, forming electrically programmable fuse device architecture of the present invention comprises, Semiconductor substrate (not shown), in Semiconductor substrate, be formed with the polysilicon layer 301 of insulating oxide (not shown) and electrically programmable fuse, the polysilicon layer 301 of described electrically programmable fuse comprises: the polysilicon layer 301b of fuse, the negative electrode polysilicon layer 301a at the polysilicon layer 301b two ends of fuse and anode polysilicon layer 302c, to be formed with virtual polysilicon layer 302 in the both sides of the polysilicon layer 301b of fuse simultaneously, simultaneously, virtual polysilicon layer 302 is not connected with negative electrode polysilicon layer 301a and is also positioned at the both sides of anode polysilicon layer 301c.On the polysilicon layer 301 of described electrically programmable fuse, be formed with self aligned polycide layer (not shown), on the polysilicon layer 301 of electrically programmable fuse and the sidewall of self aligned polycide layer, be formed with clearance wall structure (not shown), then, on insulating oxide 300, self aligned polycide layer and clearance wall structure, be formed with the contact hole 303 of contact hole etching stop-layer (not shown), interlayer dielectric layer (not shown) and the described negative electrode of the connection at interlayer dielectric layer two ends and described anode.
The top end view of the device that each step that Fig. 4 A-Fig. 4 C is the 3rd the execution mode making electrically programmable fuse device architecture according to the present invention obtains.Be with the difference of first and second embodiment, the 3rd execution mode adopts the cutting of P2-mask cut(P2-mask) technique make the negative electrode polysilicon layer 401a in the polysilicon layer 401 of virtual polysilicon layer 402 and electrically programmable fuse separated with anode polysilicon layer 401b, cut off virtual polysilicon layer 402, or can cut completely and remove virtual polysilicon layer 402.
As shown in Figure 4 A, first semi-conductive substrate (not shown) is provided, described Semiconductor substrate can be silicon or silicon-on-insulator (SOI), in Semiconductor substrate, form insulating oxide (not shown), insulating oxide can be shallow trench isolation from (STI) oxide layer or buried oxide (BOX), can adopt the techniques such as region oxidizing process and shallow isolating trough.Preferred shallow trench isolating oxide layer.Then, can adopt chemical vapor deposition (CVD) or other suitable method to form polysilicon layer (not shown) on shallow trench isolating oxide layer (not shown), then, can adopt reactive ion etching (RIE) or other suitable method optionally to remove part polysilicon layer, form thus the polysilicon layer 401 of electrically programmable fuse as shown in Figure 4 A, it is the polysilicon layer 401 of bottleneck shape, the polysilicon layer 401 of electrically programmable fuse comprises: the polysilicon layer 401b of fuse, the polysilicon layer 401a of large fuse head at the polysilicon layer 401b two ends of fuse and the polysilicon layer 402c of little fuse head, wherein, the polysilicon layer 401a of large fuse head is as the negative electrode of electrically programmable fuse device architecture, the polysilicon layer 401c of little fuse head is as the anode of electrically programmable fuse device architecture, the size of negative electrode polysilicon layer is greater than the size of anode polysilicon layer.Both sides at the polysilicon layer 401b of fuse are formed with virtual polysilicon layer 402, and virtual polysilicon layer 402 is all connected with anode polysilicon layer 402c with negative electrode polysilicon layer 401a simultaneously.Wherein, the virtual polysilicon layer 402 forming in the polysilicon layer 401b both sides of fuse, its objective is in order to realize even and narrow small-feature-size electrically programmable electric fuse device structure to meet more advanced technology node.
As shown in Figure 4 B, adopt P2-mask to cut virtual polysilicon layer 402.Wherein, because P2-mask in advanced technology node is more for the treatment of polysilicon and silicon oxynitride.Therefore, when the virtual polysilicon layer 402 of cutting, can share P2-mask with polysilicon and silicon oxynitride, not increase the consumption of extra processing step and semi-conducting material.Through adopting P2-mask to cut after virtual polysilicon layer 402, virtual polysilicon layer 402 is separated with negative electrode polysilicon layer 401a and anode polysilicon layer 401b, cut off virtual polysilicon layer 402.Wherein, preferably adopt P2-mask to cut completely and remove virtual polysilicon layer 402.Finally, form the polysilicon layer 403 of electrically programmable electric fuse.
As shown in Figure 4 C, on polysilicon layer 403, form self aligned polycide (salicide) layer (not shown).Then, on the sidewall of polysilicon layer 403 and self-alignment silicide layer, form clearance wall structure (not shown), on insulating oxide 400, form contact hole etching stop-layer (not shown), wherein the preferred titanium nitride of the material of contact hole etching stop-layer.Then, on contact hole etching stop-layer, form interlayer dielectric layer (not shown).Then, two ends in dielectric layer form through hole, described through hole exposes metal silicide layer, then adopt electric conducting material filling vias, electric conducting material and metal silicide layer are contacted, form the contact hole 404 that connects described negative electrode and described anode, the electric conducting material of filling in described through hole can be doped polycrystalline silicon, metal material etc., the preferred tungsten material of described electric conducting material.
After above-mentioned process implementing, forming electric fuse device structure of the present invention comprises, Semiconductor substrate (not shown), in Semiconductor substrate, be formed with the polysilicon layer 403 of insulating oxide (not shown) and electrically programmable fuse, the polysilicon layer 403 of described electrically programmable fuse comprises: the negative electrode polysilicon layer 403a at the polysilicon layer 403b two ends of the polysilicon layer 403b of fuse, fuse and anode polysilicon layer 403c.On insulating oxide, be also formed with cut virtual polysilicon layer 402, it is all connected with anode polysilicon layer with negative electrode polysilicon layer simultaneously.On the polysilicon layer 403 of described electrically programmable fuse, be formed with self aligned polycide layer (not shown), on the polysilicon layer 403 of electrically programmable fuse and the sidewall of self aligned polycide layer, form clearance wall structure (not shown), on insulating oxide, self aligned polycide layer and clearance wall structure, be formed with contact hole etching stop-layer, on described contact hole etching stop-layer, be formed with the contact hole 404 of interlayer dielectric layer (not shown) and the described negative electrode of the connection at interlayer dielectric layer two ends and described anode.
Fig. 5 makes the flow chart of electrically programmable fuse device architecture according to one embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 501, Semiconductor substrate is provided, in Semiconductor substrate, form insulating oxide.In step 502, on insulating oxide, form polysilicon layer and the virtual polysilicon layer of electrically programmable fuse, the polysilicon layer of electrically programmable fuse comprises: the negative electrode polysilicon layer at the polysilicon layer two ends of the polysilicon layer of fuse, fuse and anode polysilicon layer, virtual polysilicon layer is positioned at the both sides of the polysilicon layer of fuse.Wherein virtual polysilicon layer can be connected with negative electrode polysilicon layer, virtual polysilicon layer can not be connected with negative electrode polysilicon layer or virtual polysilicon layer can all be connected with anode polysilicon layer with negative electrode polysilicon layer and virtual polysilicon layer is cut off.In step 503, on the polysilicon layer of electrically programmable fuse, form self aligned polycide layer, on the sidewall of polysilicon layer and autoregistration multicrystalline silicon compounds, be formed with clearance wall structure.In step 504, on insulating oxide, self aligned polycide layer and clearance wall structure, form etching stop layer dielectric layer and interlayer dielectric layer.In step 505, in interlayer dielectric layer, form the contact hole that connects described negative electrode and described anode.
To sum up, the present invention proposes structure and the manufacture method of new electrically programmable fuse device, according to the present invention, technique can form the electrically programmable fuse device architecture of small-feature-size, between the fuse head of two ends, forms even and narrow fuse.This electrically programmable fuse device architecture can meet the more requirement of advanced technology node
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. an electrically programmable fuse device architecture, comprising:
Semiconductor substrate;
The insulating oxide forming in described Semiconductor substrate;
The described negative electrode of negative electrode, anode and connection of the electrically programmable fuse structure forming on described insulating oxide and the fuse of described anode, and the virtual polysilicon layer that is positioned at described fuse both sides.
2. electrically programmable fuse device architecture as claimed in claim 1, is characterized in that, described insulating oxide is shallow trench isolating oxide layer.
3. electrically programmable fuse device architecture as claimed in claim 1, is characterized in that, the size of described negative electrode is greater than the size of described anode.
4. electrically programmable fuse device architecture as claimed in claim 3, is characterized in that, described virtual polysilicon layer is connected with described negative electrode and is positioned at the both sides of described anode.
5. electrically programmable fuse device architecture as claimed in claim 3, is characterized in that, described virtual polysilicon layer is not connected with described negative electrode and is positioned at the both sides of described anode.
6. electrically programmable fuse device architecture as claimed in claim 1, is characterized in that, the disrupted configuration of described virtual polysilicon layer for being connected with described anode with described negative electrode respectively.
7. electrically programmable fuse device architecture as claimed in claim 6, is characterized in that, described virtual polysilicon layer is the virtual polysilicon layer that is cut off formation.
8. electrically programmable fuse device architecture as claimed in claim 7, is characterized in that, adopts P2-mask to cut off described virtual polysilicon layer.
9. manufacture, as a manufacture method for the electrically programmable fuse device architecture as described in any one in claim 1-8, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form insulating oxide;
On described insulating oxide, form polysilicon layer;
Described in etching, polysilicon layer to be to form the described negative electrode of negative electrode, anode and connection of electrically programmable fuse device architecture and the fuse of described anode, and the virtual polysilicon layer that is positioned at described fuse both sides.
10. method as claimed in claim 9, is characterized in that, also comprises the step of cutting off described virtual polysilicon layer.
11. methods as claimed in claim 10, is characterized in that, at virtual polysilicon layer described in described cut-out step, are completely removed.
12. methods as claimed in claim 9, it is characterized in that, also be included on the polysilicon layer of described electrically programmable fuse device architecture and form successively self aligned polycide layer, contact hole etching stop-layer and interlayer dielectric layer, and the step that forms the contact hole that connects described negative electrode and described anode in described interlayer dielectric layer.
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| CN109346435A (en) * | 2016-12-02 | 2019-02-15 | 乐清市风杰电子科技有限公司 | The manufacturing method of programmable polysilicon fuse structure |
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| CN104064548B (en) | 2017-08-01 |
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