JP2005244250A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, in which the resistance of a plug and wiring layers is reduced, or the parasitic capacitance between the wiring layers is reduced. <P>SOLUTION: The wiring layers comprising silicon layers are heated to 400°C or higher in an annealing process, then are substituted by a metal 8 for substitution. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for replacing an arbitrary portion of a polycrystalline silicon wiring layer with a low resistivity metal such as aluminum after completion of a process involving a high temperature heat treatment step. The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, design rules (lines / spaces) have become stricter with higher integration and larger capacity of semiconductor devices, and accordingly, wiring layers of semiconductor devices such as DRAM (Dynamic Random Access Memory). And the diameter of the via hole for forming the plug connecting the upper and lower wiring layers is becoming smaller.

  As described above, there is a problem that when the width of the wiring layer is reduced, the resistance is increased, resulting in a delay in operation speed, and the aspect ratio (depth / diameter) is extremely increased as the via hole diameter is reduced. Therefore, even if a CVD method having better step coverage than a sputtering method is used, Al cannot be completely embedded in such a via hole, and a void is formed inside the via hole. As a result of the reduced cross-sectional area of the portion, there is a problem that the resistance is increased or the wire is disconnected in some cases.

  In order to solve such a problem of fine via holes, a polysilicon-aluminum substrate (PAS) has been proposed (refer to Non-Patent Document 1 if necessary), so refer to FIG. To explain.

First, after depositing a 2.4 μm thick SiO ₂ film 202 on the silicon substrate 201 by a CVD method, the diameter of the bottom becomes 0.25 μm by RIE (reactive ion etching). A via hole, that is, a contact hole 203 is formed, and then a polycrystalline Si layer 204 that is much better than Al is deposited by low pressure chemical vapor deposition (LPCVD) to fill the inside of the contact hole 203.

Next, refer to FIG. 19B. Using a CMP method (chemical mechanical polishing method), polishing is performed until the surface of the SiO ₂ film 202 is exposed, and a polycrystalline Si layer embedded in the contact hole 203 is used to form polycrystalline Si. After the plug 205 is formed, an Al layer 206 having a thickness of 0.5 μm is deposited by sputtering.

Figure 19 (c) refer then by annealing treatment at 500 ° C. in a nitrogen atmosphere, by mutual diffusion of Si and Al, polycrystalline Si plug 205 is replaced with Al, then although not shown, SiO ₂ By polishing until the surface of the film 202 is exposed, a contact electrode made of an Al replacement plug 207 is formed.
In this case, the Si content in the Al replacement plug 207 is about 0.4% even in the bottom portion, and is almost replaced with Al.

  In the annealing step, a Ti layer having a thickness of 0.2 μm is deposited on the Al layer 206, so that the Ti layer functions as a Si absorption layer. It is thin, the annealing temperature can be lowered, and the annealing time can be shortened.

  By using such a polysilicon-aluminum substitution method (PAS method), a via hole having a maximum aspect ratio of about 10 and a diameter of 0.1 μm or less can be filled with low-resistance Al, and future MPU (Microprocessor) Unit) and DRAM plugs (contact electrodes).

  However, when such a polysilicon-aluminum replacement method is applied to an actual LSI manufacturing process, there is a relationship with other processes, and various problems arise due to the simple introduction of the above-described single process. Is expected.

  For example, when applied to a source / drain contact electrode of an IGFET (Insulated Gate Field Effect Transistor), since the source / drain region is made of the same Si as the polycrystalline Si layer, the polycrystalline Si plug is made of Al. After the replacement, the source / drain regions are also replaced with Al.

  Then, if Al enters the pn junction formed in the silicon substrate, the pn junction is destroyed due to an Al spike extending between the pn junctions. This is a fatal damage to the LSI. Become.

  Therefore, when applying such a polysilicon-aluminum substitution method to an actual device, the present inventor has provided a stopper film or a barrier film serving as an Al stopper between the source / drain regions and the polycrystalline Si plug. This application example will be described with reference to FIG.

  In general, the provision of a stopper film or a barrier film to prevent diffusion itself is a conventional method. However, in the case of the polysilicon-aluminum substitution method, it does not react with Al or reacts even at a high temperature. It was necessary to select a difficult material, and it was determined that TiN, WN, or SiC was appropriate as such a material.

  However, since TiN, WN, or SiC has poor reactivity with Si and it is difficult to make electrical contact, there is a problem that the contact resistance with the source / drain region becomes very high. In addition, a film that easily reacts with Si, that is, a contact metal is formed thinly at the interface between the stopper film or the barrier film and the source / drain region.

First, after an element isolation oxide film 212 is formed by selective oxidation in a predetermined region of the p-type silicon substrate 211, the exposed surface of the p-type silicon substrate 211 surrounded by the element isolation oxide film 212 is thermally oxidized. Then, a gate oxide film 213 is formed, and after depositing a non-doped polycrystalline Si layer, impurities such as P (phosphorus) are ion-implanted, and then the protective film 215 and the entire surface are formed by CVD. After depositing the SiO ₂ film or Si ₃ N ₄ film, the gate electrode 214 is formed by etching into a predetermined pattern.

Next, impurities such as As or P are ion-implanted using the gate electrode 214 and the protective film 215 as a mask to form n-type source / drain regions 217, and then a SiO ₂ film is deposited on the entire surface by CVD to anisotropically Side walls 216 are formed by performing etching.

Then, by CVD, after depositing the the Si ₃ N ₄ film 218 serving as a stopper film during the etching the entire surface, and the entire surface the Si ₃ N ₄ film 218 and a different SiO ₂ film is deposited etching characteristics by CVD and an interlayer insulating film 219, then, after the the Si ₃ N ₄ film 218 to form an opening in the interlayer insulating film 219 as an etching stopper layer, to selectively remove the Si ₃ N ₄ film 218 exposed in the opening.

  Next, a 20 nm thick Ti film 220 as a contact metal and a 10-100 nm thick TiN film 221 as a barrier metal are sequentially deposited by sputtering or CVD.

  Next, after depositing a polycrystalline Si film using the LPCVD method, the polycrystalline Si plug 222 is formed by polishing by the CMP method until the TiN film 221 is exposed, and then a thickness of 2 μm is formed using the sputtering method. An Al layer 223 and a Ti layer 224 having a thickness of 200 nm are deposited.

Next, after the polycrystalline Si plug 222 is replaced with Al by performing a heat treatment at a temperature of 400 to 660 ° C. for about 1 hour in a nitrogen atmosphere, the interlayer insulating film is again used by CMP. The Al replacement plug 225 is formed by polishing until the surface of 219 is exposed.

  It has been found that the polysilicon-aluminum replacement method can be applied to an actual LSI manufacturing process by employing such a configuration, that is, employing a stopper film made of a contact metal and a barrier metal.

As the contact metal in this case, W, Co, Ni, Ta, or a silicide thereof can be used in addition to Ti, and silicide is already formed on the surface of the n-type source / drain region 217. In the case where the contact metal layer is formed, or when a base functioning as a contact metal is formed, the contact metal deposition step can be omitted.
International Electron Devices Meeting 96, p. 946-948

  However, in the application example described above, there is no problem when the annealing temperature is relatively low, such as 400 ° C. to 450 ° C., but when the heat treatment is performed at a higher temperature, for example, 450 ° C. to 850 ° C. Problems arise.

  That is, when heat treatment for Al substitution is performed at such a high temperature, Ti of the contact metal itself reacts with Si in the source / drain region, and enters the pn junction to destroy the pn junction. This is because a case occurs.

  Therefore, although there is no problem if such a contact plug formation process is the final process, a polycrystalline Si plug is provided through a stopper layer in the middle of the manufacturing process, and after a high temperature treatment process in the subsequent manufacturing process, If the silicon-aluminum substitution method is performed, an Al substitution plug can be formed, but the problem that Ti diffuses in the high temperature treatment process and destroys the pn junction, and the eutectic alloy of Ti and Si is caused by the diffusion of Ti. There is also a problem that impurities are abnormally segregated in this eutectic region and contact failure occurs, so that the application process is limited.

  In addition, since the conventional polysilicon-aluminum replacement method only assumes replacement of the polycrystalline Si plug, the lower wiring layer constituting the conductive path of the LSI is higher than Al (specific resistance: 2.8 μΩ · cm). Doped polycrystalline Si with high resistance (specific resistance: 300 to 800 μΩ · cm), refractory metal (specific resistance of W: 6 μΩ · cm), or refractory metal silicide (specific resistance of W silicide: 70 μΩ · cm, Ti Since the high-temperature resistant material such as the specific resistance of silicide (15 μΩ · cm) remains, the merit of the polysilicon-aluminum substitution method cannot be fully utilized.

  For example, in the case of a DRAM bit line, a storage electrode and a capacitor insulating film constituting a capacitor of a memory cell are formed above the bit line. In the current technology, this capacitor insulating film is formed at 600 ° C. Since it is very difficult to obtain high reliability by forming at a low temperature, high temperature heat treatment at 700 ° C. to 850 ° C. is required.

  Since this process is after the formation of the bit line, Al having a melting point of 660 ° C. cannot be used for the bit line. However, if Al can be used for the bit line, the resistance of the bit line is simply lowered. In addition to being able to do this, it is allowed to make the bit line thin, so that the parasitic capacitance between adjacent bit lines can be reduced, and a high-speed and low-power consumption memory LSI can be manufactured. It becomes possible.

  Further, since the resistance and parasitic capacitance of the bit line can be reduced, the number of cells connected to one bit line can be increased, so that the degree of integration of the memory can be increased. There is a long-awaited desire for Al in bit lines.

  In the case of a normal self-aligned IGFET, ion implantation is performed using a gate electrode as a mask, and annealing for activation is performed to form a source / drain region. This annealing temperature is 800 ° C. Since it is about ˜1100 ° C., Al is not used as the gate electrode.

  However, if Al can be used as the gate electrode, as in the case of the bit line, it can greatly contribute to speeding up and lowering power consumption of the LSI, and a high added value LSI can be manufactured. In addition, if Al can be used as the gate electrode of the memory, that is, the word line, the number of cells that can be connected to one word line can be increased, and the degree of integration of the memory can be increased. Become.

  In the case of a self-aligned bipolar transistor, an external base region and an emitter region are formed by solid-phase diffusion of impurities from a base extraction electrode and an emitter electrode made of a doped polycrystalline Si layer. Therefore, Al cannot be used as a diffusion source / electrode because the heat treatment temperature for the heat treatment is 800 ° C. to 1100 ° C.

  However, if the base extraction electrode and the emitter electrode can be replaced with Al, it is possible to significantly increase the speed and reduce the power consumption, which is very desirable.

  Therefore, in order to reduce the resistance of such a wiring layer or electrode, even if the application of the polysilicon-aluminum replacement method is considered, the above-described bit line, gate electrode, or base lead electrode is not provided on the surface of the LSI. The bit line, the gate electrode, or the base lead electrode is formed of a polycrystalline Si layer and is formed on Al by the polysilicon-aluminum substitution method. Even if the replacement is attempted, the simple application of the polysilicon-aluminum replacement method causes a problem that the thick Al layer necessary for the replacement cannot be connected to the polycrystalline Si layer to be replaced.

  Moreover, since the state-of-the-art LSI has a structure in which the source / drain electrodes are formed with respect to the word lines and the capacitor contacts are formed with self-alignment with respect to the bit lines, the upper portions of the word lines and the bit lines are formed. It is indispensable to be covered with an insulating film, and it is not allowed to remove the insulating film in the subsequent process.

  Therefore, the conventional polysilicon-aluminum replacement method in which Al replacement is performed by exposing the upper portion of the word line or the bit line and contacting with a thick replacement Al layer can be applied to the dense portion of the cell. Therefore, some ingenuity is necessary.

For example, when replacing a bit line with Al,
a. A structure in which the bit line itself is easily replaced with Al, and a structure of an introduction portion of Al replacement,
b. After replacing the bit line with Al, a stopper structure for preventing Al from entering further lower polycrystalline Si plugs and source / drain regions,
c. Stopper structure when the upper plug in contact with the lower plug that is not desired to be replaced with Al is replaced with Al,
It is necessary to devise such measures, and if these measures are taken separately, the work constant increases and the cost increases, so some contrivance to prevent an increase in the manufacturing process is also necessary.

  In particular, in DRAM, competition among manufacturers is fierce, and cost reduction is very important. Even if a polysilicon-aluminum replacement method can be introduced to achieve high functionality, it is most important to reduce cost. This is a problem, and it is indispensable to prevent the cost of the Al replacement process itself and the accompanying stopper formation process.

  In addition, when the polysilicon-aluminum substitution method is applied to the gate electrode, the gate insulating film is a very delicate thin insulating film, and the reliability of the gate electrode is easily lost due to the diffusion of a small metal. In the case of replacing Al, a device that does not impair the reliability of the gate insulating film is necessary.

  In addition, when the polysilicon-aluminum substitution method is applied to the base extraction electrode and the emitter extraction electrode of the self-aligned bipolar transistor, these extraction electrodes also serve as impurity diffusion sources. It is necessary to devise an electrode structure so that it can play a role.

  Furthermore, in order to increase the speed and power consumption of LSI, it is necessary to reduce the parasitic capacitance between wiring layers. However, in conventional LSI, the dielectric constant of the insulating film itself constituting the interlayer insulating film is lowered. Therefore, parasitic capacitance countermeasures were not sufficient.

  Therefore, the present invention reduces the resistance of the plug and the wiring layer by applying the polysilicon-aluminum replacement method so that the manufacturing process does not increase so much and the device characteristics are not adversely affected, or An object is to reduce parasitic capacitance between wiring layers.

FIG. 1 is an explanatory diagram of the principle configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
1 (a) and 1 (b). (1) In the present invention, in the method of manufacturing a semiconductor device, a wiring layer composed of a silicon layer is subjected to a heat treatment step of 400 ° C. or higher and then replaced with a replacement metal 8. It is characterized by doing.

  In this way, the wiring layer that has been conventionally required to be composed of a heat-resistant silicon layer due to the heat treatment process can be reduced in resistance by replacing the metal with a silicon plug, thereby reducing the resistance. The operating speed of the semiconductor device can be greatly increased.

  (2) Further, according to the present invention, in the above (1), the wiring layer formed of the silicon layer is a bit line or a word line of the dynamic random access memory, and the dynamic random access memory A stopper pad is provided at the entry portion of the replacement metal 8 in the non-replacement portion of the plug or wiring layer of the circuit element constituting the peripheral circuit.

In this way, by providing the stopper pad at the non-substitution portion, for example, the entry portion of the substitution metal 8 in the gate electrode 3 or the like where it is desired to avoid the variation of _Vth due to metal substitution as much as possible, the metal substitution only at a desired location can be achieved. It becomes possible.

  (3) Further, according to the present invention, in the method of manufacturing a semiconductor device, after replacing a silicon plug or a silicon wiring layer provided on the semiconductor substrate 1 with an insulating film with a replacement metal 8, the metal replacement is performed. The cavity is formed by removing at least a part or the whole of the plug 10 or the metal replacement wiring layer.

  In this way, by removing at least part or all of the metal replacement plug 10 or the metal replacement wiring layer formed by using metal replacement and forming a cavity, the effective dielectric constant of the insulating film including the cavity is determined. Can be significantly reduced, and thereby parasitic capacitance can be reduced.

  (4) Further, in the present invention according to the above (3), the cavity is formed by replacing the sidewall made of the silicon layer provided on the sidewall of the gate electrode 3 with the replacement metal 8 and then removing the cavity. It is characterized by being.

  As described above, by using the silicon sidewall, a cavity can be formed in the side portion of the gate electrode 3, thereby reducing the parasitic capacitance between the gate electrode 3 and the source / drain electrodes. .

  According to the present invention, since a high-temperature treatment process is involved in the subsequent process, the wiring layer and the electrode where the Al could not be used are replaced with Al using a polysilicon-aluminum substitution method after the high-temperature treatment process is completed. Since the resistance is reduced, the operating speed of various semiconductor devices can be greatly increased, and it contributes to the reduction of power consumption.

  In the present invention, a wiring layer composed of a silicon layer is subjected to a heat treatment step at 400 ° C. or higher, for example, with a bit line or a word line of a dynamic random access memory, and then replaced with a replacement metal.

Here, the steps of the first embodiment of the present invention will be described with reference to FIG.
Refer to FIG. 2A. As in the prior art, as described with reference to FIG. 18, first, an element isolation oxide film 12 is formed in a predetermined region of the p-type silicon substrate 11 by selective oxidation, and then surrounded by the element isolation oxide film 12. The exposed surface of the p-type silicon substrate 11 is thermally oxidized to form a gate oxide film 13, and then a non-doped polycrystalline Si layer is deposited, and then P is ion-implanted to form a doped polycrystalline Si layer. Next, after depositing a SiO ₂ film to be the protective film 15 by the CVD method on the entire surface, the gate electrode 14 is formed by etching into a predetermined pattern.

Next, As is ion-implanted using the gate electrode 14 and the protective film 15 as a mask to form the n-type source / drain regions 17, and then an SiO ₂ film is deposited on the entire surface by a CVD method and anisotropic etching is performed. As a result, the sidewall 16 is formed.

Next, a Si ₃ N ₄ film 18 having a thickness of 10 to 100 nm serving as a stopper film at the time of etching is deposited on the entire surface by a CVD method, and then a thickness different from that of the Si ₃ N ₄ film 18 on the entire surface by the CVD method. An SiO ₂ film having a thickness of 100 to 500 nm is deposited to form an interlayer insulating film 19. Next, an opening is formed in the interlayer insulating film 19 using the Si ₃ N ₄ film 18 as an etching stopper layer, and then exposed to the Si _3. Via holes reaching the n-type source / drain regions 17 are formed by selectively removing the N ₄ film 18.

  Next, after depositing a polycrystalline Si layer doped with impurities by LPCVD, polishing is performed by CMP until the first interlayer insulating film 19 is exposed, thereby forming a polycrystalline Si plug 20 having conductivity.

  Next, a Ti film 21 having a thickness of 10 to 100 nm, for example, 20 nm, serving as a contact metal, and a TiN film 22 having a thickness of 10 to 200 nm, for example, 50 nm, serving as a barrier metal, are sequentially deposited by sputtering. Etching is performed so as to remain on the crystalline Si plug 20 to form a stopper pad for Al.

Next, again, a CVD method is used to deposit a SiO ₂ film having a thickness of 0.05 to 5.0 μm, for example, 0.5 μm on the entire surface to form the second interlayer insulating film 23, and then a via hole reaching the stopper pad Next, after depositing a non-doped polycrystalline Si layer again by LPCVD, the polycrystalline Si plug 24 is formed by polishing by CMP until the second interlayer insulating film 23 is exposed.

  Next, an Al layer 25 having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer 26 having a thickness of 50 to 2000 nm, for example, 200 nm are deposited by sputtering.

See FIG. 2B. Next, the polycrystalline Si plug 24 was replaced with Al by performing heat treatment at 400 to 660 ° C., for example, 500 ° C., for 1.0 to 48 hours, for example, 6 hours in a nitrogen atmosphere. Thereafter, the Al replacement plug 27 is formed by polishing again until the surface of the second interlayer insulating film 23 is exposed using the CMP method.

  As described above, in the first embodiment of the present invention, since the stopper pad is provided between the polycrystalline Si plug 20 provided in the lower part and the polycrystalline Si plug 24 provided in the upper part, the upper polycrystalline substance is provided. When replacing the Si plug 24 with Al, Al does not diffuse into the lower polycrystalline Si plug 20, and therefore the pn junction constituting the n-type source / drain region 17 is not destroyed.

  Further, even if a high temperature process of 450 ° C. or higher is performed in the heat treatment process accompanying the polysilicon-aluminum replacement process or other manufacturing processes, diffusion of Ti as a contact metal constituting the stopper pad occurs. The presence of the lower polycrystalline Si plug 20 increases the distance from the n-type source / drain region 17, so that no junction breakdown occurs.

  For the same reason, Ti and Si in the n-type source / drain region 17 do not form a eutectic alloy, and abnormal segregation of impurities accompanying the eutectic alloy does not occur, resulting in contact failure. Thus, the specific resistance of the minute via hole can be reduced, and the reliability of the element can be improved.

Next, the steps of the second embodiment of the present invention will be described with reference to FIG.
Since the manufacturing process of the lower polycrystalline Si plug is exactly the same as in the first embodiment, the description thereof is omitted.

See FIG. 3. After forming the polycrystalline Si plug 20 having conductivity as in the first embodiment, the thickness becomes 10 to 100 nm, for example, 20 nm of a Ti film 21 serving as a contact metal, and the thickness serving as a barrier metal. A TiN film 22 having a thickness of 10 to 200 nm, for example, 50 nm, and a W layer having a thickness of 10 to 500 nm, for example, 50 nm, which effectively becomes a wiring layer, are sequentially deposited by sputtering, and then deposited on the polycrystalline Si plug 20. Etching is performed so as to remain, thereby forming a W pad 28 and a W wiring layer 29.

Next, again, a CVD method is used to deposit a SiO ₂ film having a thickness of 0.05 to 5.0 μm, for example, 0.5 μm on the entire surface to form the second interlayer insulating film 23. Then, the W pad 28 and the W wiring are formed. A via hole reaching the layer 29 is provided, and then a non-doped polycrystalline Si layer is deposited again by LPCVD, and then polished by CMP until the second interlayer insulating film 23 is exposed, so that a polycrystalline Si plug is obtained. (Not shown).

  Next, an Al layer (not shown) having a thickness of 0.1 to 10.0 μm, for example, 2 μm, and a Ti layer (not shown) having a thickness of 50 nm to 2000 nm, for example, 200 nm were deposited by sputtering. Thereafter, the polycrystalline Si plug is replaced with Al by performing heat treatment at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours in a nitrogen atmosphere, and then again using the CMP method. The Al replacement plugs 27 and 30 are formed by polishing until the surface of the second interlayer insulating film 23 is exposed.

  As described above, in the second embodiment of the present invention, the stopper pad serving as a barrier against Al is formed using the wiring layer forming step, so that the film forming step for forming the stopper pad is performed. In addition, the patterning process is not necessary.

  In this case, W constituting the W pad 28 and the W wiring layer 29 reacts with Si of the polycrystalline Si plug for replacement to be partly or entirely silicided, but the TiN film 22 serves as a barrier against Al. , Al does not diffuse into the lower polycrystalline Si plug 20, and therefore, the pn junction constituting the n-type source / drain region 17 is not destroyed, and the junction destruction by Ti or eutectic alloy is caused. No contact failure occurs.

  Note that the W layer in the second embodiment may be replaced with WN, W silicide, Ta, Ti, TiN, Ti silicide, Co silicide, or the like, and has a low specific resistance as much as possible. A highly heat-resistant conductive material is desirable, and when WN or TIN is used, it is not necessary to provide the TiN film 22 as a barrier metal.

Next, the process of the 3rd Embodiment of this invention is demonstrated with reference to FIG.
Since the manufacturing process of the lower polycrystalline Si plug is exactly the same as in the first embodiment, the description thereof is omitted.

See FIG. 4A. After forming the polycrystalline Si plug 20 having conductivity as in the first embodiment, the Ti film 21 and the barrier metal having a thickness of 10 to 100 nm, for example, 20 nm, which become contact metal, A TiN film 22 having a thickness of 10 to 200 nm, for example, 50 nm is sequentially deposited by sputtering, and then a non-doped polycrystalline Si layer having a thickness of 10 to 1000 nm, for example, 300 nm, is deposited by using LPCVD. After that, etching is performed so as to remain on the polycrystalline Si plug 20 to form a polycrystalline Si pad 31 and a polycrystalline Si wiring layer 32.

Next, again, a CVD method is used to deposit a SiO ₂ film having a thickness of 0.05 to 5.0 μm, for example, 0.5 μm on the entire surface to form the second interlayer insulating film 23, and then the polycrystalline Si pad 31 and By providing a via hole reaching the polycrystalline Si wiring layer 32, and then depositing a non-doped polycrystalline Si layer again by the LPCVD method, polishing by the CMP method until the second interlayer insulating film 23 is exposed. Polycrystalline Si plugs 24 and 33 are formed.

  Next, an Al layer 25 having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer 26 having a thickness of 50 to 2000 nm, for example, 200 nm are deposited by sputtering.

Next, referring to FIG. 4B, polycrystalline Si plugs 24, 33 and polycrystalline are formed by performing heat treatment in a nitrogen atmosphere at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours. After the polycrystalline Si pad 31 and the polycrystalline Si wiring layer 32 connected to the Si plugs 24 and 33 are replaced with Al, polishing is performed again using the CMP method until the surface of the second interlayer insulating film 23 is exposed. Al replacement plugs 27 and 30, an Al replacement pad 34, and an Al replacement wiring layer 35 are formed.

  As described above, in the third embodiment of the present invention, the stopper pad serving as a barrier against Al is formed by using the wiring layer forming step, so that a patterning step for forming the stopper pad is performed. Since the wiring layer that is no longer needed and Al could not be used due to the high-temperature heat treatment at 600 ° C. or higher accompanying the subsequent manufacturing process can be replaced with low resistivity Al, the operation of the semiconductor device The speed can be increased.

  Such Al substitution of the polycrystalline Si wiring layer 32 is a matter clarified by the experiment of the present inventor, and the polycrystalline Si plug 33 can be connected without exposing the entire upper surface of the polycrystalline Si wiring layer 32. Thus, the length from the contact portion of the polycrystalline Si plug 33 to 100 μm can surely be substituted with Al, and the mutual solid phase is unpredictable from the Al substitution technique using only the polycrystalline Si plug itself. It became clear that diffusion occurred.

  In particular, in the third embodiment, non-doped polycrystalline Si wiring that is very low in conductivity as a wiring layer and not used as a conventional wiring layer in the middle of the manufacturing process. A structure that does not appear in the manufacturing process of the conventional semiconductor device is used, in which the layer 32 is used. By using such a non-doped polycrystalline Si wiring layer 32, Al substitution becomes easier, and the polycrystalline structure is obtained. Al substitution of the polycrystalline Si wiring layer at a position away from the Si plug 33 becomes possible.

Next, the process of the 4th Embodiment of this invention is demonstrated with reference to FIG.
FIG. 5B is a cross-sectional view taken along the gate lead-out wiring layer in FIG.
5A and 5B. First, an element isolation oxide film 12 is formed in a predetermined region of the p-type silicon substrate 11 by selective oxidation, and then the p-type silicon substrate 11 surrounded by the element isolation oxide film 12 is exposed. The surface is thermally oxidized to form a gate oxide film 13, and then a non-doped polycrystalline Si layer having a thickness of 10 to 300 nm, for example, 50 nm is deposited, and then P is ion-implanted to form a doped polycrystalline Si layer. 36.
Note that a doped polycrystalline Si film may be formed from the beginning.

Next, a TiN film 37 having a thickness of 10 to 100 nm, for example, 20 nm, which becomes a contact metal, and a TiN film 38 having a thickness of 10 to 200 nm, for example, 50 nm, which becomes a barrier metal, are sequentially deposited by sputtering, and then again LPCVD Is used to deposit a non-doped polycrystalline Si layer having a thickness of 10 to 1000 nm, for example, 150 nm, and then a SiO ₂ film serving as the protective film 15 is deposited on the entire surface by a CVD method to a predetermined pattern. Etching is performed to form a gate electrode and a gate lead-out wiring layer.

Next, As is ion-implanted using the gate electrode and the protective film 15 as a mask to form an n-type source / drain region 17, an SiO ₂ film is deposited on the entire surface, and anisotropic etching is performed to form the sidewall 16. Form.

Next, a Si ₃ N ₄ film 18 having a thickness of 10 to 100 nm serving as a stopper film at the time of etching is deposited on the entire surface by a CVD method, and then a thickness different from that of the Si ₃ N ₄ film 18 on the entire surface by the CVD method. An SiO ₂ film having a thickness of 100 to 500 nm is deposited to form an interlayer insulating film 19. Next, an opening is formed in the interlayer insulating film 19 using the Si ₃ N ₄ film 18 as an etching stopper layer, and then exposed to the Si _3. Via holes reaching the n-type source / drain regions 17 are formed by selectively removing the N ₄ film 18.

  Next, after depositing a polycrystalline Si layer doped with impurities by LPCVD, polishing is performed by CMP until the first interlayer insulating film 19 is exposed, thereby forming a polycrystalline Si plug 20 having conductivity.

Next, again, a CVD method is used to deposit a SiO ₂ film having a thickness of 0.05 to 5.0 μm, for example, 0.5 μm on the entire surface to form the second interlayer insulating film 23, and then reaches the gate lead-out wiring layer. A via hole is provided, and then a non-doped polycrystalline Si layer is deposited again by LPCVD, and then polished by CMP until the second interlayer insulating film 23 is exposed, thereby forming a polycrystalline Si plug.

  Next, after depositing an Al layer (not shown) having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer (not shown) having a thickness of 50 to 2000 nm, for example, 200 nm, by sputtering, In a nitrogen atmosphere, heat treatment is performed at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours. After replacing the doped polycrystalline Si layer with Al, the Al replacement plug 39, the Al replacement wiring layer 40, and the Al replacement gate electrode 41 are again polished by CMP until the surface of the second interlayer insulating film 23 is exposed. Form.

  As described above, in the fourth embodiment of the present invention, the gate electrode and the gate lead-out wiring layer, for which Al could not be used due to the high-temperature heat treatment accompanying the self-alignment process, are replaced with low specific resistance Al. Therefore, the operation speed of the insulated gate semiconductor device can be increased.

In this case, the gate electrode has a multilayer structure of non-doped polycrystalline Si layer / stopper / doped polycrystalline Si layer 36, and Al diffusion is blocked by the stopper, so Al substitution is non-doped polycrystalline. Since only the Si layer and the doped polycrystalline Si layer 36 are left as they are, the V _th does not fluctuate and the gate oxide film 13 and the channel region 42 are not damaged, so that the reliability is impaired. In addition, the resistance of the gate electrode and the gate lead-out wiring layer can be reduced.

Next, steps of the fifth embodiment of the present invention will be described with reference to FIG.
FIG. 6 is a cross-sectional view taken along the gate extraction electrode, and is the same as that of the fourth embodiment except for the structure of the gate insulating film and the gate electrode.
See FIG. 6. First, after an element isolation oxide film 12 is formed by selective oxidation in a predetermined region of the p-type silicon substrate 11, the exposed surface of the p-type silicon substrate 11 surrounded by the element isolation oxide film 12 is thermally oxidized to form a gate. An oxide film is formed, and then the gate oxide film is converted into the oxynitride film 43 by heat treatment in an ammonia atmosphere.
In this case, the composition of the oxynitride film 43 is such that the nitrogen content is higher toward the surface.

Next, after depositing a non-doped polycrystalline Si layer having a thickness of 10 to 1000 nm, for example, 150 nm on the entire surface, a SiO ₂ film to be the protective film 15 is deposited by CVD, and etched into a predetermined pattern to form a gate. An electrode and a gate lead-out wiring layer are formed.

Next, As is ion-implanted using the gate electrode and the protective film 15 as a mask to form n-type source / drain regions (not shown), a SiO ₂ film is deposited on the entire surface by CVD, and anisotropic etching is performed. The sidewall 16 is formed by applying.

Next, a Si ₃ N ₄ film 18 having a thickness of 10 to 100 nm serving as a stopper film at the time of etching is deposited on the entire surface by a CVD method, and then a thickness different from that of the Si ₃ N ₄ film 18 on the entire surface by the CVD method. An SiO ₂ film having a thickness of 100 to 500 nm is deposited to form an interlayer insulating film 19. Next, an opening is formed in the interlayer insulating film 19 using the Si ₃ N ₄ film 18 as an etching stopper layer, and then exposed to the Si _3. By selectively removing the N ₄ film 18, via holes reaching n-type source / drain regions (not shown) are formed.

  Next, after depositing a polycrystalline Si layer doped with impurities by LPCVD method, the polycrystalline Si plug (not shown) having conductivity is polished by CMP until the first interlayer insulating film 19 is exposed. Form.

Next, again, a CVD method is used to deposit a SiO ₂ film having a thickness of 0.05 to 5.0 μm, for example, 0.5 μm on the entire surface to form the second interlayer insulating film 23, and then reaches the gate lead-out wiring layer. A via hole is provided, and then a non-doped polycrystalline Si layer is deposited again by LPCVD, and then polished by CMP until the second interlayer insulating film 23 is exposed, thereby forming a polycrystalline Si plug.

  Next, after depositing an Al layer (not shown) having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer (not shown) having a thickness of 50 to 2000 nm, for example, 200 nm, by sputtering, Non-doped poly-silicon constituting the polycrystalline Si plug and its gate extraction electrode and gate electrode by performing heat treatment in a nitrogen atmosphere at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours. After replacing the crystalline Si layer with Al, the Al replacement plug 39 and the Al replacement wiring layer 44 are formed by polishing again until the surface of the second interlayer insulating film 23 is exposed using the CMP method.

  As described above, in the fifth embodiment of the present invention, since the oxynitride film 43 having a small Al diffusion coefficient is used as the gate insulating film, as in the fourth embodiment, the self-alignment process is performed. Since the gate electrode and the gate lead-out wiring layer that could not use Al due to the high temperature heat treatment accompanying the above can be replaced with low specific resistance Al, the operating speed of the insulated gate semiconductor device can be increased. Can do.

  In particular, in the fifth embodiment, since the entire gate electrode and the gate lead-out wiring layer are replaced with Al, the gate electrode can be used as either the n-channel IGFET or the p-channel IGFET. The constant can be greatly shortened.

  That is, in the case of a conventional Si gate IGFET, in order to construct a surface channel type IGFET which is said to be effective in suppressing the short channel effect and the hot carrier effect, it is p type for the p channel type IGFET. It was necessary to make a Si gate electrode and an n-type Si gate electrode for an n-channel IGFET, but this was not necessary when Al substitution was made, and CMOS (complementary MOSFET) In, the diode formed at the connection between the p-type Si gate electrode and the n-type Si gate electrode can be extinguished by Al substitution.

  Further, in the fifth embodiment, when forming the gate electrode, a stopper made of a Ti film and a TiN film is unnecessary, so that the manufacturing process can be shortened accordingly, and the gate can be reduced. Since the level difference caused by the structure can be reduced, the surface can be easily flattened, and the height of the lower polycrystalline Si plug can be reduced correspondingly, so that the parasitic capacitance can be reduced.

Next, with reference to FIG. 7, the process of the 6th Embodiment of this invention is demonstrated.
In addition, since it is the same as that of the above-mentioned 2nd Embodiment until Al substitution process, description of the intermediate manufacturing process is abbreviate | omitted.
As shown in FIG. 7A, after the polycrystalline Si plug 24 to be the upper plug is formed as in the second embodiment described above, Al having a thickness of 0.1 to 10 μm, for example, 2 μm, is formed by sputtering. A layer 25 and a Ti layer 26 having a thickness of 50 nm to 2000 nm, for example, 200 nm are deposited.

Next, after substituting the polycrystalline Si plug 24 with Al by performing heat treatment at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours, in a nitrogen atmosphere, Again, polishing is performed using the CMP method until the Al layer 25 has a thickness of 0.1 to 2.0 μm, for example, 0.7 μm.

  Next, a wiring layer including an Al wiring layer 46 connected to the Al replacement plug 27 by etching the remaining Al layer 25 into a predetermined pattern using a resist mask (not shown) as a mask using a normal photoetching process. Form.

  Thus, in the sixth embodiment of the present invention, since the wiring layer is formed using the Al layer 25 for Al replacement, the wiring layer film forming step becomes unnecessary, and the manufacturing process is performed. Constants can be shortened.

In the sixth embodiment, in the Al substitution step, the substituted Si is mixed into the Al layer 25, the Si content in the Al layer 25 is about 0.1 to 5%, and the electromigration resistance is high. Therefore, the wiring layer is suitable.
The Si content in the substituted Al replacement plug 27 is also about 0.1 to 5%.

  In this case, the Si content depends on the heat treatment temperature, the heat treatment time, and the absolute amount of the substituted portion, and the final Si content is 0.1 to 50% even at the end of the Si substitution region. Thus, the heat treatment time and the like may be set according to the absolute amount of the replacement part.

  The technical idea of the sixth embodiment is also applied to the above-described third embodiment, and a non-doped polycrystalline Si wiring layer is provided instead of the W wiring layer 29, A polycrystalline Si plug reaching the polycrystalline Si wiring layer may be formed at the same time as the polycrystalline Si plug 24, and the polycrystalline Si wiring layer may be replaced with Al simultaneously with the replacement of the polycrystalline Si plug 24 with Al.

Next, with reference to FIG. 8, the process of the 7th Embodiment of this invention is demonstrated.
Since the process up to the formation of the polycrystalline Si plug 24 is the same as that in the sixth embodiment, description of the intermediate manufacturing process is omitted.
As shown in FIG. 8A, after the polycrystalline Si plug 24 to be the upper plug is formed in the same manner as in the sixth embodiment, a thickness of 0.05 to 5 μm, for example, 0, is formed on the entire surface using the CVD method. the SiO ₂ film 47 of .5μm deposited, by etching the SiO ₂ film 47 by using a conventional photolithography process, after forming the wiring layer trench 48 at least polycrystalline Si plug 24 is exposed, sputtering Is used to deposit an Al layer 25 having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer 26 having a thickness of 50 to 2000 nm, for example, 200 nm.

Next, after the polycrystalline Si plug 24 is replaced with Al by performing heat treatment at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours, in a nitrogen atmosphere, Again, the Al layer 25 is polished by CMP until the surface of the SiO ₂ film 47 is exposed, thereby forming the Al wiring layer 46 embedded in the wiring layer groove 48.

As described above, in the seventh embodiment of the present invention, although the number of steps of forming the SiO ₂ film 47 is increased, the step of forming the wiring layer is not necessary and the formation of the insulating film that covers the wiring layer is performed. Since the film process and the flattening process of the insulating film are not necessary, considering the entire process, the two processes of the wiring layer film forming process and the flattening process are shortened as compared with the sixth embodiment described above. be able to.

Further, in the seventh embodiment, since the film thickness of the Al wiring layer 46 is determined by the deposition accuracy of the SiO ₂ film 47, the sixth embodiment is determined by the CMP polishing accuracy. Compared with it, it can be made uniform thickness with high accuracy.

  In the seventh embodiment as well, in the Al substitution step, the substituted Si is mixed into the Al layer 25, the Si content in the Al layer 25 is about 0.1 to 5%, and the electromigration resistance is high. Therefore, the wiring layer is suitable.

  The technical idea of the seventh embodiment is also applied to the third embodiment described above, and a non-doped polycrystalline Si wiring layer is provided in place of the W wiring layer 29. A polycrystalline Si plug reaching the polycrystalline Si wiring layer may be formed at the same time as the polycrystalline Si plug 24, and the polycrystalline Si wiring layer may be replaced with Al simultaneously with the replacement of the polycrystalline Si plug 24 with Al.

Next, with reference to FIG. 9, the process of the 8th Embodiment of this invention is demonstrated.
First, after providing an element isolation oxide film 52 surrounding an n-type region 51 provided on a semiconductor substrate, a non-doped layer having a thickness of 10 to 200 nm, for example, 50 nm is formed on the entire surface by LPCVD. After the polycrystalline Si layer is deposited, it is converted into a doped polycrystalline Si layer 53 by ion implantation of B.

  Next, a TiN film 54 having a thickness of 10 to 100 nm, for example, 20 nm, which becomes a contact metal, and a TiN film 55 having a thickness of 10 to 200 nm, for example, 50 nm, which becomes a barrier metal, are sequentially deposited on the entire surface by sputtering. The LPCVD method is used again to deposit a non-doped polycrystalline Si layer 56 having a thickness of 10 to 1000 nm, for example, 100 nm, and then etched into a predetermined pattern so as to determine the outer periphery of the base electrode.

Next, a SiO ₂ film having a thickness of 0.05 to 5 μm, for example, 0.5 μm is deposited by CVD to form a first interlayer insulating film 57, and then an n-type region for defining an internal base region By forming an opening reaching 51 and then performing heat treatment, B is diffused from doped polycrystalline Si layer 53 to form p-type external base region 58.

Next, B is ion-implanted at a low acceleration energy into the opening, and an internal base region 59 is formed by performing a heat treatment. Then, a SiO ₂ film is deposited on the entire surface by a CVD method, and anisotropic etching is performed. A sidewall 60 is formed on the side wall of the opening.

  Next, a non-doped polycrystalline Si layer having a thickness of 10 to 500 nm, for example, 50 nm is deposited on the entire surface by LPCVD, and then converted into a doped polycrystalline Si layer 61 by ion implantation of As. .

  Next, a TiN film 62 having a thickness of 10 to 100 nm, for example, 20 nm, which becomes a contact metal, and a TiN film 63 having a thickness of 10 to 200 nm, for example, 50 nm, which becomes a barrier metal, are sequentially deposited on the entire surface by sputtering. An LPCVD method is used again to deposit a non-doped polycrystalline Si layer 64 having a thickness of 10 to 1000 nm, for example, 100 nm.

Next, after etching to define the outer peripheral portion of the emitter electrode, a SiO ₂ film is deposited on the entire surface by CVD, and anisotropic etching is performed to form a sidewall 65 on the sidewall of the emitter electrode, and heat treatment is performed. As a result of diffusing As from the doped polycrystalline Si layer 61, an n ⁺ -type emitter region 66 is formed.

Next, a CVD method is used to deposit a SiO ₂ film having a thickness of 0.05 to 5 μm, for example, 0.5 μm on the entire surface to form the second interlayer insulating film 67. Then, the polycrystalline Si layer 56 and the polycrystalline film are formed. A via hole reaching the Si layer 64 is formed, and then a non-doped polycrystalline Si layer is deposited on the entire surface, and then polished by CMP until the surface of the second interlayer insulating film 67 is exposed. Crystal Si plugs 68 and 69 are formed, and then an Al layer 70 having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer 71 having a thickness of 50 to 2000 nm, for example, 200 nm are deposited by sputtering.

Next, refer to FIG. 9B. By performing heat treatment in a nitrogen atmosphere at 400 to 660 ° C., for example, 500 ° C., for 1 to 48 hours, for example, 6 hours, the polycrystalline Si plugs 68 and 69 and the polycrystals connected to them are removed. After replacing the crystalline Si layers 56 and 64 with Al, polishing is performed again using the CMP method until the surface of the second interlayer insulating film 67 is exposed, whereby Al replacement plugs 72 and 73 and Al replacement plugs are connected to the Al replacement plugs. A replacement base electrode 74 and an Al replacement emitter electrode 75 are formed.

  Thus, in the eighth embodiment of the present invention, the base electrode of the self-aligned bipolar transistor in which the electrode also serves as the solid phase diffusion source and the use of Al is impossible because of the high temperature processing step. In addition, since the emitter electrode can be composed of the replacement Al layer, the operation speed of the bipolar transistor can be improved and the power consumption can be reduced.

  In this case, it is not always necessary to replace both the emitter electrode and the base electrode with Al, and only one of them may be replaced with Al.

Next, with reference to FIGS. 10 and 11, a manufacturing process according to the ninth embodiment of the present invention will be described.
FIGS. 10B and 11 are cross-sectional views taken along the alternate long and short dash line connecting AA ′ in FIG. 10A, and portions connected by a vertical broken line are omitted.
10A and 10B. First, after depositing a polycrystalline Si layer on the silicon substrate 81 via the base insulating film 82, a doped polycrystalline Si layer is formed by ion implantation of P, and then First layer quasi-wiring layers 83 and 84 are formed by etching into a predetermined pattern.

Next, a SiO ₂ film is deposited on the entire surface to form a first interlayer insulating film 85, a contact hole 86 reaching the first quasi-wiring layer 83 is formed, and then a polycrystalline Si layer is deposited, P is ion-implanted to form a doped polycrystalline Si layer, and the second quasi-wiring layers 87 and 88 are formed by etching into a predetermined pattern.

Next, a SiO ₂ film is deposited on the entire surface to form a second interlayer insulating film 89, a contact hole reaching the second quasi-wiring layer 87 is formed, and then a polycrystalline Si layer is deposited and polished by CMP. By doing so, a polycrystalline Si plug 90 for Al substitution is formed.

Next, referring to FIG. 11C, an Al layer (not shown) having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer having a thickness of 50 to 2000 nm, for example, 200 nm, are formed on the entire surface by sputtering. The polycrystalline Si plug 90 and the second layer connected to them are subjected to heat treatment at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours in a nitrogen atmosphere. After substituting the quasi-wiring layer 87 and the first quasi-wiring layer 83 with Al, the Al-substitution plug 91 and the Al-substitution wiring are polished by polishing until the surface of the second interlayer insulating film 89 is exposed using the CMP method. Layers 92 and 93 are formed.

Next, cavities 94 and 95 are formed by removing the Al-substituted Al 91 plug 91 and Al-substituted wiring layers 92 and 93 by immersing in an etchant made of hydrochloric acid.
In this case, since the first-layer quasi-wiring layer 84 and the second-layer quasi-wiring layer 88 are not substituted with Al, a cavity is not formed by etching with hydrochloric acid.

Since the permittivity of the cavities 94 and 95 formed in this way is about 1/3 that of the SiO ₂ film, the parasitic capacitance between the remaining first-layer quasi-wiring layer 84 and the second-layer quasi-wiring layer 88 are used. The parasitic capacitance between them can be greatly reduced.

  Conventionally, an insulating film having a low dielectric constant has been developed in order to reduce parasitic capacitance. Even if such an insulating film having a low dielectric constant is used, the effect of reducing the parasitic capacitance is about several tens of percent at most. Therefore, the effect of the present invention is remarkable, and there is no problem of generation of cracks accompanying heat treatment.

  In such a removal process, the etching rate with hydrochloric acid is very high, so that the deeper portion of the Al-substituted wiring layer can be removed almost completely in a relatively short time.

  Further, in the conventional manufacturing process, a dummy wiring layer of the same layer level is formed simultaneously with a normal wiring layer in order to facilitate flattening, and the remaining dummy wiring causes a parasitic capacitance. By applying the technical idea of the ninth embodiment to the dummy wiring layer and making the first quasi-wiring layer 83 the dummy wiring layer, the parasitic capacitance can be reduced and the surface can be flattened. .

  In the description of the ninth embodiment, the wiring layers in the respective layers are formed of doped polycrystalline Si layers. However, the non-doped polycrystalline Si layers are formed and are not hollowed out. The wiring layer, that is, the first-layer quasi-wiring layer 84 and the second-layer quasi-wiring layer 88 are replaced with Al via another polycrystal Si plug, and the polycrystal Si plug is exposed in an etching process for cavitation. The surface may be covered with an etching resistant film.

  In the ninth embodiment, the cavity is formed by the wiring layer. However, the cavity is not necessarily a pure wiring layer, and the cavity is made hollow by using a polycrystalline Si plug embedded in the via hole. Is also good.

The etchant is not limited to hydrochloric acid, but may be an acid other than HF, for example, sulfuric acid, and may be an alkaline solution. In any case, SiO ₂ constituting the interlayer insulating film. Since Si ₃ N ₄ , BPSG, or SOG (spin-on-glass) is not etched, the Al-substituted portion can be efficiently removed.

Next, processes of the tenth embodiment of the present invention will be described with reference to FIGS. FIGS. 12B and 13 are cross-sectional views taken along the alternate long and short dash line connecting AA ′ in FIG. 12A, and portions connected by a vertical broken line are omitted.
12A and 12B. First, after depositing a polycrystalline Si layer on a silicon substrate 81 via a base insulating film 82, the first quasi-wiring layer 83 is formed by etching into a predetermined pattern. Form.

Next, a SiO ₂ film is deposited on the entire surface to form a first interlayer insulating film 85, a contact hole 86 reaching the first quasi-wiring layer 83 is formed, and then a polycrystalline Si layer is deposited, A second quasi-wiring layer 87 is formed by etching in a pattern substantially perpendicular to the first quasi-wiring layer 83.

Next, a SiO ₂ film is deposited on the entire surface to form a second interlayer insulating film 89, a contact hole 96 reaching the second quasi-wiring layer 87 is formed, and then a polycrystalline Si layer is deposited, A doped polycrystalline Si layer is formed by ion implantation of P, and then third layer quasi-wiring layers 97 and 98 are formed by etching into a predetermined pattern.
In FIG. 12A, for the sake of simplicity of illustration, portions other than the third quasi-wiring layer 97 in the vicinity of the contact hole 96 are omitted.

Next, after depositing a SiO ₂ film on the entire surface to form a third interlayer insulating film 99, a contact hole reaching the third quasi-wiring layer 97 is formed, and then a polycrystalline Si layer is deposited and polished by CMP. By doing so, the polycrystalline Si plug 100 for Al substitution is formed.

Next, referring to FIG. 13C, an Al layer (not shown) having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer having a thickness of 50 to 2000 nm, for example, 200 nm, are formed on the entire surface by sputtering. The polycrystalline Si plug 100 and the third layer connected to the polycrystalline Si plug 100 are subjected to heat treatment in a nitrogen atmosphere at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours. By substituting Al for the quasi-wiring layer 97, the second-layer quasi-wiring layer 87, and the first-layer quasi-wiring layer 83, by polishing until the surface of the third interlayer insulating film 99 is exposed using the CMP method, An Al replacement plug 101 and Al replacement wiring layers 92, 93, and 102 are formed.

Next, the cavities 94, 95, 103 are formed by removing the Al-substituted Al replacement plug 101 and the Al-substituted wiring layers 92, 93, 102 by immersing them in an etchant made of hydrochloric acid. Form.
In this case, since the third quasi-wiring layer 98 is not substituted with Al, it is not etched with hydrochloric acid to form a cavity.

Since the cavities 94, 95, 103 formed in this way have a dielectric constant of about 1/3 that of the SiO ₂ film, the remaining third layer quasi-wiring layer 98 and the active region provided in the silicon substrate 81, electrodes, or The parasitic capacitance generated between the wiring layer and the like can be greatly reduced.

  In the tenth embodiment, the cavities are formed in a mesh shape using two wiring layers. However, the cavities may be formed in the interlayer insulating film by only one wiring layer. In particular, a mesh-like cavity can be formed by patterning one wiring layer into a mesh.

  In the description of the tenth embodiment, the third quasi-wiring layers 97 and 98 are composed of doped polycrystalline Si layers, but they may be composed of non-doped polycrystalline Si layers. In that case, a part of the wiring layer that does not become hollow, that is, the third quasi-wiring layer 98 is replaced with Al through another polycrystalline Si plug, and in the etching process for hollowing, the polycrystalline Si The exposed surface of the plug may be covered with an etching resistant film.

  The technical idea of the tenth embodiment can be used to reduce the parasitic capacitance between the layers in the multilayer wiring structure. In this case, the technical idea of the ninth embodiment is the same as that of the ninth embodiment. Similarly, a wiring layer that is not partially hollowed may be left and used as a normal wiring layer or a resistor.

Next, with reference to FIG. 14 and FIG. 15, the process of the 11th Embodiment of this invention is demonstrated.
14 (b) and 15 (d) are cross-sectional views taken along the alternate long and short dash line connecting AA 'in FIG. 14 (a). FIGS. 14 (c) and 15 (e). And FIG.15 (f) is sectional drawing of the part along the dashed-dotted line which connects BB 'of Fig.14 (a).

14A to 14C. As in the prior art, first, an element isolation oxide film 112 is formed in a predetermined region of a p-type silicon substrate 111 by selective oxidation, and then a p-type surrounded by the element isolation oxide film 112. The exposed surface of the silicon substrate 111 is thermally oxidized to form a gate oxide film 113, and then a non-doped polycrystalline Si layer is deposited, and then P is ion-implanted to form a doped polycrystalline Si layer. Further, after depositing a SiO ₂ film to be the protective film 115 by the CVD method, the gate electrode 114 is formed by etching into a predetermined pattern.

Next, As is ion-implanted using the gate electrode 114 and the protective film 115 as a mask to form n-type source / drain regions 116, and then an insulating film 117 made of a thin SiO ₂ film is deposited on the entire surface by CVD. A polycrystalline Si sidewall 118 is formed by depositing a non-doped polycrystalline Si layer and performing anisotropic etching.

Next, using the polycrystalline Si sidewall 118 as a mask, the exposed portion of the thin insulating film 117 is removed by etching to expose the n-type source / drain regions 116, and then the entire surface of the stopper film is etched by CVD. After thickness is deposited 10~100nm the Si ₃ N ₄ film 119, and is deposited on the entire surface SiO ₂ film having a thickness of 100~500nm having different the Si ₃ N ₄ film 119 and the etching characteristics by CVD interlayer insulating made After forming the film 120, an opening 121 reaching the polycrystalline Si sidewall 118 is provided in the first interlayer insulating film 120 on the element isolation oxide film 112.

15D and 15E, a non-doped polycrystalline Si layer is deposited by LPCVD and then polished by CMP until the first interlayer insulating film 120 is exposed. A polycrystalline Si plug (not shown) is formed.

  Next, an Al layer (not shown) having a thickness of 0.1 to 10 μm, for example, 2 μm, and a Ti layer (not shown) having a thickness of 50 to 2000 nm, for example, 200 nm were deposited on the entire surface by sputtering. After that, in a nitrogen atmosphere, heat treatment is performed at 400 to 660 ° C., for example, 500 ° C. for 1 to 48 hours, for example, 6 hours to replace the polycrystalline Si plug and the polycrystalline Si sidewall 118 connected thereto with Al, Next, polishing is performed using the CMP method until the surface of the first interlayer insulating film 120 is exposed.

Next, by immersing in an etchant made of hydrochloric acid, the Al-substituted plug and Al-substituted side wall that have been replaced with Al are removed, thereby forming a cavity 122 on the side of the gate electrode.
In this case, since the gate electrode 114 is covered with the protective film 115 and the insulating film 117, the gate electrode 114 is not replaced with Al and is not etched and hollowed by hydrochloric acid.

Next, a via hole reaching the n-type source / drain region 116 is provided in the first interlayer insulating film 120, and a source / drain electrode 123 is formed by embedding Al or the like.

  Thus, in the eleventh embodiment of the present invention, since the source / drain electrodes 123 are provided on the side portions of the gate electrodes via the low dielectric constant cavities 122, the gate electrodes 114 and the source / drain electrodes are provided. As a result, the parasitic capacitance between the first and second transistors can be significantly reduced, and the operation speed of the device can be further increased.

  In the description of the eleventh embodiment, the polycrystalline Si sidewall 118 is replaced with Al and removed before forming the source / drain electrodes 123. This Al replacement and removal process is the final process. It may be performed in a process close to.

  In this case, the gate electrode or gate insulating film may be replaced with Al at the same time in the same manner as in the fourth or fifth embodiment. May be formed as a polycrystalline Si plug as in the fourth embodiment and connected to an Al replacement plug via a stopper pad.

Next, with reference to FIG.16 and FIG.18, the process of the 12th Embodiment of this invention is demonstrated. FIG. 16 is a schematic plan view of a memory cell region of a DRAM. First, doped polycrystalline Si provided on an exposed surface of a silicon substrate surrounded by an element isolation oxide film 137 via a gate insulating film. Source / drain regions 133 are formed by ion implantation using the word line 131 made of layers as a mask.

  Next, after providing a first interlayer insulating film, a via hole reaching the contact portion 134 of the source / drain region 133 is provided, and a lower plug 135 made of doped polycrystalline Si is formed in the via hole, and then a contact metal is formed. After sequentially depositing a Ti film (not shown) having a thickness of 10 to 100 nm, for example, 20 nm, and then a TiN film (not shown) having a thickness of 10 to 200 nm, for example, 50 nm serving as a barrier metal by a sputtering method. A bit line 132 connected to each lower plug is formed by depositing a non-doped polycrystalline Si layer on the entire surface and patterning it.

  Next, after providing a second interlayer insulating film, a via hole reaching the bit line 132 is formed, and the via hole is filled with an upper plug 136 made of polycrystalline Si, and then the entire surface is formed with a thickness of 0.1 by sputtering. Deposit an Al layer (not shown) of 10 to 10 μm, for example 2 μm, and a Ti layer (not shown) of 50 to 2000 nm, for example 200 nm, and then in a nitrogen atmosphere at 400 to 660 ° C., for example, The upper plug 136 and the bit line 132 connected thereto are replaced with Al by performing heat treatment at 500 ° C. for 1 to 48 hours, for example, 6 hours, and then polished by CMP until the surface of the second interlayer insulating film is exposed. To do.

In FIG. 17A, when the lower plug 135 is replaced with Al, as shown in the figure, a Ti film 140 and a barrier metal having a thickness of 10 to 100 nm, for example, 20 nm, serving as a contact metal, are formed on the surface of the via hole 139. A TiN film 141 having a thickness of 10 to 200 nm, for example, 50 nm may be provided, and the lower plug 135 may be provided simultaneously with the bit line 132. In this case, Al replacement treatment at a low temperature is required.

As in the embodiment, when the lower plug 135 is not replaced with Al, as in the third embodiment, the bit line 132 itself has a thickness of 10 to 10 as a contact metal. Non-doped with a thickness of 10 to 1000 nm, for example, 300 nm, deposited through a stopper made of a 100 nm, for example, 20 nm Ti film 140 and a barrier metal, 10 to 200 nm, for example, a 50 nm TiN film 141 The polycrystalline Si layer 142 may be used.

  When only the word line 131 or both the word line 131 and the bit line 132 are replaced with Al, when the word line 131 is replaced with Al, the word line 131 or the gate insulating film is replaced with the fourth or fifth described above. Similar to the first embodiment, an upper plug may be provided for the word line 131 to replace the word line 131 with Al.

  Further, in FIG. 16, for the sake of simplicity, the storage electrode constituting the capacitor and the plug connecting the storage electrode and the source / drain region 133 are not shown, but the plug is connected to the lower plug and the upper plug. The storage electrode and the upper plug may be replaced with Al simultaneously with replacement of the Al of the bit line 132 and the like by providing a stopper pad therebetween.

FIG. 18A schematically shows an IGFET constituting the peripheral circuit of the DRAM. For the gate electrode 143 and the lower plug 135 that are not desired to be replaced with Al, a source / drain region is shown. In 133 and the gate contact region 144, the upper pad 136 is provided on the conductive lower pad 135 via the stopper pad 145 in the form of the spacer as in the second embodiment, and only the upper pad 136 is replaced with Al. It ’s fine.

FIG. 18B shows a schematic configuration of a resistor using a part of the bit line 132, and a resistor made of a non-doped polycrystalline Si layer or a doped polycrystalline Si layer. After providing the lower plug 135 having conductivity in the contact regions 146 at both ends, the upper pad 136 may be provided via the stopper pad 145 in the form of a spacer and only the upper pad 136 may be replaced with Al.

  Thus, in the twelfth embodiment of the present invention, since at least one of the bit line 132 or the word line 131 is replaced with Al, the DRAM can be operated at a high speed. The backing contact provided in order to avoid the signal delay accompanying the high resistance of the bit line or word line made of Si becomes unnecessary.

Such Al replacement of the bit line 132 or the word line 131 becomes more effective as the degree of integration increases.
That is, the Al replacement distance is about 100 μm, but when the degree of integration is improved, not only the width of the wiring layer becomes narrower, but also the length of one continuous wiring layer becomes shorter. As a result of one cell becoming smaller, the lengths of the bit line 132 and the word line 131 are also shortened. Therefore, the resistance of the bit line 132 or the word line 131 by such Al replacement can be reduced only after 256 Mbit DRAM. Is.

  In previous generations of DRAMs, the lengths of the bit lines 132 and the word lines 131 are too long to be possible, and are only possible with the progress of generations and miniaturization.

  Further, as the resistance of the bit line 132 or the word line 131 is lowered, the thickness of the bit line 132 or the word line 131 can be reduced, and thereby, the parasitic capacitance between the adjacent bit lines 132 or between the word lines 131 can be reduced. Can be reduced.

  Further, as the resistance of the bit line 132 or the word line 131 is reduced, the number of cells that can be connected to the single bit line 132 or the word line 131 can be increased. The degree can be improved.

  In addition, by providing a stopper pad in a portion where Al substitution is not desired, such as a resistance element, Al does not diffuse, so that a circuit element having an arbitrary characteristic can be created separately by the stopper pad. .

  Although the embodiments of the present invention have been described above, the present invention can be variously modified. For example, the Ti layers 26 and 71 provided on the replacement Al layers 25 and 70 are not necessarily required. Absent.

  The polycrystalline Si plugs 20, 24, etc. in each of the embodiments described above are formed by forming a via hole in the interlayer insulating film, depositing the polycrystalline silicon film, and removing the plug embedded in the via hole by CMP. Although formed, the polycrystalline silicon film may be patterned into a columnar shape and the periphery thereof may be filled with an insulating film, and “plug” in this specification means both electrodes.

  In the step of forming the plug and the step of removing the Al layer, the CMP method is used. However, the present invention is not limited to the CMP method, and etch back by dry etching may be used.

  In the first to seventh embodiments and the eleventh embodiment, a single source / drain region is used for the sake of simplicity. However, an LDD (Lightly Doped Drain) structure is used. In this case, the LDD region is formed by ion implantation using the gate electrode and the protective film as a mask, and then the source / drain region is formed by ion implantation using the sidewall as a mask. What is necessary is just to form.

  In the first to fourth, sixth, and seventh embodiments, a stopper pad made of a Ti film and a TiN film is provided so as to be in contact with the lower polycrystalline Si plug 20. When the surface of the polycrystalline Si plug 20 is previously silicided, the Ti film 21 as the contact metal is not necessary.

  In the description of each of the above embodiments, Ti is used as the contact metal. However, the contact metal is not limited to Ti, and W, Co, Ni, Ta, or these silicides including Ti are used. be able to.

  The barrier metal is not limited to TiN, and any conductive film that can prevent Al diffusion can be used. For example, TaN, WN, SiC, or the like can be used.

  In each embodiment of the present invention, the polycrystalline Si layer for Al replacement is almost a non-doped layer. However, as in the ninth and tenth embodiments, the doped polycrystalline Si layer is made of Al. It may be replaced.

  In each embodiment of the present invention, Al is used as a replacement metal in consideration of low specific resistance characteristics and versatility, but Cu, Ag, Ru, Pt, or the like may be used. In the case of using Cu, a wiring layer having a lower specific resistance and higher electromigration resistance than the Al wiring layer can be formed.

  In the description of each embodiment of the present invention, the region to be replaced is made of polycrystalline silicon, but is not limited to polycrystalline silicon, and may be microcrystalline silicon or amorphous silicon. In some cases, single crystal silicon may be used.

In the description of each embodiment of the present invention, As is doped in the polycrystalline Si layer by ion implantation or the like in order to form a shallow diffusion region or the like, but P may be used. In addition, in order to invert the conductivity type, B may be doped, and as the protective film, a SiO ₂ film is used, but Si ₃ N ₄ may be used.

  In the description of each embodiment of the present invention, a conductor film other than polycrystalline silicon is deposited by a sputtering method. However, the present invention is not limited to the sputtering method, and a CVD method or a vapor deposition method may be used. It ’s good.

  In the description of each embodiment of the present invention, an n-channel IGFET or an npn transistor is used, but it goes without saying that the present invention is also applicable to a p-channel IGFET or a pnp transistor.

  Further, the PAS technique of the present invention is applied to various contact plugs and capacitor plugs in addition to the contact plugs in the embodiment.

It is explanatory drawing of the fundamental structure of this invention. It is explanatory drawing of the process of the 1st Embodiment of this invention. It is explanatory drawing of the 2nd Embodiment of this invention. It is explanatory drawing of the process of the 3rd Embodiment of this invention. It is explanatory drawing of the 4th Embodiment of this invention. It is explanatory drawing of the 5th Embodiment of this invention. It is explanatory drawing of the process of the 6th Embodiment of this invention. It is explanatory drawing of the process of the 7th Embodiment of this invention. It is explanatory drawing of the process of the 8th Embodiment of this invention. It is explanatory drawing of the process to the middle of the 9th Embodiment of this invention. It is explanatory drawing of the process after FIG. 10 of the 9th Embodiment of this invention. It is explanatory drawing of the process to the middle of the 10th Embodiment of this invention. It is explanatory drawing of the process after FIG. 12 of the 10th Embodiment of this invention. It is explanatory drawing of the process to the middle of the 11th Embodiment of this invention. It is explanatory drawing of the process after FIG. 14 of the 11th Embodiment of this invention. It is explanatory drawing of the 12th Embodiment of this invention. It is explanatory drawing of the modification of the 12th Embodiment of this invention. It is explanatory drawing of the peripheral circuit part of the 12th Embodiment of this invention. It is explanatory drawing of the conventional PAS process. It is explanatory drawing of the example of application of the conventional PAS technique.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Gate electrode 4 Source / drain region 5 Lower plug 6 Stopper 7 Upper plug 8 Replacement metal 9 Silicon absorber layer 10 Metal replacement plug 11 P-type silicon substrate 12 Element isolation oxide film 13 Gate oxide film 14 Gate electrode 15 Protective film 16 Side wall 17 N-type source / drain region 18 Si ₃ N ₄ film 19 First interlayer insulating film 20 Polycrystalline Si plug 21 Ti film 22 TiN film 23 Second interlayer insulating film 24 Polycrystalline Si plug 25 Al layer 26 Ti layer 27 Al replacement plug 28 W pad 29 W wiring layer 30 Al replacement plug 31 Polycrystalline Si pad 32 Polycrystalline Si wiring layer 33 Polycrystalline Si plug 34 Al replacement pad 35 Al replacement wiring layer 36 Doped polycrystalline Si layer 37 Ti film 38 TiN film 39 Al substitution Lug 40 Al replacement wiring layer 41 Al replacement gate electrode 42 Channel region 43 Oxynitride film 44 Al replacement wiring layer 45 Polycrystalline Si wiring layer 46 Al wiring layer 47 SiO ₂ film 48 Trench for wiring layer 51 N-type region 52 Element isolation Oxide film 53 Doped polycrystalline Si layer 54 Ti film 55 TiN film 56 Polycrystalline Si layer 57 First interlayer insulating film 58 External base region 59 Internal base region 60 Side wall 61 Doped polycrystalline Si layer 62 Ti film 63 TiN film 64 Multi Crystal Si layer 65 Side wall 66 Emitter region 67 Second interlayer insulating film 68 Polycrystalline Si plug 69 Polycrystalline Si plug 70 Al layer 71 Ti layer 72 Al replacement plug 73 Al replacement plug 74 Al replacement base electrode 75 Al replacement emitter electrode 81 Silicon substrate 82 Base insulating film 83 First layer quasi-wiring layer 84 First layer quasi-wiring layer 85 First interlayer insulating film 86 Contact hole 87 Second layer quasi-wiring layer 88 Second layer quasi-wiring layer 89 Second interlayer insulating film 90 Polycrystalline Si plug 91 Al substitution Plug 92 Al replacement wiring layer 93 Al replacement wiring layer 94 Cavity 95 Cavity 96 Contact hole 97 Third layer quasi wiring layer 98 Third layer quasi wiring layer 99 Third interlayer insulating film 100 Polycrystalline Si plug 101 Al replacement plug 102 Al Replacement wiring layer 103 Cavity 111 P-type silicon substrate 112 Element isolation oxide film 113 Gate oxide film 114 Gate electrode 115 Protective film 116 N-type source / drain region 117 Insulating film 118 Polycrystalline Si sidewall 119 Si ₃ N ₄ film 120 Interlayer insulation Film 121 Opening 122 Cavity 123 Source / drain electrode 131 Word line 1 2 Bit line 133 Source / drain region 134 Contact portion 135 Lower plug 136 Upper plug 137 Element isolation oxide film 138 First interlayer insulating film 139 Via hole 140 Ti film 141 TiN film 142 Polycrystalline Si layer 143 Gate electrode 144 Gate contact area 145 Stopper Pad 146 Contact region 201 Silicon substrate 202 SiO ₂ film 203 Contact hole 204 Polycrystalline Si layer 205 Polycrystalline Si plug 206 Al layer 207 Al replacement plug 211 P-type silicon substrate 212 Element isolation oxide film 213 Gate oxide film 214 Gate electrode 215 Protective film 216 Side wall 217 n-type source / drain region 218 Si ₃ N ₄ film 219 Interlayer insulating film 220 Ti film 221 TiN film 222 Polycrystalline Si plug 22 3 Al layer 224 Ti layer 225 Al replacement plug

Claims (4)

A method for manufacturing a semiconductor device, comprising: replacing a wiring layer formed of a silicon layer with a replacement metal after a heat treatment step of 400 ° C. or higher. The wiring layer composed of the silicon layer is a bit line or a word line of the dynamic random access memory, and the plug or wiring layer of the circuit element constituting the peripheral circuit of the dynamic random access memory 2. A method of manufacturing a semiconductor device according to claim 1, wherein a stopper pad is provided at an ingress portion of the replacement metal in the non-replacement portion. After replacing the silicon plug or silicon wiring layer provided on the semiconductor substrate via the insulating film with a replacement metal, at least a part or the whole of the metal replacement plug or metal replacement wiring layer replaced with metal is removed, and the cavity portion is removed. Forming a semiconductor device. 4. The semiconductor device according to claim 3, wherein the hollow portion is formed by replacing a side wall made of a silicon layer provided on a side wall of the gate electrode with a replacement metal and then removing the side wall. Production method.

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