201025401 六、發明說明： 【發明所屬之技術領域】 本發明是關於-種電㈣結構，尤指—種可提升炼_ 熔絲之電麗範圍（blowing window)的電炫絲纟士構 【先前技術】 ❿ 元 隨著半導體製程的微小化以及複雜度的提高，半導體 件也變得更容易受各式缺陷或雜質所影響，而單—金屬連 線、二極體或電晶體等的失效往往即構成_晶片的缺^。 因此為了解決這個問題，現行技術便會在積體電路中形成一 些可熔斷的連接線(fusible links) ’也就是熔絲(fuse)，以確保 積體電路的可利用性。 μ 一般而言，熔絲是連接積體電路中的冗餘電路 ® (redundancy circuit)，一旦檢測發現部分電路具有缺陷時， 這些連接線就可用於修復(repairing)或取代這些有缺陷的電 路。另外，目前的溶絲設計更可以提供程式化(pr〇gramming elements)的功能，以使各種客戶可依不同的功能設計來程式 化電路。而從操作方式來說，熔絲大致分為熱熔絲和電熔絲 (eFuse)兩種。所謂熱熔絲’是藉由一雷射切割（1· zip)的步 驟來切斷；至於電熔絲則是利用電致遷移（electr〇_migrati〇n) 的原理使熔絲出現斷路，以達到修補的效果或程式化的功 201025401 能。此外，半導體元件中之電熔絲可為例如多晶矽電熔絲 (poly efuse)、MOS 電容反溶絲（MOS capacitor anti-fuse)、擴 散電熔絲（diffusion fuse)、接觸插塞電熔絲（contact efuse)、 接觸插塞反溶絲（contact anti-fuse)等等。 典型上，電熔絲的斷開機制如第1圖所示，一電熔絲結 構1的陰極與一熔斷裝置（blowing device) 2的電晶體的没極 & 電連接，於電熔絲結構1的陽極上施加一電壓Vfs，於電晶 體的閘極施加一電壓Vg，於電晶體的汲極施加一電壓Vs， 電晶體的源極接地。電流(I)由電熔絲結構1的陽極流向電熔 絲結構1的陰極，電子流(e_)由電熔絲結構1的陰極流向電 溶絲結構1的陽極。進行炼斷時所使用的電流有一段較佳範 圍，電流太低時，所得的阻值太低，會使電性遷移不完整， 而電流太高時，會導致電熔絲熱破裂。一般，對於65nm製 程的電熔絲結構的熔斷電流為約13毫安培(mA)。其中，電 & 熔絲的熔斷位置依結構設計不同也會不同，例如接觸插塞熔 絲的斷開處則位於陰極上的接觸插塞，而多晶矽電熔絲的斷 開處則位於多晶發層。 需注意的是，習知在熔斷電熔絲結構時，通常會先設定 一預定電壓值，然後以此電壓值以上的範圍來熔斷電熔絲結 構。但以上述習知的多晶矽電熔絲結構為例，在熔斷電熔絲 時通常無法得到在預定電壓值以上且不超出預定電壓值太 4 201025401 多的可完全熔斷電熔絲結構之電壓值，使電熔絲結構所需的 斷開電壓範圍不佳（poor Mowing window) ?因此，如何改良 目前的電熔絲結構以製作出一種具有較佳斷開電壓範圍的 電熔絲結構即為現今一重要課題。 【發明内容】 因此本發明的主要目的是提供一種電熔絲結構，以改善 目前熔斷電熔絲時斷開電壓範圍不佳的缺點。 響. 本發明是揭露一種電熔絲結構，其包含一熔絲本體設於 一半導體基底表面、一陰極電性連接熔絲本體的一端、以及 一陽極電性連接熔絲本體的另一端。依據本發明之較佳實施 例，至少部分的熔絲本體上設有一壓縮應力層（compressive stress layer) ° ❿ 本發明另一實施例是揭露一種電熔絲結構，包含一半導 體基底，其上具有一電晶體區以及一電熔絲區；一電晶體設 於電晶體區之半導體基底上；一熔絲本體設於電熔絲區之半 導體基底上；一陰極與一陽極分別連接熔絲本體之兩端；以 及一壓縮應力層覆蓋電晶體區之電晶體以及電熔絲區之熔 絲本體、陰極與陽極上。 本發明主要在電熔絲結構的熔絲本體上設置一壓縮應力 201025401 層，並藉由此壓縮應力層的應力來提升炫斷電炫絲的斷開電 壓範圍（Mowing window)。依據本發明之較佳實施例，電溶 絲結構的熔絲本體與陰極、陽極均是製作於半導體基底表 面，以構成一表面型（surface type)電、溶絲結構，且雜應力 層的壓縮應力較佳介於-5GPa至〇GPa，且可完全覆蓋電熔絲 7構的熔絲本體及陽極陰極、僅覆蓋在熔絲本體或僅覆蓋在 陽極與陰極上。 ❹ 【實施方式】 清參照第2囷及第3圖，第2圖為本發明較佳實施例之 一電溶絲結構之上視圖，第3圖則為第2圖中沿著切線BB， 之截面示意圖。如圖中所示，本發明主要先提供一半導體基 底30，例如一由碳矽氧氫化物(SiCOH)、二氧化矽（si〇2)或 氮化石夕（SbN4)所構成的矽基底。然後形成由圖案化之多晶矽 ❿ 層32與矽化•金屬層34所構成的熔絲本體(fuseelement)36及 連接溶絲本體36兩端的陽極38與陰極40於半導體基底30 上°其中’圖案化之多晶矽層32可由微影暨蝕刻製程來達 成’而圖案化之矽化金屬層則可利用自行對準金屬矽化物製 程來完成。例如，可全面覆蓋一金屬層（圖未示）在多晶矽層 32上，然後進行一熱處理使金屬層與裸露的多晶矽層32反 應並濕蚀刻去除未反應的金屬層而形成矽化金屬層34。在本 實施例中’熔絲本體36與陽極38、陰極40雖由多晶矽層與 砂化金屬層兩者所構成，但不侷限於此，熔絲本體36與陽 201025401 極38、陰極40的材料又可包括任何導電材料，例如多晶矽、 金屬、或二者的組合，且可彼此相同或不同。 ❹ 隨後形成一壓縮應力層42並覆蓋在熔絲本體％及陽極 38與陰極40上。依據本發明之較佳實施例，壓縮應力層 是由一具有壓縮應力的介電材料所構成，包括氣切或氧化 矽，且壓縮應力層42的壓縮應力值是介於_5GPa至〇GPa。 壓縮材料之應力係由調整形成時的製程條件如挪声壓= 前驅物種類、流量...等而加以達成，或在形成壓^材料後利 2外的退火處理或W照射而加以達成。另需注意的是， 本實施例是將壓縮應力層42同時覆蓋 38、陰極40上，但不偈限於這個設計 36與陽極 程需求調整壓縮應力層42所覆蓋的區 明又可依照製 力層42僅覆蓋在陽極38與陰極4〇上^ ?1如可將縮應 體36上，此㈣本發明所涵蓋的範圍。或僅覆蓋在溶絲本 力層之前，更可减-層薄介電材料又’在形成壓縮應 氣化矽作為襯墊層。 然後可先覆蓋一介電層（圖未示）在 體基底上30並進行一微影暨蝕刻製程缩應力層42及半導 與壓縮應力層42 ,以於介電層與壓縮’去除部分的介電層 個接觸洞44並暴露出陽極38與陰極$力層42中形成複數 中填入由嫣、銘、銅、纽、氮化叙、 接者於接觸洞44 金屬材料，以形成複數個連接陽太或氮化鈦等所構成的 8與陰極40的導電插塞 7 201025401 46。至此即完成本發明較佳實施例之一電熔絲結構。 另需注意的是，本實施例（如第2圖）中連接陰極 電插塞46各具有-約略圓形的剖面。但不侷限於 極40圖案上設置具有不同剖面形狀的導電 插塞。舉例來說，本發明可在陰極4G的相料間區域形成 一具有橢圓形剖面的導電插塞47，如第4圖所示一 圓形之導電插塞47具有一長軸48與一短軸4广且1:’ 是約略大於各圓形導電插塞46的兩倍直經，而 ^ 略等於各圓形導電插塞46的直徑。 則約 本發明上述實施例僅於半導體基底上製作— 電溶絲&構的同時整合MOS電晶體的製程，此 ❿ 所涵蓋的範I請參照第5圖至第6 = . 乐5圖至第ό圖為 j明整口 -则電晶體與—電熔絲結構之製程示意圖。 如第5 @所示’首聽供—半導體基底5()， 曰触1 Λ。 、工疋我有 ^ Η)Μ及—電熔絲區1G4。然後進行1離@。論η) 製程’⑽電㈣區1()2及電熔㈣1()4之間的半導體基底 50中形成一例如淺溝隔離(STI)的隔離結構52，並同時在電 =區H)4的半導體基底5〇中同時形成另1溝隔離 耆全面沈積-由氧化物所構朗介㈣⑽未示)於半導體 基底50表面，並形成—由多晶㈣構成的閘極材料層（圖未 201025401 示）在介電層上。然後進行一微影暨蝕刻製程，去除部分的 閘極材料層與介電層，以於電晶體區102的半導體基底 上形成一閘極電極56與設於其下的閘極介電層58，並同時 於電熔絲區104的淺溝隔離54上形成一具有熔絲本體、、 極區塊以及陽極區塊的電熔絲圖案層60。本實施例的間极& 料層雖由多晶矽所構成，但不侷限於此，閘極材料層又可由 金屬、金屬與多晶矽上下堆疊等材料所構成，此均屬本發B ❹所涵蓋的範圍。 月 然後形成一側壁子66於電晶體區102的閘極電極％ 電熔絲圖案層60侧壁，並進行一離子佈植製程，以於、 體區102之側壁子66兩側的半導體基底50中形成一振^曰 波極區域62、64。需注意的是，本實施例是以單—側/ 66及源極/汲極區域62、64為例，但又可依製程需求柃 ⑩極電極56的侧壁上形成複數個側壁子，並可同時搭配輕^ 舉例來說，可先形成一偏位侧壁子在閘極電 的半導體^ —輕換雜離子佈植，以於偏位侧壁子兩侧 ㈣-主Γ底中形成—輕#雜&極。接著在偏位侧壁子周圍 兩二丰:壁子’並進行一重_離子佈植，以於主侧壁子 側壁子底巾减1細_域。糾，形成偏位 又=製1、輕掺雜極與源極/⑽區域的先後順序 又叮依製程需求任意調整，而不偈限於此。 201025401 然後如第6圖所示’可視製程情況進行一自行對準秒化 金屬製程，以於電熔絲圖案層60與源極/汲極區域62、64 表面形成一矽化金屬層68。矽化金屬層68可包含梦化鎮、 矽化鈦、矽化鈷、矽化鎳或上述者與其他金屬如鉑的合金， 但不限於此。至此即於電晶體區102完成一 M〇s電晶體。 接著沈積一由氧化矽或氮化矽所構成且具有壓縮應力的接 觸洞蚀刻停止層88並全面覆蓋電晶體區102的MOS電晶體 ❹及全面或部分覆蓋電熔絲區104的電熔絲圖案層6〇，然後再 沈積一介電層70於接觸洞蝕刻停止層88上。同上所述，形 成壓縮材料之前或之後尚可形成一層薄介電材料襯墊層；壓 縮材料之應力係由調整形成時的製程條件如溫度、壓力、前 驅物種類、流量...等而加以達成’或在形成壓縮材料後利用 額外的退火處理或uv照射而加以達成。隨後進行一微影暨 蚀刻製程’去除部分介電層70與接觸洞蝕刻停止層88以形 ❿成複數個接觸洞並暴露出MOS電晶體的閘極電極56頂部與 源極/汲極區域62、64及電熔絲區 104的部分矽化金屬層 68。此處應注意，在一般的邏輯電路區中具有NM〇s&pM〇s 電晶體’為了因應兩種電晶體的導電載子不同（NMOS為電 子’ PM〇S為電洞），在NMOS上可能不會覆蓋壓縮應力接 觸洞触刻停止層或覆蓋伸張應力接觸洞蝕刻停止層而在 PMC>S上覆蓋歷縮應力接腳#刻停止層。目此，本發明之 方法更可包含：在沈積壓縮應力接觸洞蝕刻停止層之前或之 後’全面覆蓋伸張應力接觸洞蝕刻停止層，並去除PMOS及 201025401 電熔絲區104上的伸張應力接觸洞蝕刻停止層。 接著填入由鎢、鋁、銅、钽、氮化钽、鈦或氮化鈦等所 構成的金屬材料於接觸洞中，以於電晶體區1〇2及電熔絲區 1〇4分別形成複數個貫穿介電層70與接觸洞蝕刻停止層88 並電性連接MOS電晶體與電熔絲圖案層6〇的導電插塞72、 74、76、78、80。然後可進行一金屬内連線製程，例如形成 ❿一金屬内連線82連接陰極上的導電插塞74與源極/汲極區域 62上的導電插塞76以及一金屬内連線84連接陽極上的導電 插塞72與周邊的邏輯電路。至此即完成本發明另一實施例 之整合性MOS電晶體與電熔絲結構。 綜上所述，本發明主要在電熔絲結構的熔絲本體上設置 一壓縮應力層，並藉由此壓縮應力層的應力來提升熔斷電熔 絲時的斷開電壓範圍（blowing window)。依據本發明之較佳 實施例，電熔絲結構的熔絲本體與陰極、陽極均是製作於半 導體基底表面’以構成一表面型（surface type)電熔絲結構， 且壓縮應力層的壓縮應力較佳介於_5GPa至OGPa，且可完全 覆蓋電熔絲結構的熔絲本體及陽極陰極、僅覆蓋在熔絲本體 或僅覆羞在陽極與陰極上。 依據本發明之另一實施例，此覆蓋於電熔絲結構表面的 壓縮應力層又可採用MOS電晶體製程中的接觸洞蝕刻侉止 201025401 層。換句話說，本發明可先於半導體基底上劃分出一電晶體 區與一電熔絲區，然後在完成MOS電晶體的製作後覆蓋一 具有壓縮應力的接觸洞蝕刻停止層在MOS電晶體與電熔絲 圖案層上。最後再覆蓋一介電層並於介電層中形成複數個連 接MOS電晶體與電熔絲的導電插塞，以完成一 MOS電晶體 與電熔絲的整合性結構。 ^ 以上所述僅為本發明之較佳實施例，凡依本發明申請專 ❹ 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知一電熔絲裝置之斷開機制。 第2圖為本發明較佳實施例之一電熔絲結構之上視圖。 第3圖為第2圖中沿著切線BB’之截面示意圖。 第4圖為本發明另一實施例之電熔絲結構之上視圖。 ❿ 第5圖至第6圖為本發明整合一 MOS電晶體與一電熔絲結 構之製程示意圖。 【主要元件符號說明】 1 電熔絲結構 2 熔斷裝置 10 多晶矽電熔絲結構 12 陽極 14 陰極 16 熔絲本體 18、20 鶴插塞 22 多晶矽層 12 201025401201025401 VI. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an electric (four) structure, and more particularly to an electric genital structure that can enhance the blowing window of a refining _ fuse [previously Technology] With the miniaturization and complexity of semiconductor processes, semiconductor devices have become more susceptible to various types of defects or impurities, while single-metal wires, diodes, or transistors have often failed. That is, it constitutes the absence of the wafer. Therefore, in order to solve this problem, the prior art forms fuse links "fuse" in the integrated circuit to ensure the availability of the integrated circuit. μ In general, a fuse is a redundant circuit that is connected to an integrated circuit. Once a circuit is found to have defects, these wires can be used to repair or replace these defective circuits. In addition, the current solution design provides pr〇gramming elements so that various customers can program the circuit according to different functions. In terms of operation mode, fuses are roughly classified into two types: thermal fuses and electric fuses (eFuse). The so-called thermal fuse ' is cut by a laser cutting (1 zip) step; as for the electric fuse, the fuse is broken by the principle of electro-migration (electr〇_migrati〇n) Reach the patched effect or stylized work 201025401 can. Further, the electric fuse in the semiconductor element may be, for example, a poly efuse, a MOS capacitor anti-fuse, a diffusion fuse, a contact plug electric fuse ( Contact efuse), contact anti-fuse, etc. Typically, the breaking mechanism of the electric fuse is as shown in Fig. 1, the cathode of an electric fuse structure 1 is electrically connected to the pole of the transistor of a blowing device 2, and the electrical fuse structure is A voltage Vfs is applied to the anode of the transistor, a voltage Vg is applied to the gate of the transistor, a voltage Vs is applied to the drain of the transistor, and the source of the transistor is grounded. The current (I) flows from the anode of the electric fuse structure 1 to the cathode of the electric fuse structure 1, and the electron flow (e_) flows from the cathode of the electric fuse structure 1 to the anode of the electrolysis filament structure 1. There is a better range of currents used in the refining. When the current is too low, the resulting resistance is too low, which will result in incomplete electrical migration. When the current is too high, the electrical fuse will thermally rupture. Typically, the fusing current for an electrical fuse structure of the 65 nm process is about 13 milliamperes (mA). Wherein, the fuse position of the electric fuse is different depending on the structural design, for example, the contact plug of the contact plug fuse is located at the contact plug on the cathode, and the disconnection of the polysilicon electric fuse is located at the polycrystal. Hair layer. It should be noted that it is conventional to first set a predetermined voltage value when fusing the electric fuse structure, and then to fuse the electric fuse structure over the range of the voltage value. However, taking the above-mentioned polycrystalline silicon electric fuse structure as an example, when the electric fuse is blown, it is generally impossible to obtain a voltage of a fully fusible electric fuse structure that is above a predetermined voltage value and does not exceed a predetermined voltage value of too much 4 201025401. The value of the electrical fuse structure is poor (poor Mowing window)? Therefore, how to improve the current electrical fuse structure to produce an electric fuse structure with a better disconnection voltage range is An important issue today. SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide an electrical fuse structure to improve the current disadvantage of a poor range of turn-off voltages when fusing electrical fuses. The present invention discloses an electrical fuse structure comprising a fuse body disposed on a surface of a semiconductor substrate, a cathode electrically connected to one end of the fuse body, and an anode electrically connected to the other end of the fuse body. According to a preferred embodiment of the present invention, at least a portion of the fuse body is provided with a compressive stress layer. 另一 Another embodiment of the present invention discloses an electrical fuse structure including a semiconductor substrate having thereon a transistor region and an electric fuse region; a transistor is disposed on the semiconductor substrate of the transistor region; a fuse body is disposed on the semiconductor substrate of the electric fuse region; and a cathode and an anode are respectively connected to the fuse body Both ends; and a compressive stress layer covers the transistor of the transistor region and the fuse body, cathode and anode of the electric fuse region. The present invention mainly provides a layer of compressive stress 201025401 on the fuse body of the electric fuse structure, and thereby increases the breaking voltage range (Mowing window) of the snaking wire by compressing the stress of the stress layer. According to a preferred embodiment of the present invention, the fuse body, the cathode and the anode of the electro-dissolved filament structure are both formed on the surface of the semiconductor substrate to form a surface type electric and lysate structure, and the compression of the impurity stress layer. The stress is preferably between -5 GPa and 〇GPa, and may completely cover the fuse body and the anode cathode of the electric fuse 7 structure, covering only the fuse body or only covering the anode and the cathode.实施 [Embodiment] Referring to Figures 2 and 3, FIG. 2 is a top view of an electrolysis wire structure according to a preferred embodiment of the present invention, and FIG. 3 is a cross-sectional line BB in FIG. Schematic diagram of the section. As shown in the figure, the present invention primarily provides a semiconductor substrate 30, such as a germanium substrate composed of carbon oxyhydroxide (SiCOH), cerium oxide (si 〇 2) or strontium nitride (SbN 4 ). Then, a fuse body 36 composed of the patterned polysilicon layer 32 and the germanium metal layer 34 and an anode 38 and a cathode 40 connected to both ends of the filament body 36 are formed on the semiconductor substrate 30. The polysilicon layer 32 can be achieved by a photolithography and etching process, and the patterned deuterated metal layer can be completed by a self-aligned metal telluride process. For example, a metal layer (not shown) may be overlaid on the polysilicon layer 32, followed by a heat treatment to react the metal layer with the exposed polysilicon layer 32 and wet etch away to remove the unreacted metal layer to form the deuterated metal layer 34. In the present embodiment, the fuse body 36 and the anode 38 and the cathode 40 are composed of both a polysilicon layer and a sanding metal layer, but are not limited thereto, and the fuse body 36 and the material of the anode 201025401 and the cathode 40 are 40. It may in turn comprise any electrically conductive material, such as polysilicon, metal, or a combination of both, and may be the same or different from each other. A compressive stress layer 42 is then formed and overlies the fuse body % and the anode 38 and cathode 40. In accordance with a preferred embodiment of the present invention, the compressive stress layer is comprised of a dielectric material having compressive stress, including gas cut or yttria, and the compressive stress layer 42 has a compressive stress value between _5 GPa and 〇GPa. The stress of the compressive material is achieved by the process conditions at the time of adjustment formation, such as the sound pressure = the type of the precursor, the flow rate, etc., or the annealing treatment or W irradiation after the formation of the pressure material. It should be noted that, in this embodiment, the compressive stress layer 42 is simultaneously covered on the 38 and the cathode 40, but is not limited to this design 36 and the anode process needs to adjust the area covered by the compressive stress layer 42 and can be in accordance with the force layer. 42 covers only the anode 38 and the cathode 4 ^1 as it can be on the condensing body 36, which (4) covers the scope of the present invention. Or only before the layer of the molten wire, it is possible to reduce the thickness of the thin dielectric material and to form the compressed gasified crucible as the backing layer. Then, a dielectric layer (not shown) may be overlaid on the bulk substrate 30 and a lithography and etching process stress reducing layer 42 and a semiconducting and compressive stress layer 42 may be applied to the dielectric layer and the compressed portion. The dielectric layer contacts the hole 44 and exposes the anode 38 and the cathode. The force layer 42 forms a plurality of metal materials filled in the contact hole 44 by 嫣, Ming, copper, New, and nitride, to form a plurality of metal materials. A conductive plug 7 201025401 46 of 8 and cathode 40 formed by cation or titanium nitride is connected. Thus, an electric fuse structure of a preferred embodiment of the present invention has been completed. It should also be noted that the connecting cathode electrical plugs 46 in this embodiment (as in Fig. 2) each have a - approximately circular cross section. However, it is not limited to the provision of conductive plugs having different cross-sectional shapes on the pole 40 pattern. For example, the present invention can form a conductive plug 47 having an elliptical cross section in the interphase region of the cathode 4G. As shown in FIG. 4, a circular conductive plug 47 has a long axis 48 and a short axis. 4 wide and 1:' is approximately twice as large as each of the circular conductive plugs 46, and is slightly equal to the diameter of each of the circular conductive plugs 46. Then, in the above embodiment of the present invention, the process of integrating the MOS transistor is performed only on the semiconductor substrate, and the method of integrating the MOS transistor is performed. Please refer to FIG. 5 to FIG. 6 for the model I covered. The first diagram is a schematic diagram of the process of the transistor and the electric fuse structure. As shown in the 5th @'s first hearing-semiconductor substrate 5 (), 曰 touch 1 Λ. I have ^ Η) Μ and - electric fuse area 1G4. Then proceed 1 away from @. An isolation structure 52 such as shallow trench isolation (STI) is formed in the semiconductor substrate 50 between the η) process '(10) electric (four) region 1 () 2 and the fused (four) 1 () 4, and simultaneously in the electric = region H) 4 The semiconductor substrate 5 is simultaneously formed with another trench isolation and is deposited entirely by an oxide (4) (10) (not shown) on the surface of the semiconductor substrate 50, and forms a gate material layer composed of polycrystalline (4) (not shown in 201025401). ) on the dielectric layer. Then, a lithography and etching process is performed to remove a portion of the gate material layer and the dielectric layer to form a gate electrode 56 and a gate dielectric layer 58 disposed thereon on the semiconductor substrate of the transistor region 102. At the same time, an electric fuse pattern layer 60 having a fuse body, a pole block and an anode block is formed on the shallow trench isolation 54 of the electric fuse region 104. The interpole & layer of the present embodiment is composed of polycrystalline germanium, but is not limited thereto. The gate material layer may be composed of materials such as metal, metal and polycrystalline germanium stacked on top of each other, which are covered by the present invention. range. A sidewall 66 is then formed on the sidewall of the gate electrode % of the transistor region 102, and an ion implantation process is performed to expose the semiconductor substrate 50 on both sides of the sidewall 66 of the body region 102. A vibrating pole region 62, 64 is formed in the middle. It should be noted that, in this embodiment, the single-side/66 and source/drain regions 62 and 64 are taken as an example, but a plurality of sidewalls may be formed on the sidewall of the 10-pole electrode 56 according to process requirements, and It can be combined with light at the same time. For example, a semiconductor device with a biased sidewall on the gate electrode can be formed first, so as to form on the two sides of the biased sidewall (four)-main bottom. Light #杂 & pole. Then, around the side wall of the eccentricity, the wall is erected and a heavy _ ion is implanted to reduce the area of the main side wall. Correction, formation of offsets ==1, lightly doped poles and source/(10) regions are sequentially adjusted according to the process requirements, and are not limited to this. 201025401 Then, a self-aligned second metal process is performed as shown in FIG. 6 to form a germanium metal layer 68 on the surface of the electric fuse pattern layer 60 and the source/drain regions 62, 64. The deuterated metal layer 68 may comprise, but is not limited to, a dream town, titanium telluride, cobalt telluride, nickel telluride or an alloy of the foregoing with other metals such as platinum. Thus, a M〇s transistor is completed in the transistor region 102. Next, a contact hole etch stop layer 88 composed of yttrium oxide or tantalum nitride and having compressive stress is deposited and completely covers the MOS transistor 电 of the transistor region 102 and the electric fuse pattern covering the electric fuse region 104 in whole or in part. The layer 6 is then deposited with a dielectric layer 70 on the contact hole etch stop layer 88. As described above, a thin dielectric material backing layer may be formed before or after the formation of the compressive material; the stress of the compressive material is determined by adjusting process conditions such as temperature, pressure, precursor type, flow rate, etc. This is achieved by the use of additional annealing or uv irradiation after the formation of the compressed material. Subsequently, a lithography and etching process is performed to remove a portion of the dielectric layer 70 and the contact hole etch stop layer 88 to form a plurality of contact holes and expose the top and source/drain regions 62 of the gate electrode 56 of the MOS transistor. And 64 and a portion of the deuterated metal layer 68 of the electrical fuse region 104. It should be noted here that in the general logic circuit area, there are NM〇s & pM〇s transistors 'in order to respond to the different conductive carriers of the two transistors (NMOS is the electron 'PM〇S is the hole), on the NMOS It may not cover the compressive stress contact hole etch stop layer or cover the tensile stress contact hole etch stop layer and cover the shrink stress pin #刻止层 on PMC>S. Therefore, the method of the present invention may further comprise: 'overlying the tensile stress contact hole etch stop layer before or after depositing the compressive stress contact hole etch stop layer, and removing the tensile stress contact hole on the PMOS and 201025401 electric fuse region 104. Etch stop layer. Then, a metal material composed of tungsten, aluminum, copper, tantalum, tantalum nitride, titanium or titanium nitride is filled in the contact hole to form the transistor region 1〇2 and the electric fuse region 1〇4, respectively. A plurality of conductive plugs 72, 74, 76, 78, 80 are formed through the dielectric layer 70 and the contact hole etch stop layer 88 and electrically connected to the MOS transistor and the EMF pattern layer 6A. A metal interconnect process can then be performed, such as forming a german metal interconnect 82 connecting the conductive plug 74 on the cathode with the conductive plug 76 on the source/drain region 62 and a metal interconnect 84 connecting the anode The upper conductive plug 72 and the peripheral logic circuit. Thus, the integrated MOS transistor and the electric fuse structure of another embodiment of the present invention are completed. In summary, the present invention mainly provides a compressive stress layer on the fuse body of the electric fuse structure, and thereby increases the breaking voltage range when the electric fuse is blown by compressing the stress of the stress layer. . According to a preferred embodiment of the present invention, the fuse body and the cathode and the anode of the electric fuse structure are both formed on the surface of the semiconductor substrate to form a surface type electric fuse structure, and the compressive stress of the compressive stress layer is formed. It is preferably between _5 GPa to OGPa and can completely cover the fuse body and the anode cathode of the electric fuse structure, covering only the fuse body or only shrugging on the anode and the cathode. According to another embodiment of the present invention, the compressive stress layer overlying the surface of the electrical fuse structure can be etched by contact holes in the MOS transistor process to terminate the 201025401 layer. In other words, the present invention can divide a transistor region and an electrical fuse region on the semiconductor substrate, and then cover the contact hole with a compressive stress to form an etch stop layer in the MOS transistor after the fabrication of the MOS transistor is completed. On the layer of electric fuse pattern. Finally, a dielectric layer is covered and a plurality of conductive plugs connecting the MOS transistor and the electric fuse are formed in the dielectric layer to complete an integrated structure of the MOS transistor and the electric fuse. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the specific scope of the invention are intended to be within the scope of the present invention. [Simple description of the drawing] Fig. 1 is a disconnection mechanism of a conventional electric fuse device. Figure 2 is a top plan view of an electrical fuse structure in accordance with a preferred embodiment of the present invention. Fig. 3 is a schematic cross-sectional view taken along line BB' in Fig. 2. Figure 4 is a top plan view of an electrical fuse structure in accordance with another embodiment of the present invention. ❿ Figs. 5 to 6 are schematic views showing the process of integrating a MOS transistor and an electric fuse structure according to the present invention. [Main component symbol description] 1 Electric fuse structure 2 Fuse device 10 Polycrystalline silicon fuse structure 12 Anode 14 Cathode 16 Fuse body 18, 20 Crane plug 22 Polycrystalline layer 12 201025401
24 矽化金屬層 30 半導體基底 32 多晶石夕層 34 矽化金屬層 36 熔絲本體 38 陽極 40 陰極 42 壓縮應力層 44 接觸洞 46 導電插塞 47 導電插塞 48 長軸 49 短軸 50 半導體基底 52、54 淺溝隔離結構 56 閘極電極 58 閘極介電層 60 電熔絲圖案層 62、64 源極/汲極區域 66 側壁子 68 石夕化金屬層 70 介電層 72、74 、76 、 78 、 80 接觸插塞 82、84 金屬内連線 88 接觸洞蝕刻停 止層 102 電晶體區 104 電熔絲區 1324 Deuterated metal layer 30 Semiconductor substrate 32 Polycrystalline layer 34 Deuterated metal layer 36 Fuse body 38 Anode 40 Cathode 42 Compressive stress layer 44 Contact hole 46 Conductive plug 47 Conductive plug 48 Long axis 49 Short axis 50 Semiconductor substrate 52 , 54 shallow trench isolation structure 56 gate electrode 58 gate dielectric layer 60 electrical fuse pattern layer 62, 64 source/drain region 66 sidewall spacer 68 Shi Xihua metal layer 70 dielectric layer 72, 74, 76, 78, 80 contact plugs 82, 84 metal interconnects 88 contact holes etch stop layer 102 transistor region 104 electric fuse region 13