JP2005191038A - Module - Google Patents

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Publication number
JP2005191038A
JP2005191038A JP2003426846A JP2003426846A JP2005191038A JP 2005191038 A JP2005191038 A JP 2005191038A JP 2003426846 A JP2003426846 A JP 2003426846A JP 2003426846 A JP2003426846 A JP 2003426846A JP 2005191038 A JP2005191038 A JP 2005191038A
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Prior art keywords
pattern
semiconductor chip
mounting
module
module according
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JP2003426846A
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Japanese (ja)
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Yoshiaki Yatani
佳明 八谷
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2003426846A priority Critical patent/JP2005191038A/en
Publication of JP2005191038A publication Critical patent/JP2005191038A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To improve the adhesiveness of a semiconductor chip to a mounting pattern and secure the heatsink property of the semiconductor chip in a module having the semiconductor chip serving as a heating source. <P>SOLUTION: The module includes a packaging substrate 1 having a packaging pattern 2, a wiring pattern 3 and a heatsink pattern 4. The packaging pattern 2 and the heatsink pattern 4 are connected via a through hole 5. The packaging pattern 2, the wiring pattern 3, the heatsink pattern 4 and the through hole 5 are formed of conductive materials 6 (for example, Cu). The semiconductor chip 9 being the heating source is connected to the packaging pattern 2 via a die bonding material 10. The through hole 5 is arranged/formed on the packaging pattern 2 of the outer periphery of the semiconductor chip 9. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、複数の半導体チップ、複数の電子部品を同一実装基板上に実装したモジュールに関する。特に、パワー半導体チップをガラスエポキシ等の熱伝導率の低い基板上に実装したモジュールにおいて、パワー半導体チップと実装基板との密着性を確保しつつ、且つパワー半導体チップからの熱を効率よく放熱させるための構造に関する。   The present invention relates to a module in which a plurality of semiconductor chips and a plurality of electronic components are mounted on the same mounting substrate. In particular, in a module in which a power semiconductor chip is mounted on a substrate having a low thermal conductivity such as glass epoxy, heat from the power semiconductor chip is efficiently radiated while ensuring adhesion between the power semiconductor chip and the mounting substrate. For the structure.

図１１に従来のモジュールの実施例を示す（例えば特許文献１参照。）。図１１においては、用途としては、マイクロプロセッサやメモリ等の半導体チップを複数個実装する場合を想定している。   FIG. 11 shows an example of a conventional module (see, for example, Patent Document 1). In FIG. 11, it is assumed that a plurality of semiconductor chips such as a microprocessor and a memory are mounted.

ガラスエポキシ基板１の主面上には複数の半導体チップ９が実装され、ガラスエポキシ基板１の主面と基板内部とに、配線層１９（電源層やグラウンド層を含む）が形成されている。半導体チップ９はワイヤボンディング或いはＴＡＢにより基板に実装され、配線層１９と接続されている。半導体チップ９が実装されている箇所には内部が金属で充填された多数のスルーホール５が形成され、スルーホール５を介して、主面と反対の主面に形成された金属膜２０が接続されている。これにより、半導体チップ９から発生した熱は半導体チップ直下の半導体チップ９が実装されている実装面に形成されたスルーホール５を介して、主面とは反対の主面に形成された金属膜２０に放熱させるというものである。
特開平５−２６７５１２号公報 A plurality of semiconductor chips 9 are mounted on the main surface of the glass epoxy substrate 1, and a wiring layer 19 (including a power supply layer and a ground layer) is formed on the main surface of the glass epoxy substrate 1 and inside the substrate. The semiconductor chip 9 is mounted on the substrate by wire bonding or TAB and connected to the wiring layer 19. A number of through-holes 5 filled with metal are formed at locations where the semiconductor chip 9 is mounted, and a metal film 20 formed on the main surface opposite to the main surface is connected through the through-holes 5. Has been. Thereby, the heat generated from the semiconductor chip 9 is transmitted through the through-hole 5 formed on the mounting surface on which the semiconductor chip 9 immediately below the semiconductor chip is mounted, and the metal film formed on the main surface opposite to the main surface. 20 to dissipate heat.
JP-A-5-267512

図１１に示す従来の実施例は以下の課題を有する。   The conventional embodiment shown in FIG. 11 has the following problems.

半導体チップを実装面に実装した場合、半導体チップ直下にスルーホールが存在することとなるため、実装面の平坦性が悪くなり、半導体チップと実装基板の実装面との密着性が悪くなる。特に、パワー半導体チップ等の発熱が大きくなるチップを使用する場合、半導体チップからの熱による応力が増大しやすく、実装基板との熱応力差も大きくなるため、半導体チップが実装基板の実装面から剥れやすく、モジュールの破壊、モジュールを使用したセットの破壊等に結びつく可能性がある。   When the semiconductor chip is mounted on the mounting surface, a through hole exists immediately below the semiconductor chip, so that the flatness of the mounting surface is deteriorated and the adhesion between the semiconductor chip and the mounting surface of the mounting substrate is deteriorated. In particular, when using a chip that generates a large amount of heat, such as a power semiconductor chip, the stress due to heat from the semiconductor chip is likely to increase, and the difference in thermal stress from the mounting substrate also increases, so the semiconductor chip is removed from the mounting surface of the mounting substrate. It is easy to peel off and may lead to the destruction of the module and the set using the module.

上記の課題を解決する方法として、半導体チップと実装基板との熱応力差を低応力タイプのダイボンド材で緩和するという方法もあるが、一般的に低応力タイプのダイボンド材は放熱性が悪くなるため、効果的な放熱とはならない。   As a method for solving the above problem, there is a method of relaxing the thermal stress difference between the semiconductor chip and the mounting substrate with a low-stress type die-bonding material, but generally a low-stress type die-bonding material has poor heat dissipation. Therefore, it is not effective heat dissipation.

本発明は上記の課題を解決するものである。   The present invention solves the above problems.

本発明のモジュールは、実装基板に導電性材料により接続され、前記実装基板に形成された配線パターンと金属製ワイヤーで接続された半導体チップを有するモジュールにおいて、前記実装基板が、回路構成部品と前記半導体チップとを実装するための実装パターンと前記配線パターンとが形成された第一の主面と、前記第一の主面と反対の面に放熱用パターンが形成された第二の主面を有し、前記実装パターンの前記半導体チップが載置されるチップ載置部の外周に前記実装パターンと前記放熱用パターンとを金属により接続する複数のスルーホールが形成されていることを特徴としており、半導体チップと実装面の密着性確保と放熱性向上を同時に実現する。   The module of the present invention is a module having a semiconductor chip connected to a mounting substrate by a conductive material, and connected to the wiring pattern formed on the mounting substrate and a metal wire. A first main surface on which a mounting pattern for mounting a semiconductor chip and the wiring pattern are formed; and a second main surface on which a heat dissipation pattern is formed on a surface opposite to the first main surface. And a plurality of through holes that connect the mounting pattern and the heat dissipation pattern with metal are formed on an outer periphery of a chip mounting portion on which the semiconductor chip of the mounting pattern is mounted. In addition, the semiconductor chip and the mounting surface can be secured at the same time and heat dissipation can be improved.

本発明のモジュールによれば、放熱性の向上が実現でき、且つモジュールの動作温度が高い場合においても高信頼性を維持することが可能となる。   According to the module of the present invention, it is possible to improve heat dissipation and maintain high reliability even when the operating temperature of the module is high.

更に、高放熱性と高信頼性を確保しつつ、ガラスエポキシ基板のような実装基板に直接半導体チップを実装することができるため、モジュールの小型化、薄型化、低価格化を実現することができ、そして合わせてセットの小型化・低価格化を実現することができる。   Furthermore, while ensuring high heat dissipation and high reliability, a semiconductor chip can be directly mounted on a mounting substrate such as a glass epoxy substrate, so that the module can be made smaller, thinner, and less expensive. In addition, the size and price of the set can be reduced.

以下、本発明の実施の形態について、図１から図１０を用いて具体的に説明する。   Hereinafter, embodiments of the present invention will be specifically described with reference to FIGS.

（実施の形態１）
図１〜図５に本発明の第１の実施形態を示す。図１（ａ）は半導体チップ９およびチップ抵抗，チップコンデンサ等の回路構成部品１１が実装されている実装基板１の実装パターン・配線パターン面（表面）を表し、図１（ｂ）は実装基板１の放熱用パターン（裏面）を表す。図２は実装基板１の表面には、実装パターン２、配線パターン３が、実装基板１の裏面には放熱用パターン４が金属等（例えばＣｕ）の導電性材料で形成されている。ここで、実装基板１には、電気的に接続が必要な箇所すなわち配線パターンの電極パッド６および実装パターンの電極パッド６とチップ載置部８以外は全てレジスト７（図２〜図５参照、図１では省略）で絶縁されている。半導体チップ９の実装パターン２は、半導体チップ９よりも十分広い面積の矩形パターンで形成されており、矩形パターンの１つのコーナ部にチップ載置部８が設けられている。チップ載置部８以外の実装パターンには、実装パターン２と裏面の放熱用パターン４を導電性材料で接続する複数のスルーホール５がチップ載置部８の２つの辺に沿った比較的近い距離に配置されており、半導体チップ載置部８にはスルーホール５は無い。複数のスルーホール５は、実装パターン２と裏面の放熱用パターン４を導電性材料で接続しており、図２（ａ），図３（ａ），図４（ａ），図５（ａ）に示すようにスルーホール５の内壁が金属で覆われて、スルーホールはレジスト７が充填されている場合と、図２（ｂ），図３（ｂ），図４（ｂ），図５（ｂ）に示すようにスルーホール５自体を完全に導電性材料で埋める場合の２つの形態がある。半導体チップ９はダイボンド材１０により半導体チップ実装部８に接続され、半導体チップ９と配線パターン３のそれぞれの電極パッド１２同士をＡｕワイヤー等の金属製ワイヤー１３等により電気的に接続されている。図２〜図５に示したとおり、半導体チップ９および回路構成部品１１が実装された後、実装基板１の実装パターン・配線パターン面（表面）側は樹脂封止１４されており、樹脂封止面積は実装基板よりわずかに内側に形成される。なお、樹脂封止１４は樹脂コート材で塗布して被覆しても良い。図３は図２からさらにモジュール全体が樹脂コート材１５で覆った場合（表面、裏面、側面全て）の断面図を示す。図４および図５は実装基板１の放熱用パターン（裏面）にヒートシンク１６を接続した場合の断面図を示し、図５は更にモールド全体を樹脂コート材１５で覆った場合の断面図を示す。図４、５中のヒートシンク１６と放熱用パターンとの接続は、ネジどめによる場合と半田付けによる場合がある。なお、図示していないがモジュールの外部出力用端子は樹脂封止１４や樹脂コート材１５で被覆されていない。 (Embodiment 1)
1 to 5 show a first embodiment of the present invention. FIG. 1A shows a mounting pattern / wiring pattern surface (front surface) of a mounting substrate 1 on which a semiconductor chip 9 and circuit components 11 such as a chip resistor and a chip capacitor are mounted, and FIG. 1 represents a heat radiation pattern (back surface). In FIG. 2, the mounting pattern 2 and the wiring pattern 3 are formed on the front surface of the mounting substrate 1, and the heat radiation pattern 4 is formed of a conductive material such as metal (for example, Cu) on the back surface of the mounting substrate 1. Here, the mounting substrate 1 has a resist 7 (see FIGS. 2 to 5) except for the portions that need to be electrically connected, that is, the electrode pads 6 of the wiring pattern and the electrode pads 6 of the mounting pattern and the chip mounting portion 8. It is insulated in FIG. The mounting pattern 2 of the semiconductor chip 9 is formed as a rectangular pattern having a sufficiently larger area than the semiconductor chip 9, and the chip mounting portion 8 is provided at one corner portion of the rectangular pattern. A plurality of through holes 5 connecting the mounting pattern 2 and the heat radiation pattern 4 on the back surface with a conductive material are relatively close to the mounting patterns other than the chip mounting portion 8 along the two sides of the chip mounting portion 8. The semiconductor chip mounting portion 8 has no through hole 5 disposed at a distance. The plurality of through holes 5 connect the mounting pattern 2 and the heat radiation pattern 4 on the back surface with a conductive material, and are shown in FIGS. 2 (a), 3 (a), 4 (a), and 5 (a). As shown in FIG. 2, the inner wall of the through hole 5 is covered with metal, and the through hole is filled with the resist 7, and FIG. 2 (b), FIG. 3 (b), FIG. 4 (b), FIG. As shown in b), there are two forms in which the through hole 5 itself is completely filled with a conductive material. The semiconductor chip 9 is connected to the semiconductor chip mounting portion 8 by a die bond material 10, and the electrode pads 12 of the semiconductor chip 9 and the wiring pattern 3 are electrically connected to each other by a metal wire 13 such as an Au wire. 2 to 5, after the semiconductor chip 9 and the circuit component 11 are mounted, the mounting pattern / wiring pattern surface (front surface) side of the mounting substrate 1 is resin-sealed 14. The area is formed slightly inside the mounting substrate. The resin seal 14 may be coated and coated with a resin coating material. FIG. 3 shows a cross-sectional view of the case where the entire module is further covered with the resin coating material 15 from FIG. 4 and 5 show cross-sectional views when the heat sink 16 is connected to the heat radiation pattern (back surface) of the mounting substrate 1, and FIG. 5 shows a cross-sectional view when the entire mold is covered with the resin coating material 15. The connection between the heat sink 16 and the heat radiation pattern in FIGS. 4 and 5 may be by screwing or by soldering. Although not shown, the external output terminals of the module are not covered with the resin seal 14 or the resin coating material 15.

第１の実施形態においては、半導体チップ実装部８にはスルーホールが無いため、半導体チップ９は平坦性良く接続され、且つ半導体チップ９からの熱は、スルーホール５により効率的に放熱することができる。   In the first embodiment, since there is no through hole in the semiconductor chip mounting portion 8, the semiconductor chip 9 is connected with good flatness, and the heat from the semiconductor chip 9 is efficiently radiated through the through hole 5. Can do.

（実施の形態２）
図６に本発明の第２の実施形態を示す。複数のスルーホール５が半導体チップ９を囲むような形状となっている以外は、基本的に図１に示す本発明の第１の実装形態と放熱効果は同じであるが、半導体チップ９を囲むようにスルーホール５の数が増えたことにより、本発明の第１の実施形態よりも効果的に実装基板１裏面の放熱用パターンへ放熱される。 (Embodiment 2)
FIG. 6 shows a second embodiment of the present invention. The heat dissipation effect is basically the same as that of the first mounting form of the present invention shown in FIG. 1 except that the plurality of through holes 5 have a shape surrounding the semiconductor chip 9, but the semiconductor chip 9 is surrounded. Thus, by increasing the number of through holes 5, heat is radiated to the heat radiation pattern on the back surface of the mounting substrate 1 more effectively than the first embodiment of the present invention.

（実施の形態３）
図７に本発明の第３の実施形態を示す。半導体チップ９のグランド電極を実装基板１の実装パターンと接続するＡｕワイヤー等の金属製ワイヤー１３の長さを短くし、且つ半導体チップ９からの熱を効率的に放熱するために、本発明の第１の実施形態における金属製ワイヤー１３がスルーホール５を跨がないようにスルーホール５を配置したもので、基本的な放熱効果は、図１に示す本発明の第１の実装形態と同じである。 (Embodiment 3)
FIG. 7 shows a third embodiment of the present invention. In order to shorten the length of the metal wire 13 such as an Au wire that connects the ground electrode of the semiconductor chip 9 to the mounting pattern of the mounting substrate 1 and to efficiently dissipate the heat from the semiconductor chip 9, The through hole 5 is arranged so that the metal wire 13 does not straddle the through hole 5 in the first embodiment, and the basic heat dissipation effect is the same as that of the first mounting form of the present invention shown in FIG. It is.

（実施の形態４）
図８に本発明の第４の実施形態を示す。複数のスルーホール５が半導体チップ９を囲むような形状となっている以外は、基本的に図７に示す本発明の第３の実装形態と放熱効果は同じであるが、半導体チップ９を囲むようにスルーホール５の数が増えたことにより、本発明の第３の実施形態よりも効果的に実装基板１裏面の放熱用パターンへ放熱される。 (Embodiment 4)
FIG. 8 shows a fourth embodiment of the present invention. Except for the shape in which the plurality of through holes 5 surround the semiconductor chip 9, the heat dissipation effect is basically the same as that of the third mounting form of the present invention shown in FIG. Thus, by increasing the number of through holes 5, heat is radiated to the heat radiation pattern on the back surface of the mounting substrate 1 more effectively than the third embodiment of the present invention.

（実施の形態５）
図９に本発明の第５の実施形態を示す。複数のスルーホール５の数を更に増やして半導体チップ９を囲むように配置した以外は、基本的に図８に示す本発明の第４の実装形態と放熱効果は同じであるが、スルーホール５の数が増えたことにより、本発明の第４の実施形態よりも効果的に実装基板１裏面の放熱用パターンへ放熱される。 (Embodiment 5)
FIG. 9 shows a fifth embodiment of the present invention. Except for further increasing the number of the plurality of through holes 5 so as to surround the semiconductor chip 9, the heat dissipation effect is basically the same as that of the fourth mounting form of the present invention shown in FIG. As a result, the heat is radiated to the heat radiation pattern on the back surface of the mounting substrate 1 more effectively than the fourth embodiment of the present invention.

（実施の形態６）
図１０に本発明の第６の実施形態を示す。図１０のように半導体チップ９を配置すれば、半導体チップ９のグランド電極と実装基板１の半導体チップ９の実装パターンを接続し、半導体チップ９のグランド電極と裏面の放熱用パターン（半導体チップ９のグランド電極と同電位）と合わせて、実装基板１に形成された回路を回路部１（図１０中の１７）と回路部２（図１０中の１８）に左右に分けることができるため、放熱効果だけではなく、配線浮遊容量による不安定動作低減やシールド効果が期待できる。 (Embodiment 6)
FIG. 10 shows a sixth embodiment of the present invention. If the semiconductor chip 9 is arranged as shown in FIG. 10, the ground electrode of the semiconductor chip 9 and the mounting pattern of the semiconductor chip 9 of the mounting substrate 1 are connected, and the ground electrode of the semiconductor chip 9 and the heat radiation pattern (semiconductor chip 9) In addition, the circuit formed on the mounting substrate 1 can be divided into a circuit part 1 (17 in FIG. 10) and a circuit part 2 (18 in FIG. 10) on the left and right. In addition to the heat dissipation effect, it can be expected to reduce unstable operation and shield effect due to wiring stray capacitance.

なお、実施の形態２から実施の形態６におけるモジュールの断面図は図２〜図５のいずれの形状でも良い。   It should be noted that the cross-sectional views of the modules in the second to sixth embodiments may be any shape shown in FIGS.

以上のように、本発明のモジュールによれば、放熱性の向上が実現でき、且つモジュールの動作温度が高い場合においても高信頼性を維持することが可能となる。   As described above, according to the module of the present invention, improvement in heat dissipation can be realized, and high reliability can be maintained even when the operating temperature of the module is high.

更に、高放熱性と高信頼性を確保しつつ、ガラスエポキシ基板のような実装基板に直接半導体チップを実装することができるため、モジュールの小型化、薄型化、低価格化を実現することができ、そして合わせてセットの小型化・低価格化を実現することができる。   Furthermore, while ensuring high heat dissipation and high reliability, a semiconductor chip can be directly mounted on a mounting substrate such as a glass epoxy substrate, so that the module can be made smaller, thinner, and less expensive. In addition, the size and price of the set can be reduced.

本発明の第１の実施形態を示す図The figure which shows the 1st Embodiment of this invention 本発明の実装基板表面側を樹脂封止した断面図Sectional view in which the mounting board surface side of the present invention is sealed with resin 本発明の実装基板表面側を樹脂封止後にモジュールを樹脂でコーティングした断面図The sectional view which coated the module with resin after resin-sealing the mounting substrate surface side of the present invention 本発明の実装基板表面側に樹脂封止、裏面側にヒートシンクを取り付けた場合の断面図Sectional view when mounting resin on the front side of the mounting board and mounting a heat sink on the back side 本発明の実装基板表面側に樹脂封止、裏面側にヒートシンクを取り付け、モジュールを樹脂でコーティングした断面図Sectional view of resin mounting on the front side of the mounting board of the present invention, heat sink attached to the back side, and module coating with resin 本発明の第２の実施形態を示す図The figure which shows the 2nd Embodiment of this invention 本発明の第３の実施形態を示す図The figure which shows the 3rd Embodiment of this invention 本発明の第４の実施形態を示す図The figure which shows the 4th Embodiment of this invention 本発明の第５の実施形態を示す図The figure which shows the 5th Embodiment of this invention 本発明の第６の実施形態を示す図The figure which shows the 6th Embodiment of this invention 従来の実施例を示す図The figure which shows the conventional Example

符号の説明Explanation of symbols

１ 実装基板
２ 実装パターン
３ 配線パターン
４ 放熱用パターン
５ スルーホール
６ 導電性材料
７ レジスト
８ 半導体チップ実装部
９ 半導体チップ
１０ ダイボンド材
１１ 電子部品
１２ 電極パッド
１３ 金属製ワイヤー
１４ 樹脂コート材
１５ 樹脂コート材
１６ ヒートシンク
１７ 回路部１
１８ 回路部２
１９ 配線層
２０ 金属膜 DESCRIPTION OF SYMBOLS 1 Mounting substrate 2 Mounting pattern 3 Wiring pattern 4 Heat radiation pattern 5 Through hole 6 Conductive material 7 Resist 8 Semiconductor chip mounting part 9 Semiconductor chip 10 Die bond material 11 Electronic component 12 Electrode pad 13 Metal wire 14 Resin coating material 15 Resin coating Material 16 Heat sink 17 Circuit part 1
18 Circuit part 2
19 Wiring layer 20 Metal film

Claims (9)

実装基板に導電性材料により接続され、前記実装基板に形成された配線パターンと金属製ワイヤーで接続された半導体チップを有するモジュールにおいて、
前記実装基板が、回路構成部品と前記半導体チップを実装するための実装パターンと前記配線パターンとが形成された第一の主面と、前記第一の主面と反対の面に放熱用パターンが形成された第二の主面を有し、
前記実装パターンの前記半導体チップが載置されるチップ載置部の外周に前記実装パターンと前記放熱用パターンとを金属により接続する複数のスルーホールが形成されていることを特徴とするモジュール。 In a module having a semiconductor chip connected to a mounting substrate by a conductive material and connected to a wiring pattern formed on the mounting substrate and a metal wire,
The mounting substrate has a first main surface on which a circuit pattern component and a mounting pattern for mounting the semiconductor chip and the wiring pattern are formed, and a heat dissipation pattern on a surface opposite to the first main surface. Having a second main surface formed;
A module, wherein a plurality of through holes for connecting the mounting pattern and the heat radiation pattern with a metal are formed on an outer periphery of a chip mounting portion on which the semiconductor chip of the mounting pattern is mounted. 前記複数のスルーホールが半導体チップの外周を囲むように形成されていることを特徴とする請求項１記載のモジュール。 2. The module according to claim 1, wherein the plurality of through holes are formed so as to surround an outer periphery of the semiconductor chip. 前記複数のスルーホールの内壁が金属で覆われていることを特徴とする請求項１記載のモジュール。 The module according to claim 1, wherein inner walls of the plurality of through holes are covered with metal. 前記複数のスルーホールが全て金属で埋められていることを特徴とする請求項１記載のモジュール。 The module according to claim 1, wherein the plurality of through holes are all filled with metal. 前記導電性材料と前記半導体チップと前記金属製ワイヤーは樹脂で覆われていることを特徴とする請求項１記載のモジュール。 The module according to claim 1, wherein the conductive material, the semiconductor chip, and the metal wire are covered with a resin. 前記半導体チップおよび前記回路構成部品が実装された前記実装基板の第一の主面が樹脂で覆われていることを特徴とする請求項１記載のモジュール。 The module according to claim 1, wherein a first main surface of the mounting substrate on which the semiconductor chip and the circuit component are mounted is covered with a resin. 前記実装基板の第二の主面に形成された放熱用パターンに放熱用部品が接続されていることを特徴とする請求項１記載のモジュール。 2. The module according to claim 1, wherein a heat dissipation component is connected to a heat dissipation pattern formed on the second main surface of the mounting substrate. 外部出力用端子と前記放熱用パターンとの接続部を除く前記放熱用部品以外は全て樹脂で被覆されていることを特徴とする請求項７記載のモジュール。 8. The module according to claim 7, wherein all of the components other than the heat radiation component except for the connection portion between the external output terminal and the heat radiation pattern are covered with resin. 外部出力用端子以外は全て樹脂で被覆されていることを特徴とする請求項１〜６記載のモジュール。 The module according to claim 1, wherein all but the external output terminals are covered with resin.
JP2003426846A 2003-12-24 2003-12-24 Module Pending JP2005191038A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015018933A (en) * 2013-07-11 2015-01-29 株式会社村田製作所 Method for manufacturing multilayer substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015018933A (en) * 2013-07-11 2015-01-29 株式会社村田製作所 Method for manufacturing multilayer substrate

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