JP2005186530A - Device and method for processing data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printer capable of outputting an image with less jitter. <P>SOLUTION: An image data is output by ASIC 14 having the circuits consisting of a discrimination circuit 23 by which the phase difference between a horizontal synchronizing signal ϕ2 and a clock signal CLK is acquired as a digital value m using the first delay circuit 21 serially connecting a delay element 31, a control circuit 25 calculating the value n which makes the sum with the value m fixed and an output circuit 24 which outputs an image signal ϕ3 delayed so that the phase difference between the horizontal synchronizing signal ϕ2 and the clock signal CLK may be compensated using the second delay circuit 22 in which the delay element 32 having been serially connected. Thereby, even if the frequency of the clock signal is not made heightened, the image data ϕ3 can be output with the resolution higher than the one of the clock signal at the timing after a fixed time from the horizontal synchronizing signal ϕ2, so that the generation of the jitter can be inhibited. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a data processing apparatus and a data processing method that operate according to a clock signal.

In a raster scan type laser printer, when a horizontal synchronization signal output from a printer engine is detected by a control system, output of an image signal for one line is started from the control system, and image recording for one line is started. The In the example shown in FIG. 5, when it is detected that the horizontal synchronization signal / HSYNC supplied from the printer engine has fallen, supply of the image signal / VOUT for one line of the image to the printer engine is started. Recording of an image for one line is started by the printer engine. Therefore, the horizontal synchronization signal also has a function as a trigger signal for determining a recording start position for starting recording of an image for one line on a medium such as a photosensitive drum.
JP-A-8-94950

  In a data processing device that operates in synchronization with a clock signal, signal sampling is also performed in synchronization with the clock signal. Accordingly, the horizontal synchronization signal is also detected in synchronization with the clock signal, and the supply of image data starts when a predetermined time has elapsed since the detection. On the other hand, the horizontal synchronization signal is originally obtained by a method such as detecting a laser reflected from a predetermined portion of the photosensitive drum, and is generated at a timing when mechanical conditions are satisfied. Then, by supplying and recording the image data after a predetermined time from the timing when the mechanical conditions are satisfied, the start positions of the image data recorded on the photosensitive drum are aligned.

  When a mechanically or analogly generated horizontal synchronization signal is sampled by a clock signal, there is a possibility that a delay of one clock at the longest occurs, and this delay becomes a deviation of the start position of image data. Therefore, as long as processing synchronized with the clock signal is performed, an error with a width corresponding to one clock occurs at the start position of the image data, and when a vertical line is printed, the vertical line becomes jagged and so-called jitter occurs. To do. If this jitter becomes clearly visible, it will lead to deterioration of print quality.

  By increasing the frequency of the clock signal, the jitter is reduced and the print quality is improved. However, increasing the frequency of the clock signal leads to an increase in power consumption, and an ASIC or LSI operating at a high frequency is expensive. Therefore, it is not economical to manufacture an ASIC that operates with a high-frequency clock signal only to suppress jitter, although it is not required for main print processing such as image processing.

  Japanese Patent Application Laid-Open No. 8-94950 discloses an image recording apparatus that prevents jitter by generating a clock signal having a high frequency by multiplying a clock signal that controls printing processing. In this image recording apparatus, a high-frequency reference clock signal having a multiplication relationship of a pixel clock signal used for modulating image data in units of pixels is generated, and this reference clock signal (normal phase reference clock signal) and this Prepare a clock signal that is out of phase with the reference clock (reverse phase reference clock signal), and select a reference clock that is closer to the start time of the image from the rise time of these reference clock signals. The reference clock signal is divided to a frequency that can be used as a pixel clock. With this method, it is possible to limit circuits that operate with a high-frequency clock signal. However, instead of having to incorporate a circuit that operates with a high-frequency clock signal, it is necessary to design the ASIC on a base that can handle a high-frequency clock signal, and to design a logic circuit in which clock signals with different frequencies are mixed. Because it is, it cannot be said that it is an economical solution.

  There is always a demand to detect a signal (trigger signal) faster than a clock signal and perform processing in synchronization with the signal in a data processing device that operates based on a clock signal, not limited to a technique for suppressing jitter of a laser printer. However, in a logic circuit that operates digitally with a clock signal, a technique for performing processing with higher resolution than the clock signal without partially using a high-frequency clock signal or a signal containing a high-frequency component similar thereto is disclosed. I can't find what I did.

  Therefore, in the present invention, without generating a high-frequency clock signal from the clock signal, a signal such as a trigger signal input from the outside is detected with a resolution higher than that of the clock signal, and processing synchronized with the detection is performed. An object of the present invention is to provide a data processing apparatus and a data processing method capable of performing the above. Then, in a laser printer, to provide a data processing device and a data processing method capable of realizing the same effect as suppressing jitter using a high-frequency clock signal without using a high-frequency clock signal partially. It is aimed.

In the present invention, the first signal supplied to the first input of the first delay circuit in which a plurality of delay elements are connected in series is sampled by the clock signal on the output side of each of the plurality of delay elements. A determination circuit for determining the maximum m-th delay element from the first input from which the first signal is detected, a control circuit for obtaining a value n that makes the sum of the values m constant, and a first delay circuit The second signal supplied to the second input of the second delay circuit in which a plurality of delay elements having the same characteristics as those connected in series is output from the output side of the nth delay element from the second input. A data processing apparatus having an output circuit is provided. In this data processing device, the deviation (phase difference) or delay between the first signal supplied to the first input and the clock signal is obtained as a numerical value m in the determination circuit. Then, in the control circuit, a value n whose sum with the value m is constant is obtained, and a second signal synchronized with the clock signal is output from the output side of the nth delay element of the output circuit. Assuming that one delay time is Td, a time Tw from when the first signal is input to the first input of the first delay circuit to when the second signal is output from the output circuit is expressed by the following equation ( 1).
Tw = (m + n) Td + Cd (1)

  Cd is the number of cycles consumed from when the first signal is detected on the output side of the maximum m-th delay element in the determination circuit until the second signal is input to the output circuit. This is the time (interval) consumed in synchronism with the clock signal regardless of the timing at which the signal is detected. The circuit is configured so that the interval Cd is constant, and the sum of the numerical value m and the numerical value n is constant, so that the accuracy of detecting the first signal is within the range of the delay time Td of one delay element. . A delay element having a delay time Td smaller than one cycle of a clock signal can be easily built in an ASIC or the like in which a logic circuit that operates with the clock signal is built. Therefore, the data processing apparatus of the present invention detects the first signal with the delay time Td having a resolution higher than that of the clock signal, and synchronizes with the first signal at a timing having a resolution higher than that of the clock signal. A signal can be output.

  Further, in the data processing device of the present invention, the deviation between the first signal and the clock signal is sampled in synchronization with the clock signal in the determination circuit, and the result is a digital value processed in synchronization with the clock signal as a value m. It becomes data. Also in the output circuit, the value n of the digital data processed in synchronization with the clock signal is used, and the second signal input in synchronization with the clock signal is output from the output of the nth delay element. Thus, a higher resolution than that of the clock signal is obtained. Therefore, in the data processing apparatus of the present invention, all signals to be controlled are synchronized with the clock signal even though the first signal can be detected and output with the higher resolution than the clock signal. The data processing apparatus can be designed and manufactured at the frequency of the clock signal. That is, the data processing device of the present invention can control input / output of data or signals at a frequency higher than that of the clock signal using a logic circuit synchronized with the clock signal. Therefore, according to the present invention, it is possible to provide an economical architecture capable of detecting a signal with a resolution higher than that of a clock signal and performing processing in synchronization therewith.

  In the present invention, a first signal is supplied to a first input of a first delay circuit in which a plurality of delay elements are connected in series, and sampling is performed by a clock signal on each output side of the plurality of delay elements. A determination step of determining the maximum m-th delay element from the first input, a step of obtaining a value n that makes the sum of the value m constant, a first signal being detected; A second signal is supplied to a second input of a second delay circuit in which a plurality of delay elements having the same characteristics as the delay circuit are connected in series, and output from the output side of the nth delay element from the second input And a data processing method having an output process. With this control method, in a low-cost data processing apparatus using the first delay circuit and the second delay circuit, a signal can be detected with a resolution higher than that of the clock signal, and processing synchronized therewith can be performed.

  The delay time due to the delay element may vary depending on the temperature. Therefore, in order to minimize the difference between the delay time Td of the delay element in the first delay circuit and the delay time Td of the delay element in the second delay circuit, the first delay circuit and the second delay circuit The delay circuit is preferably arranged in a region where the thermal influence of the data processing device and / or the power supply voltage is substantially equal. For example, it is desirable to arrange the second delay circuit in the vicinity of the first delay circuit.

  The data processing apparatus of the present invention is realized as a chip or chip set such as an electric circuit, ASIC, or LSI, a printed circuit board on which these chips are mounted, a control module or a control unit having an appropriate control function, and the like. The present invention can be applied not only to an electric circuit but also to a circuit using light or magnetism as a medium. A first supply means for supplying a horizontal synchronizing signal obtained from the printer engine as a first signal to the first input to the data processing apparatus; and an image signal supplied to the printer engine as a second signal as the second input. By providing the second supply means for supplying to the above, it can be used to suppress the above-mentioned jitter, and the time difference in which the jitter occurs can be stopped within the range of the delay time Td. In the data processing method of the present invention, the horizontal synchronization signal obtained from the printer engine is supplied as the first signal in the determination step, and the image signal supplied to the printer engine is used as the second signal in the output step. By supplying, the jitter can be reduced to the delay time Td of the delay element. Therefore, by using the data processing apparatus and the data processing method of the present invention, it is possible to provide a printer capable of printing a high-quality image from the printer engine.

  In the present invention, a deviation or delay between the first signal supplied to the first delay circuit having a plurality of delay elements and the clock signal is obtained as a numerical value m, and a value that makes the sum of the numerical value m constant. The second signal synchronized with the clock signal is output from the output side of the nth delay element of the output circuit by obtaining n. As a result, the accuracy of detecting the first signal can be increased up to the range of the delay time of one delay element, and the delay time of the delay element having a shorter cycle than the clock signal allows the first signal to be detected more accurately than the clock signal. The first signal can be detected with high resolution. Therefore, it is possible to output the second signal in synchronization with the first signal at a timing having a shorter cycle than the clock signal and higher resolution. In addition, the first signal can be detected and the second signal can be output with a resolution higher than that of the clock signal, but all of these processes can be performed in synchronization with the clock signal. All can be designed at the frequency of the clock signal. Therefore, according to the present invention, it is possible to provide an economical ASIC or LSI capable of detecting a signal with a resolution higher than that of a clock signal and performing processing in synchronization with the signal. By using such a data processing apparatus of the present invention, it is possible to provide an economical printer capable of reducing jitter to the delay time of the delay element and printing a high-quality image from the printer engine.

  Hereinafter, the present invention will be described in more detail with reference to the drawings. FIG. 1 schematically shows a printer having a data processing apparatus according to the present invention. The printer 1 is a raster scan type laser printer. The printer 1 receives printing data φ1 from the interface 3 from a peripheral device such as a digital camera or a host device such as a personal computer. The print data φ1 may be provided by a storage such as a compact flash (registered trademark) or a memory stick. In the printer 1, the print start position in the line direction (display direction or horizontal direction) is determined based on the time from the fall of the horizontal synchronization signal (/ NSYNC) φ2 output from the printer engine 4. Therefore, the image signal φ3 is output to the printer engine 4 and printing is started after a predetermined time from the detection of the horizontal synchronization signal φ2 output from the printer engine 4.

  The printer 1 has a CPU 11, a RAM 12, a ROM 13, and an ASIC 14 as control modules, and these are connected by a bus 15. The printer 1 further includes a clock generator 16 that supplies a clock signal CLK. The CPU 11, the ASIC 14, or other modules operate based on the clock signal CLK. The RAM 12 is used as a frame memory 12a in which a partial area stores an image in units of one page or the like. When the ASIC 14 having a function as an image controller receives the horizontal synchronization signal φ2 from the printer engine 4, An image signal φ3 for one line is output from the frame memory 12a to the printer engine 4, and printing in units of one line is executed.

  FIG. 2 shows a schematic configuration of the function of the ASIC 14 as an image controller. The ASIC 14 includes a first delay circuit 21 in which p (p ≧ 2) delay elements 31 are connected in series, and p delay elements 32 having the same characteristics as the first delay circuit 21 are connected in series. A wiring (first supply means) 35 for inputting the horizontal synchronization signal φ2 from the printer engine 4 as the first signal to the input (first input) 21a of the second delay circuit 22 and the first delay circuit 21. And a wiring (second supply means) 36 for inputting the image signal φ3 from the frame memory 12a to the input (second input) 22a of the second delay circuit 22. In the first delay circuit 21, the buffer gate and the wiring connected in series function as the delay element 31, and the horizontal synchronization signal φ2 supplied to the input 21a propagates through the delay element 31 connected in series. The horizontal synchronizing signal delayed by the delay time Td by the delay element appears on the output side of each delay element 31. Hereinafter, after the horizontal synchronizing signal φ2 is supplied to the input 21a, a signal obtained from the output 21b of each delay element 31 is indicated by a delay signal DLYA (k) (1 ≦ k ≦ p). Assuming that the delay time by one delay element 31 is Td, the signal DLYA (m) appearing on the output side of the mth delay element 31 is a signal delayed by m × Td from the horizontal synchronization signal φ2.

  In the second delay circuit 22, the image signal φ3 is supplied from the frame memory 12a to the input 22a and propagates through the delay elements 32 connected in series. Therefore, an image signal φ3 delayed by the delay time Td by the delay element appears on the output side of each delay element 32. Hereinafter, after the image signal φ3 is supplied to the input 22a, a signal appearing at the output 22b of each delay element 32 is indicated by a delay signal DLYB (k). Since the characteristics of each delay element 32 are made to be the same as those of the delay element 31 of the first delay circuit 21, ideally the delay time by the delay element 32 of the second delay circuit 22 is the first delay time. Similarly to the delay circuit 21 of FIG. Therefore, the signal DLYB (n) appearing on the output side of the nth delay element 32 is a signal obtained by delaying the image signal φ3 by n × Td.

  The ASIC 14 further receives any one signal from the determination circuit 23 that samples the delay signal DLYA (k) of the first delay circuit 21 by the clock signal CLK and the delay signal DLYB (k) of the second delay circuit 22. An output circuit 24 for selecting and outputting and a control circuit 25 for selecting a signal DLYB selected in the output circuit 24 are provided.

  The determination circuit 23 samples each delay signal DLYA (k) at the rising edge of the clock signal CLK. An example of the determination circuit 23 is a circuit that samples each delay signal DLYA (k) using an AND gate with the clock signal CLK and latches the result into the FF. In the first delay circuit 21, a plurality of delay signals DLYA obtained by delaying the horizontal synchronization signal φ2 by the delay time Td for each delay element are obtained. Therefore, if at least the delay time (p × Td) of the signal output from the p-th delay element 31 in the final stage is longer than one clock (one cycle of the clock signal CLK), the (p−1) -th stage in the preceding stage. By using the plurality of signals DLYA output from the delay elements 31 up to the above, it is possible to obtain a signal or timing obtained by decomposing the horizontal synchronization signal φ2 into a fraction of a clock. Therefore, by sampling the signal DLYA with the clock signal, the phase difference or deviation between the horizontal synchronization signal φ2 and the clock signal can be obtained within the resolution range of the delay time Td.

  For example, as shown in FIG. 3A, the horizontal synchronization signal φ2 (/ HSYNC) changed to the low level is input at the timing t1 preceding the clock signal CLK by the deviation (phase difference) D, It is assumed that when the sampling is performed at the timing t2 when the next clock signal CLK rises, the horizontal synchronization signal φ2 that has changed to the low level up to the delay signal DLYA (m) output from the mth delay element 31 is obtained. This means that the phase difference D between the clock signal CLK and the horizontal synchronization signal φ2 is between m × Td and (m + 1) × Td. Therefore, by determining the maximum delay signal DLYA (m) sampled by the clock signal CLK by the determination circuit 23, the clock signal CLK and the horizontal synchronizing signal φ2 are within the resolution range of the delay time Td of the analog delay element. Or the phase difference D can be determined, and the phase difference D can be output as a numerical value m which is a digital signal.

  The control circuit 25 includes a calculation unit 27 that calculates a value n that makes the sum of the value m obtained from the determination circuit 23 constant, and a buffer 28 that holds a control signal φ5 that supplies the value n to the output circuit 24. It has. The arithmetic unit 27 is given a sum K of the value m and the value n in advance, and calculates a value n that gives the sum K based on the value m corresponding to the phase difference D decoded by the determination circuit 23. .

  The output circuit 24 selects the output of the nth delay element 31 designated by the control signal φ5 and outputs it to the printer engine 4 as the image signal φ3. As shown in FIG. 3B, the image signal φ3 (/ Vx0) is input to the first delay circuit 22 from the frame memory 12a in synchronization with the clock signal CLK even if there is a certain delay time Tdw due to wiring or the like. 22a. For this reason, the image signal φ3 output from the output circuit 24 is output at the timing t4 delayed by the phase difference n × Td and the fixed delay time Tdw with respect to the rising timing t3 of the clock signal CLK, and is output to the printer engine 4. Supplied.

Therefore, the timing t4 of the image data φ3 supplied from the output circuit 24 to the printer engine 4 is the time Tw shown in the following equation (2) from the timing t1 when the horizontal synchronization signal φ2 is supplied to the first delay circuit 21. It will be delayed.
Tw = (m + n) Td + Twd + Cd (2)

  Here, the time Cd is a timing t2 when the horizontal synchronizing signal φ2 is sampled by the clock signal CLK in the first delay circuit 21, and a timing t3 when the video signal φ3 is output by the clock signal CLK to the second delay circuit 22. Is the time difference. Therefore, since the time Cd is a time consumed by a circuit synchronized with the clock signal CLK for a certain function, the number of cycles is constant. Further, as described above, the sum of the value m and the value n is controlled by the control circuit 25 so as to become the value K, and the time Twd is a delay time of the wiring, so it may be considered constant and ideally It may be understood that no delay time occurs. Therefore, the image signal φ3 is output from the output circuit 24 after a certain time Tw after the horizontal synchronization signal φ2 is input to the first delay circuit 21. The resolution of the horizontal synchronizing signal φ2 using the first delay circuit 21 is the delay time Td by the delay element 31.

  In the ASIC 14 designed to operate with the clock signal CLK, designing the delay time Td to be a fraction of the clock signal CLK or less is a normal design range and is extremely easy. Therefore, the ASIC 14 of this example can detect the horizontal synchronization signal φ2 with a resolution higher than that of the clock signal CLK, and the image data φ3 is synchronized with the horizontal synchronization signal φ2 at a certain time interval at the resolution level. It can be supplied to the printer engine 4. For this reason, in the printer 1 employing the ASIC 14 of this example, the recording start position for the horizontal synchronization signal φ2 can be controlled at a level having a higher resolution than the clock signal CLK, and the horizontal printing start position is It is possible to prevent the occurrence of jitter that is visible or can be seen at a glance.

  FIG. 4 shows an outline of processing as an image controller in the ASIC 14 using a flowchart. When the printer engine 4 generates the horizontal synchronization signal φ2 in step 41, the determination circuit 23 uses the first delay circuit 21 in step 42 to digitally calculate the phase difference between the horizontal synchronization signal φ2 and the clock signal CLK. Convert to value m. In step 43, the control circuit 25 calculates a digital value n indicating a delay time that compensates for the phase difference between the clock signal CLK and the horizontal synchronization signal φ2, and in step 44, the output circuit 24 outputs the second delay circuit 22 to the second delay circuit 22. Is used to output the image signal φ3 delayed from the clock signal CLK by the instructed time. Such control makes it possible to align the time from when the horizontal synchronizing signal φ2 is obtained until the image signal φ3 is output in units of the delay time Td of the delay elements shorter than one cycle of the clock signal CLK. .

  Further, in the ASIC 14 of the present example adopting the above control method, the timing of the horizontal synchronizing signal φ2 is detected at a frequency higher than that of the clock signal CLK, and the time is adjusted at a resolution higher than that of the clock signal CLK in synchronization therewith. The process of outputting the image data φ3 can be performed by a process synchronized with the clock signal CLK. In the determination circuit 23, the phase difference between the horizontal synchronization signal φ2 and the clock signal CLK is output as digital data, and the output circuit 24 receives data indicating a delay for compensating for the phase difference as digital data. Therefore, in the ASIC 14, signal processing can be performed at a frequency higher than that of the clock signal CLK by a logic circuit synchronized with the clock signal CLK. For this reason, the ASIC 14 does not need to be moved at a frequency higher than that of the clock signal that actually operates in whole or in part, and the ASIC 14 of this example is substantially designed only to operate at the frequency of the clock signal CLK. Signal processing with a frequency higher than that of the clock signal CLK is enabled. Therefore, the difficulty of designing and manufacturing an ASIC with a countermeasure for canceling jitter in a laser printer is drastically reduced, and an ASIC capable of high-quality printing at low cost and a printer equipped with the ASIC are provided. can do.

  In order to make the time Tw shown in the expression (2) constant with higher accuracy, the delay time Td in the first delay circuit 21 that obtains the value m and the delay time Td in the second delay circuit that uses the value n. Are preferably the same. Since the delay time Td is small compared to the clock frequency, the unevenness (jitter) of the print start position due to the difference between the delay time Td in the first delay circuit 21 and the delay time Td in the second delay circuit 22 is Compared to the jitter that appeared as an error of one clock, it is very small. Therefore, it is possible to sufficiently reduce the jitter even if the characteristics of the delay elements constituting the first delay circuit 21 and the characteristics of the delay elements constituting the second delay circuit 22 do not coincide with each other with very high accuracy. it can.

  However, the characteristics of the delay element change depending on the power supply voltage or temperature in addition to the structural difference. Therefore, even if it is very small compared with the error of one clock, if the difference in the conditions of the delay circuit as described above acts synergistically, it becomes a factor to increase the jitter. For this reason, in the ASIC 14 of the present example, the first delay circuit 21 and the second delay circuit 22 are arranged at almost adjacent positions so that the difference in delay time due to the difference in power supply voltage and the temperature difference does not occur as much as possible. I have to. Further, when the first delay circuit 21 and the second delay circuit 22 cannot be arranged close to each other due to circuit arrangement, these delays are arranged at positions where the temperatures are the same in the AISC 14, for example, symmetrical positions. It is desirable to arrange the circuits 21 and 22. Furthermore, since the delay of the wiring connecting between the delay elements 31 and 32 and the wiring leading the output from each delay element is also detected as the difference in the delay time Td, an arrangement is adopted in which the delay due to the wiring matches as much as possible. It is desirable to do.

  In the above example, the buffer gate is employed as the delay element as the analog delay element, but other known circuit configurations that generate an appropriate delay may be employed. One delay element constituted by a buffer gate and a wiring is easy to manufacture and can prevent signal attenuation when transmitting a plurality of delay elements. As a delay element forming the delay circuit of this example, Most suitable. In addition, the delay due to the wiring occupies a small proportion of the delay time, and in order to improve the accuracy of the delay time in units of each buffer gate, the wiring length is appropriately adjusted in consideration of the delay time during layout. desirable.

  In the above, an example in which image data is output in synchronization with a horizontal synchronization signal in a laser printer is shown. However, the present invention is a process that requires data to be output in a certain time in synchronization with a target signal. Can be applied not only to the printing process.

1 is a diagram showing a schematic configuration of a printer having a data processing apparatus according to the present invention. It is a figure which shows schematic structure of a function as an image controller of ASIC. FIG. 3A is a timing chart showing a state in which the phase difference between the horizontal synchronizing signal and the clock signal is detected using the first delay circuit, and FIG. 3B is a timing chart showing how the clock signal is detected using the second delay circuit. It is a timing chart which shows a mode that delayed image data is output. It is a flowchart which shows the process as an image controller in ASIC. It is a figure which shows a mode that an image signal is output after a horizontal synchronizing signal is detected.

Explanation of symbols

1 Printer 14 ASIC
21 first delay circuit 21a first input 22 second delay circuit 22a second input 23 determination circuit 24 output circuit 25 control circuit 31, 32 delay element φ2 horizontal synchronization signal (first signal)
φ3 Image signal (second signal)

Claims (7)

A first signal supplied to a first input of a first delay circuit in which a plurality of delay elements are connected in series is sampled with a clock signal on each output side of the plurality of delay elements, and the first signal is sampled. A determination circuit for determining a maximum m-th delay element from the first input, wherein:
A control circuit for obtaining a value n that makes the sum of the value m constant;
A second signal supplied to a second input of a second delay circuit in which a plurality of delay elements having the same characteristics as those of the first delay circuit are connected in series is received from the second input to the n th A data processing apparatus having an output circuit for outputting from the output side of the delay element.   2. The data processing device according to claim 1, wherein the first delay circuit and the second delay circuit are arranged in a region where the thermal effect of the data processing device and / or the power supply voltage are substantially equal.   2. The data processing apparatus according to claim 1, wherein the second delay circuit is disposed in the vicinity of the first delay circuit. The first supply means according to claim 1, wherein a first synchronizing signal is supplied to the first input as the first signal.
A data processing apparatus comprising: a second supply unit configured to supply an image signal supplied to the printer engine to the second input as the second signal.   A printer comprising the data processing apparatus according to claim 4 and the printer engine. The first signal is supplied to a first input of a first delay circuit in which a plurality of delay elements are connected in series, and sampling is performed with a clock signal on the output side of each of the plurality of delay elements. A determination step of determining a maximum m-th delay element from the first input, wherein one signal is detected;
Obtaining a value n that makes the sum of the value m constant;
A second signal is supplied to a second input of a second delay circuit in which a plurality of delay elements having the same characteristics as those of the first delay circuit are connected in series, and the nth delay from the second input A data processing method comprising: an output step of outputting from the output side of the element. In Claim 6, in the determination step, a horizontal synchronization signal obtained from a printer engine is supplied as the first signal,
A data processing method for supplying an image signal supplied to the printer engine as the second signal in the output step.

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