JP4199025B2 - Image forming apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus used for various copying machines and printers, and more particularly, an image output circuit that outputs image data phase-synchronized with a video clock, and laser control based on the image data output from the image output circuit. The present invention relates to an image forming apparatus having a laser control circuit that generates a signal and outputs the signal to a laser drive system.
[0002]
[Prior art]
Conventionally, in this type of image forming apparatus (for example, see Patent Document 1), when a photoconductor is scanned using a laser beam and image formation is performed, a laser beam detector is provided in the vicinity of the photoconductor. The detector detects the laser beam in the non-image forming area, and feeds back the detection signal to the control system, so that the detection signal is used as a synchronization signal in the sub-scanning direction.
The synchronization in the main scanning direction is performed by generating a reference clock by a crystal oscillator or the like and supplying the reference clock to each part of the control system. In particular, in an image output circuit for generating image data, A video clock is generated based on the clock, and image data is output in synchronization with the video clock, so that a laser control signal by pulse width modulation corresponding to the image data is generated in a subsequent laser control circuit, The laser light source is driven and controlled.
The image output circuit is composed of, for example, an ASIC (so-called printer ASIC), takes in image data stored in a memory or the like in advance, and this image data is video in the main scanning direction at the sub-scan synchronization timing based on the beam detection signal described above. Output at the timing synchronized with the clock.
[0003]
[Patent Document 1]
JP-A-5-344292 [0004]
[Problems to be solved by the invention]
By the way, since the image output circuit and the laser control circuit described above are both operated by a common reference clock, the operation timing on the image output circuit side and the operation timing on the laser control circuit side are basically the same. In reality, however, a slight delay occurs in the video clock due to components in the image output circuit (printer ASIC), and image data including a slight phase shift may be output.
When image data including such a phase shift is supplied, when the pulse width modulation is performed by the laser control circuit, the rising edge of the pulse is shifted due to the phase shift of the image data, leading to a subtle deterioration in image quality. There is.
For this reason, conventionally, in order to make the phase of the image data output from the image output circuit coincide with the phase of the operation clock of the laser control circuit, for example, a high-speed synchronization circuit is provided to minimize signal delay, or the printer ASIC It was handled by a method that pays attention to the timing at the time of compiling, and it was extremely complicated.
[0005]
Therefore, an object of the present invention is to realize phase alignment between the image output circuit and the laser control circuit with a simple configuration at low cost, and to design the image output circuit without strictly considering timing. An object of the present invention is to provide an image forming apparatus capable of expanding design flexibility.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention generates an image output circuit that outputs image data that is phase-synchronized with a video clock, and generates a laser control signal based on the image data output from the image output circuit. A laser control circuit for outputting, and the image output circuit selects a predetermined delay buffer by selecting a plurality of delay buffers for delaying the video clock by a plurality of delay times, and the plurality of delay buffers. A selector that generates image data based on a video clock whose phase is shifted by a delay amount and outputs the image data to the laser control circuit, and a delay setting unit that sets a delay buffer selected by the selector are provided.
[0007]
In the image forming apparatus of the present invention, when outputting image data from the image output circuit to the laser control circuit, the phase is shifted by a predetermined delay amount by selecting the delay buffer by the selector based on the setting of the delay setting unit. Since image data is generated and output using a video clock, the subtle phase difference between the image output circuit and the laser control circuit can be removed with a simple configuration, and appropriate processing on the laser control circuit side can be realized. Is possible.
Therefore, for example, phase alignment between the image output circuit and the laser control circuit can be realized with a simple configuration without providing a high-speed synchronization circuit, and image quality can be improved at low cost. In addition, the image output circuit can be designed without strictly considering the timing, and the degree of design freedom can be expanded.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of an image forming apparatus according to the present invention will be described below.
FIG. 1 is a block diagram showing a part of a control circuit of an image forming apparatus according to an embodiment of the present invention, and FIG. 2 is a configuration example of a phase alignment circuit unit of a video clock provided in the control circuit shown in FIG. It is a block diagram showing typically.
As shown in FIG. 1, the image forming apparatus of this example includes a printer ASIC 100 as an image output circuit, a horizontal synchronization IC 200 as a laser control circuit, a laser drive system 300 for controlling a laser beam, and a reference clock. And a clock generator 400 to be supplied.
[0009]
The printer ASIC 100 takes, for example, image data stored in a large-capacity memory and outputs it to the horizontal synchronization IC 200 as image data phase-synchronized with a video clock, and performs phase alignment of the image data at the final output stage. The phase matching circuit unit 110 shown in FIG. 2 is provided.
In this printer ASIC 100, line synchronization (vertical synchronization) of image data in the sub-scanning direction uses a detection signal of a laser beam from a beam detector 310 (to be described later) as a vertical synchronization signal, and based on the input timing of this detection signal. The output timing of each line data of the image is determined.
In the bit synchronization (horizontal synchronization) in the main scanning direction, a bit clock is generated based on a reference clock from the clock generation unit 400, and image data is phase-synchronized with the bit clock.
However, during this bit synchronization, there may be a bit phase shift with the horizontal synchronization IC 200 on the image data receiving side due to factors such as the circuit configuration in the printer ASIC 100. Therefore, in this example, a phase matching circuit unit 110 for phase matching of image data is provided at the final output stage of the printer ASIC 100 so as to remove subtle phase shifts. Details of the phase matching circuit unit 110 will be described later.
[0010]
The horizontal synchronization IC 200 generates a PWM (pulse width modulation) signal based on the image data input from the printer ASIC 100 and outputs it as a laser drive signal to the laser drive system 300. In the horizontal synchronization IC 200, a beam detection signal is input from a beam detector 310 arranged in the unit of the laser drive system 300, and is transferred to the printer ASIC 100 as a vertical synchronization signal.
The horizontal synchronization IC 200 is also supplied with the reference clock from the clock generation unit 400, and bit synchronization is performed based on the reference clock. However, there is a bit phase shift in the image data from the printer ASIC 100. In this case, the bit synchronization becomes unstable, and the edge position of the pulse in each line may be shifted, leading to deterioration of image quality. By preventing a subtle bit phase shift, stable bit synchronization is ensured, and a laser drive signal having an appropriate pulse edge can be generated on all lines.
[0011]
Although not shown, the laser drive system 300 includes a semiconductor laser that serves as a laser light source, and a scanning optical system that includes a polygon mirror that scans a laser beam from the semiconductor laser and forms a latent image on a photosensitive member. .
The laser driving system 300 is provided with a beam detector 310. This beam detector 310 is arranged in a non-image forming area near the photoconductor, detects a laser beam in the non-image forming area after scanning each line, and uses the detected pulse as a timing signal for vertical synchronization. IC IC 200 is supplied.
The clock generation unit 400 generates a reference clock using a crystal oscillator or the like and supplies it to each unit of the image forming apparatus.
[0012]
Next, the phase matching circuit unit 110 used in this example will be described.
As shown in FIG. 2, the phase matching circuit unit 110 of this example includes a plurality of stages (only four stages are shown in the figure) of delay buffers 111 and a selector 112 that selects the output of each delay buffer 111.
The multi-stage delay buffer 111 is obtained by sequentially connecting the output of the delay buffer 111 of the preceding stage to the input of the delay buffer 111 of the subsequent stage, and the output of each delay buffer 111 is connected to the input terminal of the selector 112. Also, image data synchronized with the video clock in the printer ASIC is input to the input of the delay buffer 111 at the foremost stage.
[0013]
Each delay buffer 111 uses, for example, a D-type flip-flop as a delay loop, and sequentially delays image data input to the foremost delay buffer 111 so that a delay corresponding to one cycle of the video clock can be performed as a whole. It is a thing. That is, when the number of delay buffers 111 is N and one period of the video clock is T, the delay amount of each delay buffer 111 is set to T / (N + 1) or a value close to T / N, so that the video clock 1 The period can be delayed in N stages, and it is possible to cope with a slight phase shift of the video clock. The image data that is not delayed is directly connected to the input terminal of the selector 112 without passing through the delay buffer 111, so that it is possible to output image data without delay.
For example, when the frequency of the video clock is 50 MHz to 60 MHz, the delay buffer 111 having a delay time of 2 nsec can be connected in eight stages.
[0014]
The selector 112 receives the delayed image data and non-delayed image data output from each delay buffer 111 described above, selects one image data from these image data, and outputs the selected image data to the horizontal synchronization IC 200. is there.
The selection of the image data in the selector 112 corresponds to the delay amount by, for example, a CPU (not shown) of the system control unit reading a delay amount setting value stored in advance in a delay amount setting register (not shown). This is executed by supplying predetermined selection instruction data to the control terminal of the selector 112 so that the image data is selected by the selector 112.
As described above, in the phase alignment circuit unit 110 of this example, the image data synchronized with the video clock by the printer ASIC 100 is delayed by the delay amount corresponding to the phase shift of the video clock, and the horizontal synchronization IC 200 in the subsequent stage is aligned. The laser control signal by PWM can be generated on the basis of the image data having no phase shift by the horizontal synchronization IC 200.
[0015]
Note that the delay amount set in the phase matching circuit unit 110 is used by calculating a delay amount necessary for phase matching by, for example, performing simulation during circuit design and predicting a bit phase shift caused by an element configuration. be able to.
Then, at the manufacturing adjustment stage of the image forming apparatus, the previously determined delay amount is written in the delay amount setting register by a predetermined operation from the operation panel, for example.
As a result, during the actual image forming operation, the system controller (such as a CPU) reads the set value of the delay amount setting register and controls the selector, so that the phase adjustment circuit unit 110 can perform bit phase alignment. become.
[0016]
As described above, in the image forming apparatus of this example, the bit phase of the image data from the printer ASIC 100 is matched with the bit phase on the laser control circuit side by the phase matching circuit unit 110 provided at the output stage of the printer ASIC 100 to the laser control circuit. It is possible to supply.
Therefore, when designing the printer ASIC 100, for example, it is possible to design without considering strict phase shift correspondence such as an image data pattern and other element configurations, and it is possible to achieve improvement in design efficiency and improvement in freedom, and high reliability image. A forming apparatus can be provided.
[0017]
In the above example, an example of an image forming apparatus in which line synchronization in the sub-scanning (vertical) direction is performed by directly detecting a laser beam in a non-image forming area has been described. The present invention can be similarly applied to a synchronous image forming apparatus.
Further, the configuration of the delay buffer can be realized other than the configuration using the flip-flop, and various forms can be adopted.
In addition, the image data output by the image forming apparatus of the present invention is not limited to the data stored in advance in the memory, and may be configured to output image data input from various external devices, communication media, and the like.
In the above example, the combination of the printer ASIC and the horizontal synchronization IC is described as the image output circuit and the laser control circuit. However, other element configurations may be used, and each circuit is mounted on the same IC chip. It may be what has been done.
[0018]
【The invention's effect】
As described above, in the image forming apparatus of the present invention, when outputting image data from the image output circuit to the laser control circuit, the delay buffer is selected by the selector based on the setting of the delay setting unit, so that a predetermined delay is achieved. Since the image data is generated and output by the video clock with the phase shifted by the amount, the subtle phase difference between the image output circuit and the laser control circuit can be removed with a simple configuration, and the proper value on the laser control circuit side can be removed. Processing can be realized.
Therefore, for example, the phase alignment between the image output circuit and the laser control circuit can be realized with a simple configuration without providing a high-speed synchronization circuit, and it is possible to improve the image quality at low cost.
Further, the image output circuit can be designed without strictly considering the timing, and the degree of freedom in design can be increased.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a part of a control circuit of an image forming apparatus according to an embodiment of the present invention.
2 is a block diagram showing an example of the configuration of a video clock phase matching circuit provided in the control circuit shown in FIG. 1;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 Printer ASIC, 110 Phase alignment circuit part, 111 Delay buffer, 112 Selector, 200 Horizontal synchronization IC, 300 Laser drive system, 310 Beam detector, 400 Clock generation part

Claims (6)

An image output circuit for outputting image data phase-synchronized with the video clock;
A laser control circuit that generates a laser control signal based on the image data output from the image output circuit and outputs the laser control signal to a laser drive system ;
A reference clock generation unit for generating a reference clock ;
The image output circuit includes:
A plurality of stages of delay buffers for delaying the video clock by a plurality of delay times;
By selecting the plurality of stages of delay buffers, a selector that generates image data based on a video clock shifted in phase by a predetermined delay amount and outputs the image data to the laser control circuit;
Have a delay setting section for setting a delay buffer selected by said selector,
The image forming apparatus, wherein the image output circuit and the laser control circuit operate based on a common reference clock from the reference clock generator.   The image forming apparatus according to claim 1, wherein the image output circuit includes an ASIC.   It has a beam detector that generates a synchronization signal in the sub-scanning direction by detecting a laser beam scanned by the laser drive system in a non-image forming region, and the image output circuit is input from the beam detector 2. The image forming apparatus according to claim 1, wherein an output timing of the image data in the sub-scanning direction is controlled based on a synchronization signal in the sub-scanning direction.   The image forming apparatus according to claim 1, wherein the delay setting unit is a register that stores selection instruction data for the selector. 2. The laser control circuit according to claim 1, wherein the laser control circuit generates a pulse width modulation signal corresponding to the image data from the image output circuit, and outputs the pulse width modulation signal to the laser drive system as a laser drive signal. Image forming apparatus. The image output circuit generates the video clock based on a reference clock supplied from the reference clock generation unit, and outputs the video clock to the laser control circuit after being delayed by the delay buffer and selector. The image forming apparatus according to claim 1.

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