JPH11216906A - Image-recording apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make utilizable high-speed multi-phase clocks of overlapping clocks, and realize fine positioning control for pixels at low cost. SOLUTION: The apparatus has a multi-phase clock generation circuit 46, a correction amount 1 memory means 60 for storing a phase difference of a specific reference clock and a clock detecting a beam detection signal first as a correction amount to correct a phase shift count from the reference clock, and a pixel clock modulation means 64 for selecting one of N multi-phase clocks as a pixel clock and outputs the pixel clock which is compressed, extended in units of 1/N clocks every time the phase is switched to an adjacent phase. During a time after the detection of beams before the start of laser modulation based on pixel data, a clock phase is switched to be selected stepwise from the reference clock phase through the pixel clock modulation means 64 on the basis of the correction amount, thereby obtaining a reference pixel clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image recording apparatus such as a direct plate making apparatus used in the printing industry such as newspapers. In particular, the present invention provides a pixel clock (video clock) in an image recording apparatus that scans a laser beam modulated from image information with an optical scanning unit including a rotating mirror, performs exposure recording on a photoconductor, and records an image.
And an image recording apparatus with improved control means.

[0002]

2. Description of the Related Art A conventional example will be described below. §1: General description of the prior art Conventionally, in an electrophotographic image recording apparatus using an optical scanning system based on a laser scan method, a laser light detector for detecting a scanning start position of laser light is provided, Image formation is performed by starting reading pixel data in response to the output of the photodetector, modulating the laser light with the pixel data and the pixel clock, and transferring the developed light to a recording medium. Since the light output and the pixel clock are not physically synchronized, the modulation start timing of the laser light fluctuates by a maximum of one pixel clock (the fluctuation of the recording start position).

Further, in the laser scanning method using a rotary polygon mirror, an image pitch is deviated due to a change in a recording end position for each surface due to an optical system surface irregularity and a uniformity of the fθ characteristic of the optical system. Also, in a device in which a plurality of recording units for each color are arranged and a transfer is performed on a recording medium to form an image in multiple colors, since the position of the laser light detector and the characteristics of the rotary polygon mirror are different for each recording unit, The color shift has a remarkable effect over the entire area from the scanning start position to the scanning end position.

[0004] For this reason, with respect to the fluctuation of the recording start position, the output of the laser beam detector is detected by a clock having a frequency N times the pixel clock, and 1 / N is used as a reference pixel clock. Or a method in which the above-described detection circuits for the number of phases are provided by using N-phase polyphase clocks, and a clock phase detected first is used as a reference clock phase. And a method of generating a pixel clock synchronized with the output of.

On the other hand, with respect to the deviation of the image pitch due to the non-uniformity of the optical system fθ characteristics, the effective scanning area of the laser beam is divided into a plurality of blocks, and the frequency of the pixel clock or the phase of the pixel clock is divided into blocks. (See Japanese Patent Application Laid-Open No. 2-282763) and a method using a mechanism for adjusting the depth and inclination of the optical system.

§2: Description of conventional pixel clock control section
.. See FIGS. 10 and 11 FIG. 10 is a block diagram of a conventional pixel clock control unit, and FIG.
1 is a timing chart of FIG. Hereinafter, FIG.
A specific example of a conventional pixel clock control unit will be described with reference to FIGS.

(1) Description of Pixel Clock Control Unit in Direct Plate Making Apparatus Conventionally, in the printing industry such as newspapers, exposure drawing by laser light modulation is performed directly on a plate material coated with a photosensitive agent.
2. Description of the Related Art A direct plate making apparatus for producing a printing plate through development and etching of a non-exposed portion has been known. Such a direct plate-making apparatus has a pixel clock control unit for controlling a pixel clock for forming an image.

In the pixel clock control unit, a printing plate prepared for each color is mounted on a rotary press for each color, and a printing plate for performing multicolor printing by overprinting has vertical and horizontal drawing dimensions and a drawing origin position. Therefore, high accuracy is required for unevenness in vertical and horizontal drawing pitches, and fine pixel positioning control (fine adjustment of pixel position) is indispensable.

Conventionally, a high-frequency clock that is N times the pixel clock is used, and the frequency division ratio of the high-frequency clock is switched for each pixel clock, so that fine pixel positioning control in 1 / N units is performed. In this case, an expensive ultra-high-speed ECL element is also used for a single-phase high-frequency clock oscillator and a pixel clock control unit for controlling the frequency division ratio of the pixel clock.

(2): Description of the Configuration of the Pixel Clock Control Unit In FIG.
L oscillator 2 high-frequency clock Φ generated by (e.g., frequency = 300MH _Z) and a laser beam detection signal outputted from the laser beam detector 3, the pixel clock control from the higher control unit (hereinafter referred to as "CPU") The pixel clock is controlled by inputting information, image data, and the like.

Reference numeral 4 denotes a horizontal synchronizing signal detecting circuit, which is an ECL.
High frequency clock Φ from oscillator 2 and laser light detector 3
The horizontal synchronization signal is detected by inputting the laser light detection signal from the controller. Reference numeral 5 denotes a pulse width setting register in which pixel clock pulse width information is set by the CPU.
Is an OR circuit (logical sum circuit).

Reference numeral 7 denotes a period counter for counting the period of the pixel clock, and reference numeral 8 denotes a pulse width setting counter for determining an exposure time per pixel. 9 is parallel /
It is a serial conversion circuit (hereinafter, referred to as a “P / S conversion circuit”), which converts image data (parallel data) transferred from the CPU into serial data. 10 is J
K is a flip-flop (hereinafter referred to as "JK-FF"), the JK-FF10 from the pixel clock Φ _X is obtained. Reference numeral 11 denotes an AND circuit (logical product circuit) for calculating the logical product of the pixel clock output from the JK-FF 10 and the image data (pixel data) output from the P / S conversion circuit 9. A modulated output is obtained.

Reference numeral 12 denotes a cycle setting register in which write correction information (correction information of a write position) is set by the CPU. 13 is a cycle setting register,
Basic cycle information is set by the CPU. 14
Is a selector, which selects and outputs the output of the cycle setting register 12 and the output of the cycle setting register 13 based on a selector switching signal from the horizontal synchronization signal detection circuit 4. 15 is an adder. Numeral 16 denotes correction information storage means for storing pixel pitch correction data from the CPU.

Reference numeral 17 denotes a pixel clock number setting register for setting pixel pitch correction start information from the CPU. Reference numeral 18 denotes a pixel clock number setting register.
This is for setting laser modulation start information from the CPU. Reference numeral 19 denotes a pixel clock number setting register, which is a CPU.
To set the laser modulation end information. 20
Is a pixel clock counting counter, which is synchronized with a beam synchronization signal output from the horizontal synchronization signal detection circuit 4,
Is, the number of pixel clock [Phi _X output from the JK-FF10.

Reference numeral 21 denotes a comparison circuit, which outputs the pixel clock number setting register 17 and the pixel clock counter 20.
Are compared. 22 is a comparison circuit,
The output of the pixel clock number setting register 18 and the output of the pixel clock counter 20 are compared. A comparison circuit 23 compares the output of the pixel clock number setting register 19 with the output of the pixel clock counter 20.

Reference numerals 24 and 25 denote set / reset flip-flops (hereinafter, referred to as "FF"). The FF2
4 is set by the output of the comparison circuit 21 (output of the comparison result) and is reset by the output of the comparison circuit 23 to output a correction data reading start signal. (EN terminal input signal)
It is assumed that. The FF 25 is set by the output of the comparison circuit 22 and is reset by the output of the comparison circuit 23 to output an image data read start signal. This output is output to the enable input of the P / S conversion circuit 9 (input signal of the EN terminal). ).

(3) Description of Operation of Pixel Clock Control Unit The operation of the pixel clock control unit 1 will be described below with reference to FIGS. Note that in FIG. 11, a is E
The high-frequency clock Φ output from the CL oscillator 2, b indicates the output (CY) of the period counter 7, c indicates the output (CY) of the pulse width setting counter 8, and d indicates the pixel clock Φ _X output from the JK-FF 10. .

Prior to the start of image data drawing, pixel clock pulse width information, write-out correction information, basic period information, pixel pitch correction data, pixel pitch correction start information,
Pixel clock control information such as laser modulation start information and laser modulation end information is set in each register by the CPU.

That is, pixel clock pulse width information is set in the pulse width setting register 5, writing correction information (writing position correction information) is set in the cycle setting register 12, and basic cycle information is set in the cycle setting register 13. The pixel pitch correction data is set in the correction information storage means 16, the pixel pitch correction start information is set in the pixel clock number setting register 17, the laser modulation start information is set in the pixel clock number setting register 18, and the laser modulation end information is set. This is set in the pixel clock number setting register 19.

The horizontal synchronization signal detection circuit 4 captures the rising edge of the beam detection signal from the laser light detector 3 and synchronizes with a high frequency clock Φ whose frequency is N times (N: an arbitrary integer) to perform beam synchronization. Signal (BDSYNC)
It outputs a period counter load signal B and a selector switching signal C.

[0021] The beam synchronous signal (BDSYNC) b is input to the pixel clock count counter 20, a signal for starting the counting of the pixel clock [Phi _X. The cycle counter load signal B is sent to the cycle counter 7 via the OR circuit 6.
, And becomes a load signal of the counter. The selector switching signal C is input as a select signal of the selector 14, and the output of the period setting registers 12 and 13 is switched by this signal.

The cycle counter 7 is changed to the counter cycle by the cycle setting register 12 only at the rising edge of the beam detection signal by the load signal and the selector switching signal. Thus, movement in 1 / N pixel units becomes possible.

For each count-up signal (CY) of the cycle counter 7 itself, a value obtained by adding the compression and decompression instruction values read from the correction information storage means 16 to the value of the cycle setting register 13 which is the basic cycle is used. Written to the cycle counter 7. The cycle of the pixel clock repeatedly increases and decreases +0, +1 and -1 in accordance with the compression instruction value and the expansion instruction value, and optimizes the pixel position in 1 / N pixel units.

The value of the pulse width setting counter 8 is written to the pulse width setting counter 8 for determining the exposure time per pixel for each count-up signal (CY) of the period counter 7.

The count-up signal (CY) of the cycle counter 7 and the count-up signal (CY) of the pulse width setting counter 8 are connected to the J and K inputs of the subsequent JK-FF 10, respectively. on in the count-up signal of the period counter 7 (CY), and outputs a pixel clock signal [Phi _X which turns off the count-up signal of the pulse width setting counter 8 (CY). The pixel clock signal Φ _X is sent to the pixel clock counter 20.

Receiving the beam synchronizing signal from the horizontal synchronizing signal detecting circuit 4, the pixel clock counting counter 20 starts counting the pixel clock signal Φ _X , and the count value is calculated by the comparing circuits 21, 22, and 23. The values of the number setting registers 17, 18, and 19 are compared for each pixel clock.

The FFs 24 and 25 at the subsequent stage include comparison circuits 21 and 2
3 is set by the coincidence output, and is reset by the non-coincidence output of the comparison circuit 23. The FF 24 outputs a pixel pitch correction data read start signal in a period up to the value set in the pixel clock number setting registers 17 to 19, and the FF 25 outputs a pixel data in a period up to the value set in the pixel clock number setting registers 18 to 19. Output a read start signal.

[0028]: receiving a read start signal of the pixel pitch correction data, converts the correction data acquisition to N pixels comprised correction information storage unit 16 in the shift register at every clock, the serial data in synchronization with the pixel clock [Phi _X Then, it is input to the adder 15 as a compression instruction and an expansion instruction signal, and controls the value of the cycle counter 7.

Receiving the image data read start signal, the correction data is taken into a P / S conversion circuit (parallel / serial conversion circuit) 9 composed of a shift register every N pixel clocks, and serially synchronized with the pixel clock. The data is converted into data, and a laser modulation output is obtained through an AND circuit (logical product circuit) 11 with the pixel clock.

[0030]

The above-mentioned prior art has the following problems. There are many known examples of methods for synchronizing the output of the laser light detector with the pixel clock, and correcting the bias of the pixel pitch due to the characteristics of the optical scanning system by increasing or decreasing the cycle of the pixel clock. In devices with relatively slow periods, each could be an effective approach.

However, as the speed and resolution have been increased and the diversification of printing (color, underprinting, etc.) has progressed,
And fast pixel clock frequency exceeds 300MH _Z, in order to realize a pixel clock fine adjustment function for each pixel, it is necessary to clear all of the following conditions.

Synchronizing the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. : Variation in the mounting position of the laser light detector is 1 / N
Correct in pixel units.

Correcting the variation between the recording units in the mounting position of the laser light detector in units of 1 / N pixels. : Correcting an image shift due to characteristics of the optical scanning system (surface tilt, fθ characteristics, mirror rotation speed, focal depth) in 1 / N pixel units for each pixel.

The compression / expansion of the print width in 1 / N pixel units. : To be able to respond to a high-speed pixel clock. The correction unit is desirably no more than the toner particles (6 to 8 μm). For example, when the resolution is 400 dpi, the size of one pixel is equal to or less than the diameter of 62 μm. ÷ 12 = 5.2 <Toner particles are satisfied. In the pixel clock frequency 26MH _Z, N
= If you have a 12, the basic clock frequency is 312MH _Z
If a high-speed logic element (e.g., ECL LSI) operable on a computer is used, the above conditions (1) to (4) can be satisfied, but it becomes very expensive.

Although the conventional PLL system can cope with the above-mentioned speedup, the remaining items (,...)
Can not respond. Further, the prior art using the multi-phase clock system (see Japanese Patent Application Laid-Open No. 2-282763) is a technology based on a low-speed multi-phase clock in which the clocks do not overlap, and can satisfy the above conditions. Was not.

The present invention solves such a conventional problem and makes it possible to use a high-speed multi-phase clock in which respective clocks are overlapped to satisfy all of the above conditions. It is another object of the present invention to be able to sufficiently cope with diversification and to realize an inexpensive and stable image recording apparatus.

[0037]

Means for Solving the Problems The present invention has the following constitution in order to achieve the above object. (1): Equipped with an optical scanning unit that scans laser light and a laser light detector that detects the scanning start position of laser light and outputs a beam detection signal, and modulates using pixel data (image data) and a pixel clock. A multi-phase clock generating means for generating a multi-phase clock for determining a modulation cycle of pixel data in an image recording apparatus for recording an image by exposing and recording on a photoreceptor by scanning the laser beam thus obtained; A phase difference between a specific reference clock phase of the phase clocks and a clock phase in which a beam detection signal is first detected is defined as a phase shift number from the reference clock, and the first phase shift number is stored as a correction amount. Correction amount storage means, and selecting one of the N multi-phase clocks as a pixel clock;
And a pixel clock modulating means for outputting a compressed / expanded pixel clock in units of 1 / N clock every time switching to an adjacent phase is performed, wherein the beam detection signal is sampled and the first clock detection is performed. Is used as a reference pixel clock, and during a period from the beam detection to the start of laser modulation by pixel data, a clock phase is stepped from a reference clock phase through the pixel clock modulation means based on the correction amount. By switching the selection, the reference pixel clock is obtained.

(2): In the image recording apparatus of (1),
As a correction amount for performing fine adjustment of the recording start position to start laser modulation by pixel data from the beam detection,
A second correction amount storage unit for storing a phase difference from a specific reference clock as a phase shift number, wherein the second correction amount is stored during a period from the beam detection to the start of laser modulation based on pixel data. Based on the correction amount stored in the amount storage unit, the recording start position is switched stepwise from the clock phase detected first through the pixel clock modulation unit to the clock phase corresponding to the correction amount. To 1 /
Adjustment is possible in N pixel units.

(3): In the image recording apparatus of (2),
One is stored as a compression amount and the other is stored as an expansion amount so that the polarity of the correction amount of the first correction amount storage unit and the polarity of the correction amount of the second correction amount storage unit are opposite.

(4): In the image recording apparatus of (2),
The correction amounts are read from the first and second correction amount storage units at the same timing in synchronization with the pixel clock, and one of the correction amounts is sent to the pixel clock modulation unit as a compression instruction and the other correction amount is an expansion instruction. The pixel clock modulating means is provided with an exclusive OR circuit, and the exclusive OR circuit takes an exclusive OR of the compression instruction and the decompression instruction, and generates a pixel clock according to the result. Modulation was performed.

(5): In the image recording apparatus of (2),
Correction information storage means for storing pixel pitch correction data for instructing a dynamic correction of an individual pixel pitch in an effective scanning area of laser light; and correction information storage means after completion of pixel clock modulation by the pixel clock modulation means. Correction data reading means for reading out the correction data in synchronization with a pixel clock, and inputting the pixel pitch correction data read from the correction information storage means by the correction data reading means to the pixel clock modulation means, The pixel clock modulation is performed in the effective scanning area of the laser beam based on the pitch correction data, and the laser modulation based on the pixel data is performed in a part of the effective scanning area.

(Operation) The operation of the present invention based on the above configuration will be described with reference to FIG. (a): Operation of the above (1) The multi-phase clock generating means generates a multi-phase clock in which respective clocks are overlapped, and the first correction amount storage means generates the multi-phase clock by the multi-phase clock generating means. A phase difference between a specific reference clock phase of the multiphase clocks and a clock phase in which a beam detection signal is first detected is set as a phase shift number from the reference clock, and the phase shift number is stored as a correction amount.

The pixel clock modulating means selects one of the N multi-phase clocks generated by the multi-phase clock generating means as a pixel clock, and in units of 1 / N clock each time a transition to an adjacent phase is made. And outputs the compressed and expanded pixel clock.

Thus, the beam phase is sampled and the clock phase in which the beam detection signal is first detected is used as a reference pixel clock. In this case, during the period from the beam detection to the start of laser modulation by the pixel data, the selection of the clock phase is switched stepwise from the reference clock phase via the pixel clock modulation means based on the correction amount. Is obtained.

This makes it possible to use a high-speed multi-phase clock in which the respective clocks overlap, thereby realizing a high-speed pixel clock and a pixel clock fine adjustment function for each pixel clock. Further, the output of the laser light detector and the pixel clock can be synchronized in units of 1 / N (N: an arbitrary integer) pixels. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording.

(B): Operation of the above (2) The second correction amount storage means stores a specific amount as a correction amount for performing fine adjustment of the recording start position at which laser modulation is started by pixel data from beam detection. The phase difference from the reference clock is stored as a phase shift number. Then, during the period from the beam detection to the start of the laser modulation based on the pixel data, based on the correction amount stored in the second correction amount storage unit, the clock phase detected first through the pixel clock modulation unit is used. The recording start position is adjusted in 1 / N pixel units by switching stepwise to a clock phase corresponding to the correction amount.

This makes it possible to respond to a high-speed pixel clock, and synchronize the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. Further, it is possible to correct the image shift due to the characteristics of the optical scanning system in units of 1 / N pixel for each pixel. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording.

(C): Operation of the above (3) When the correction amounts are stored in the first and second correction amount storage means, the correction amount of the first correction amount storage means and the second correction amount storage means One is stored as the compression amount and the other is stored as the expansion amount so that the polarities of the correction amounts are opposite.

This makes it possible to respond to a high-speed pixel clock, and synchronize the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. Further, it is possible to correct the image shift due to the characteristics of the optical scanning system in units of 1 / N pixel for each pixel. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording.

(D): Operation of the above (4) When the pixel clock is modulated by the pixel clock modulating means,
The correction amounts are read out from the first and second correction amount storage units at the same timing in synchronization with the pixel clock, and one of the correction amounts is sent to the pixel clock modulation unit as a compression instruction and the other correction amount is an expansion instruction. In the pixel clock modulating means, an exclusive OR circuit takes an exclusive OR of the compression instruction and the decompression instruction, and modulates the pixel clock according to the result.

This makes it possible to cope with a high-speed pixel clock, and synchronize the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. Further, it is possible to correct the image shift due to the characteristics of the optical scanning system in units of 1 / N pixel for each pixel. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording.

(E): Operation of the above (5) The correction information storage means stores pixel pitch correction data for instructing dynamic correction of individual pixel pitches in the effective scanning area of the laser beam. Further, the correction data reading means includes:
After the modulation of the pixel clock by the pixel clock modulation means, the correction data in the correction information storage means is read out in synchronization with the pixel clock.

Then, the pixel pitch correction data read from the correction information storage means by the correction data reading means is input to the pixel clock modulation means, and the pixel clock modulation is performed within the effective scanning area of the laser beam based on the pixel pitch correction data. I do. Further, laser modulation based on pixel data is performed in a part of the effective scanning area.

This makes it possible to respond to a high-speed pixel clock, and synchronize the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. Further, it is possible to correct the image shift due to the characteristics of the optical scanning system in units of 1 / N pixel for each pixel. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording.

[0055]

Embodiments of the present invention will be described below in detail with reference to the drawings. §1: Description of Image Recording Apparatus—See FIG. 1 FIG. 1 is an explanatory diagram of the image recording apparatus. Hereinafter, an example of the image recording apparatus will be described with reference to FIG.

(1): Description of Configuration of Image Recording Apparatus This image recording apparatus includes a hopper 31 for storing an unprinted print medium and a stacker 32 for storing a printed print medium. Image recording unit 35 for each color for recording an image for each color on a medium
38, a fixing unit 40 for performing a fixing process on the recorded print medium, an endless belt 33 for conveying the print medium, and an endless belt including a motor, a gear, and the like for driving the endless belt 33. Driving means (not shown),
A roller (not shown) for conveying the recording medium is provided.

In this case, four (Y) (yellow), M (magenta), C (cyan) and K (black) are stored in the image recording apparatus.
Image recording units 35, 36, 37, and 38 are provided, and from the upstream to the downstream along a paper moving path on the upper side of the belt defined between the rollers constituting the driving means of the endless belt 33. Tandem configuration in which Y, M, C, and K are arranged in series.

The image recording units 35, 36, 37,
Reference numeral 38 uses a yellow toner component (Y), a magenta toner component (M), a cyan toner component (C), and a black (black) toner component (K) as developers. Therefore, the image recording units 35 to 38 transfer and record the yellow toner image, the magenta toner image, the cyan toner image, and the black toner image on the recording medium moving along the paper moving path above the endless belt 33 in order. To form a full-color toner image.

(2): Outline of Operation When the image recording apparatus configured as described above is operated, it is connected to the host computer 29 and operated. In operation, when a recording command (print command) is sent from the host computer 29 to the image recording apparatus, a data request is issued from the image recording apparatus to the host computer 29. When image data is sent from the host computer 29 to the image recording apparatus in response to this request, image recording is performed in the image recording apparatus, and a response signal is returned from the image recording apparatus to the host computer 29. In this way, printing is performed on the print medium in the image recording apparatus.

In this case, the following operation is performed in the image recording apparatus. In the image recording apparatus, the host computer 2
9, a recording command (print start command) is issued, and subsequently, when image data to be printed is sent in response to a data request, an internal control unit (not shown) controls image data from the host computer 29. The image recording is started based on.

At this time, the upper traveling portion (upper part in the figure) of the endless belt 33 forms a moving path of the recording medium. The recording medium is accumulated in the hopper 31, is fed out one by one from the recording medium at the uppermost part of the hopper 31 by a pickup roller (not shown), and is introduced into the recording medium moving path from the roller side of the endless belt 33. The recording medium that has passed through the movement path is discharged from the rollers, and then conveyed to the stacker 32 and discharged to the stacker 32. §2: Description of the image recording unit ... see FIG. 2 FIG. 2 is a block diagram of the image recording unit. As described above, the image recording apparatus is provided with the image recording units 35 to 38 for recording images for each color, and these image recording units 35 to 38 are configured as shown in FIG.

As shown in FIG. 2, each image recording unit has a CPU (central processing unit) 45 for performing various controls in the image recording unit, and a reception for performing image data reception control based on instructions from the CPU 47. A control unit 47; a buffer 48 for temporarily storing image data for each color (Y, M, C, BK) transferred from the host computer 29 in response to a data request from the reception control unit 45; A multi-phase clock generation circuit 46, an image data memory 53 for storing image data, and the image data memory 53
An image data memory R / W arbitration unit 49 for arbitrating read / write of image data, an optical scanning unit 54 for optically scanning the photosensitive drum 41, and the CP
A recording control unit 50 that controls recording of image data based on an instruction from U45, a pixel clock control unit 1 that inputs a multi-phase clock generated by the multi-phase clock generation circuit 46 and controls a pixel clock, A correction data memory 52 for storing correction data (including pixel pitch correction data) is provided.

The operation of each unit is as follows. CPU
Upon receiving the recording command from the host computer 29, the 45 analyzes the contents and instructs the reception control unit 47 to receive image data. In response to this instruction, the reception control unit 47
Makes a data request to the host computer 29.

Thereafter, when image data is sent from the host computer 29, the reception control unit 47 receives the image data and stores the image data in the buffer 48.
The CPU 45 notifies the CPU 45 that the image data has been received. Then, the reception control unit 47 sends the image data write information to the image data memory R / W arbitration unit 49.

Upon receiving the image data write information, the image data memory R / W arbitration unit 49 sends address information and image data to the image data memory 53 based on the information, and sends the address information and image data to the image data memory 53. Buffer 48
Is stored. The image data transferred from the host computer 29 in this manner is sequentially stored in the image data memory 53.

On the other hand, the CPU 45 having received the recording command (print command) instructs the recording control unit 50 to start recording image data. In response to this instruction, the recording control unit 50 sends a read start signal to the image data memory R / W arbitration unit 49. The image data memory R / W arbitration unit 49 receiving this signal sends address information to the image data memory 53, reads out the corresponding image data, and sends the image data to the recording control unit 50.

Upon receiving the image data, the recording control section 50 sends a laser modulation signal to the optical scanning unit 54. The optical scanning unit 54 performs optical scanning with laser light using the laser modulation signal, and performs exposure recording on the photosensitive drum 41. When exposure and recording are performed with the laser light modulated by the image data in this manner, the laser light that has been optically scanned by the laser light detector 3 is detected, and a beam detection signal is input to the pixel clock control unit 1.

When performing exposure recording with the laser light modulated as described above, the pixel clock control unit 1 controls the multi-phase clock from the multi-phase clock generation circuit 46 and the beam detected by the laser light detector 3. The detection signal is input to control the pixel clock. In this case, the pixel clock control unit 1
The pixel pitch correction data read start signal generated inside the pixel clock correction data memory 52 is sent to the correction data memory 52, and the pixel pitch correction data stored in the correction data memory 52 is read and stored in the correction information storage means 16 in the pixel clock control unit 1. The pixel clock is controlled using these data.

That is, for the image quality correction including the optical system such as the fθ characteristic, the image quality correction data (in this example, the pixel pitch correction data) is stored in advance in the correction data memory 52 and read out in synchronization with the pixel clock. Like that. Then, the data read from the correction data memory 52 is used as an instruction to advance or delay the pixel clock phase, and the phase shift control of the pixel clock is performed to correct the image quality.

§3: Description of Pixel Clock Control Unit—See FIG. 3 FIG. 3 is a block diagram of the pixel clock control unit. In addition,
3, the same components as those in FIGS. 10 and 2 are denoted by the same reference numerals. As described above, the image recording unit 3 for each color
5 to 38 are provided, and each of these image recording units is provided with a pixel clock control unit 1 for controlling a pixel clock. The configuration of each pixel clock control unit 1 will be described with reference to FIG.

In FIG. 3, reference numeral 4 denotes a horizontal synchronizing signal detecting circuit, which is a group of multi-phase clocks Φ _{0 to} Φ _n from the multi-phase clock generating circuit 46 and a beam detecting signal (laser beam detecting signal) from the laser beam detector 3. Signal) to detect a horizontal synchronizing signal. Reference numeral 58 denotes a correction amount calculation circuit which receives an output signal from the horizontal synchronization signal detection circuit 4 and calculates a correction amount. 59 is a correction amount setting register,
This is for setting writing correction information (writing position correction information).

Reference numeral 60 denotes a correction amount 1 storage means for storing the correction amount calculated by the correction amount calculation circuit 58 and outputting a compression instruction signal (hereinafter, referred to as "compression instruction 1").
Reference numeral 61 denotes a correction amount 2 storage means, and the correction amount setting register 5
9, the correction amount (hereinafter referred to as “correction amount 2”) is stored, and a decompression instruction (hereinafter referred to as “decompression instruction 1”) is output. Reference numeral 16 denotes a correction information storage unit which stores the pixel pitch correction data read from the correction data memory 52, and includes a compression instruction signal (hereinafter, referred to as "compression instruction 2") and an expansion instruction signal (hereinafter, "expansion instruction 2"). ) Is output.

Reference numeral 17 denotes a pixel clock number setting register for setting pixel pitch correction start information (pixel clock number). Reference numeral 18 denotes a pixel clock number setting register for setting laser modulation start information (pixel clock number). Reference numeral 19 denotes a pixel clock number setting register for setting laser modulation end information (pixel clock number).

Reference numeral 20 denotes a pixel clock counter.
In synchronization with the beam synchronous signal outputted from the horizontal synchronizing signal detecting circuit 4, is, the number of pixel clock [Phi _x output from the pixel clock modulation means 64. Reference numeral 9 denotes a P / S conversion circuit (parallel / serial conversion circuit) which converts input image data (parallel data) into serial data to generate a laser modulation output.

A comparison circuit 21 compares the value of the pixel clock number setting register 17 with the value of the pixel clock counter 20. A comparison circuit 22 compares the value of the pixel clock number setting register 18 with the value of the pixel clock counter 20. A comparison circuit 23 compares the value of the pixel clock number setting register 19 with the value of the pixel clock count counter 20.

Reference numeral 24 denotes a set / reset type flip-flop (hereinafter referred to as “FF”). The comparison result of the comparison circuit 21 is input to the set terminal S, and the comparison result of the comparison circuit 23 is used as the reset terminal. A pixel pitch correction data read start signal is generated and output to the correction information storage means 16 as an enable signal (input signal of an EN terminal).

Reference numeral 25 denotes a set / reset type flip-flop (hereinafter, referred to as “FF”). The comparison result of the comparison circuit 22 is input to the set terminal S, and the comparison result of the comparison circuit 23 is set to the reset terminal. It generates a pitch correction data read start signal and outputs it to the P / S conversion circuit 9 as an enable signal (input signal of the EN terminal).

Reference numeral 65 denotes a logical sum circuit (hereinafter referred to as an “OR circuit”), which is a logical sum of a compression instruction 1 output from the correction amount 1 storage means 60 and a compression instruction 2 output from the correction information storage means 16. By performing the operation, a signal of a compression instruction is output. Reference numeral 66 denotes a logical sum circuit (hereinafter, referred to as an “OR circuit”) that performs a logical sum operation of the decompression instruction 1 output from the correction amount 2 storage unit 61 and the decompression instruction 2 output from the correction information storage unit 16. Thus, a signal of a decompression instruction is output.

Reference numeral 64 denotes a pixel clock modulating means, which is an exclusive OR circuit (hereinafter referred to as an "EOR circuit") 67, 68.
And a clock phase control circuit 69. And
The EOR circuit 67 outputs the output of the OR circuit 65 (compression instruction).
By performing an exclusive OR operation on the output of the OR circuit 66 (decompression instruction), a phase advance instruction signal is output. The EOR circuit 68 outputs a delay instruction signal by performing an exclusive OR operation on the output (compression instruction) of the OR circuit 65 and the output (decompression instruction) of the OR circuit 66. Further, the clock phase control circuit is provided with the EOR circuits 67 and 6
8 the output signal of, is to multiphase clock group, and then the beam sync signal input to generate a pixel clock [Phi _X output.

§4: Description of horizontal synchronizing signal detection circuit
FIG. 4 shows a configuration example of a horizontal synchronization signal detection circuit. In this example, the horizontal synchronization signal detection circuit 4 includes a delay element 71,
An AND circuit (AND circuit) 72, a set / reset type flip-flop (hereinafter referred to as “FF”) 73, and a plurality (four in this example) provided corresponding to the polyphase clock
FFs 74 (hereinafter, referred to as “FF”) and a second column FF including a plurality of flip-flops provided at a stage subsequent to the first column FF group 74.
A group 75, a third column FF group 76 including a plurality of flip-flops provided at a stage subsequent to the second column FF group 75, and an inverter 78 connected to the output side of each FF of the third column FF group. An AND circuit group 7 including a plurality of AND circuits (logical AND circuits) provided at the subsequent stage of the third column FF group 76
7 is provided.

The delay element 71 outputs a beam detection signal (BD
S) is delayed for a predetermined time. AND circuit 72
Is to generate a BDS delay signal by taking the logical product of the beam detection signal (BDS) and the output signal of the delay element 71. The FF 73 generates a BDS hold signal (signal for holding a beam detection signal) by inputting an output signal of the AND circuit 72 and a laser modulation end signal. The BDS hold signal is input to the first column FF group 74.

The first column FF group 74 is provided with the BDS hold signal.
Signal as data input (input signal of D terminal),
Clock generated by the clock generation circuit 46 (Φ₀,
Φ₁, Φ _Two, Φ_Three) Clock input (CP terminal input signal)
No.). The second column FF group 75 is the first column FF
The output signal of the group 74 is used as a data input, and a multi-phase clock (Φ
₀, Φ₁, Φ_Two, Φ_Three) With clock input
You.

The third column FF group 76 uses the output signal of the second column FF group 75 as a data input (input signal of the D terminal) and a clock input. The AND circuit group 77 has a third column FF
The logical product of the output of the group 76 and the signal obtained by inverting the output of the third column FF group 76 by the inverter 78 is obtained.

§5: Description of Multi-Phase Clock—See FIG. 5 FIG. 5 is an explanatory diagram of the multi-phase clock, where A shows a conventional multi-phase clock, and B shows a multi-phase clock of the present invention. Conventionally, generally used multi-phase clock generation circuits generate multi-phase clocks having different phases.
In such a conventional multi-phase clock generation circuit, for example,
As shown in FIG. 5A, a multi-phase clock group (generally, a clock pulse) composed of clocks (clock pulses) Φ _{0 to} Φ ₃
Φ _{0 to} Φ _n ).

When the multi-phase clock (four-phase clock in this example) Φ ₀ , Φ ₁ , Φ ₂ , and Φ ₃ is Φ ₀ as a basic clock, Φ ₁ , Φ ₂ , and Φ ₃ are the basic clock. Φ ₀
Is a clock having a fixed phase shift with respect to. In this case, after the clock Φ ₀ changes from the high level H to the low level L,
The next clock Φ ₁ is made from a low level L and the high level H. Then, after the clock [Phi ₁ is changed from the high level H to low level L, the next clock [Phi ₂ is made from a low level L to high level H.

Next, after the clock φ ₂ changes from the high level H to the low level L, the next clock φ ₃ changes from the low level L to the high level H. Thereafter, the above state is repeated to generate a multi-phase clock group composed of Φ ₀ , Φ ₁ , Φ ₂ , and Φ ₃ . As described above, the conventional multi-phase clocks Φ ₀ , Φ ₁ , Φ ₂ , Φ
₃ is generated sequentially.

On the other hand, the multi-phase clock generation circuit 46 of the device according to the present invention generates a multi-phase clock as shown in FIG. 5B. That is, in the multi-phase clock generation circuit 46, for example, as shown in B of FIG. 5, the clock (clock pulse) [Phi ₀ to [phi] a _three multiphase clock group (typically, [Phi ₀ to [phi] _n polyphase clocks).

[0088] The multi-phase clock (in this example four-phase _{clock) Φ 0, Φ 1, Φ} 2, of the [Phi _3, when the [Phi ₀ and the basic _{clock, Φ 1, Φ 2, Φ} 3 is the basic clock Φ ₀
Is a clock having a fixed phase shift with respect to. In this case, the clock Φ ₀ changes from the low level L to the high level H, and before the clock Φ ₀ changes to the low level L, the next clock Φ ₁ changes from the low level L to the high level H (Φ ₀ and Φ ₁ overlap and output Is done).

Next, before the clock Φ ₁ changes from the high level H to the low level L, the next clock Φ ₂ changes from the low level L to the high level H (Φ ₁ and Φ ₂ are output overlapping). . Next, before the clock φ ₂ changes from the high level H to the low level L, the next clock φ ₃ changes to the low level L.
It becomes high level H from ([Phi ₂ and [Phi ₃ is output overlapping).

Thereafter, the above-mentioned state is repeated, and Φ ₀ ,
A multi-phase clock group consisting of Φ ₁ , Φ ₂ and Φ ₃ is generated.
As described above, in the conventional multi-phase clock, Φ ₀ , Φ ₁ , Φ ₂ , and Φ ₃ are sequentially generated so that each clock pulse overlaps. Therefore, high-speed image recording can be achieved by using such overlapping multi-phase clocks.

§6: Description of Operation—See FIGS. 6 to 9 In the apparatus having the configuration shown in FIGS. 1 to 4, the conventional high-frequency clock oscillator and the pixel clock control circuit using the ultra-high-speed ECL element are used. It is intended to realize fine pixel positioning control at low cost. For this reason, in the conventional example,
A single-phase clock having a frequency N times the pixel clock is used as an input clock, and the increase / decrease control of the divided value is performed. However, in the device according to the present invention, the divided value of the conventional example is set to the same frequency as the pixel clock. A corresponding number of multiphase clocks (see FIG. 5) are used as input clocks, and synchronization with a beam signal, correction of a write start position, and optimization of a pixel position in a beam scanning area are all realized only by changing clock phases. . Hereinafter, detailed operations will be described based on each timing chart.

(1): Description of timing chart (a): Description of FIG. 6 FIG. 6 is a timing chart of a beam detection signal, a beam synchronization signal, and a pixel clock. In FIG. 6, a is a beam detection signal (also referred to as “BDS”), which is output from the laser light detector 3. b denotes a BDS delay signal obtained by delaying the BDS by a predetermined time, and is output from the AND circuit 72. c is a BDS hold signal, which is output from the FF 73. d is a reference clock φ _0, which is output from the multi-phase clock generation circuit 46. e is the pixel clock Φ _X
And output from the pixel clock modulation means 64. f
Is a beam synchronization signal, which is output from the horizontal synchronization signal detection circuit 4.

(B): Description of FIG. 7 FIG. 7 is a timing chart 1 for synchronizing with a beam detection signal.
, And the shows the case where [Phi ₁ four-phase clock a beam detection signal is first detected by the writing correction information = 0. In FIG. 7, a is a BDS hold signal (same as c in FIG. 6). b is a four-phase clock (polyphase clock) Φ ₀ , Φ ₁ , Φ
₂ and Φ _3, which are output from the multi-phase clock generation circuit 46.

C is the pixel clock Φ _X (same as e in FIG. 6)
It is. d is a beam synchronization signal (same as f in FIG. 6). e is a load signal output from the horizontal synchronization signal detection circuit 4. f is a correction amount (BD synchronization) output from the correction amount calculation circuit 58. g is the state of the counter of the correction amount 1 storage means 60. h is a time-up signal (CY) of the counter of the correction amount 1 storage means 60.

I is a compression instruction 1 output from the correction amount 1 storage means 60. j is the write-out correction amount set in the correction amount setting register 59. k is the correction amount 2 storage means 6
This is the state of the counter of 1. m is the correction amount 2 storage means 61
Is a time-up signal (CY) of the counter of FIG. n is an expansion instruction 1 output from the correction amount 2 storage means 61.

(C): Description of FIG. 8 FIG. 8 is a timing chart 2 for synchronizing with the beam detection signal.
This shows the case where the writing correction information = 3 and the beam detection signal is first detected by the four-phase clock Φ ₃ . In FIG. 8, a is a BDS hold signal. b is a four-phase clock Φ ₀ , Φ ₁ , Φ ₂ , Φ ₃ . c is the pixel clock Φ
_X. d is a beam synchronization signal output from the horizontal synchronization signal detection circuit 4. e is a load signal output from the horizontal synchronization signal detection circuit 4. f is a correction amount calculation circuit 5
8 is a correction amount (BD synchronization) output from the reference numeral 8.

G is the state of the counter of the correction amount 1 storage means 60. h is a time-up signal (CY) of the counter of the correction amount 1 storage means 60. i is the correction amount 1 storage means 6
This is the compression instruction 1 output from 0. j is the write-out correction amount set in the correction amount setting register 59.

K is the state of the counter of the correction amount 2 storage means 61. m is a time-up signal (CY) of the counter of the correction amount 2 storage means 61. n is the correction amount 2 storage means 6
This is the decompression instruction 1 output from the first instruction.

(D): Description of FIG. 9 FIG. 9 is a correction timing chart based on the pixel pitch correction data. In FIG. 9, a is a beam detection signal (denoted as “BDS”) output from the laser light detector 3. b is a BDS hold signal. c is a pixel clock [Phi _X. d is the state of the pixel clock counter 20. e is an output of the comparison circuit 21. f is the output of the comparison circuit 22.

G is the output of the comparison circuit 23. h is FF
This is a pixel pitch correction data read start signal output from 24 to the correction information storage means 16. m is image data input to the P / S conversion circuit 9. n is a laser modulation output output from the P / S conversion circuit 9.

(2) Description of Operation Based on Timing Chart Hereinafter, the operation will be described based on the timing chart. (a): Before starting the drawing of image data, pixel clock control information such as write-out correction information (write-out position correction information), pixel pitch correction start information, laser modulation start information, and laser modulation end information is stored in each register by the CPU 45. Is set to That is, the CPU 45 sets the writing correction information in the correction amount setting register 59, sets the pixel pitch correction start information in the pixel clock number setting register 17, sets the laser modulation start information in the pixel clock number setting register 18, The modulation end information is set in the pixel clock number setting register 19.

(B): On the other hand, as shown in FIG. 4, the horizontal synchronizing signal detection circuit 4 receives the beam detection signal (BDS) from the laser beam detector 3 and converts the beam detection signal into a delay element 71. The noise is removed by delaying with. The AND circuit 72 calculates the logical product of the signal passed through the delay element 71 and the original beam detection signal to generate a BDS delay signal (see FIG. 6B).

Thereafter, the FF 73 inputs the BDS delay signal to the set terminal S, and inputs the laser modulation end signal sent from the CPU 45 to the reset terminal R. As a result, the FF 73 is set at the rise of the beam detection signal connected to the set input, the laser modulation is completed, and the FF 73 is reset immediately before a new beam detection signal is input.
A DS hold signal (see FIG. 6C) is generated.

The BDS hold signal is input to the first column FF group 74 which receives the multi-phase clocks Φ _{0 to} Φ _n (n = 3 in this example) as clocks, and outputs the same multi-phase clock as the input. To the input of the second column FF group 75. The first column FF group 74 receives an asynchronous beam detection signal (BD
Synchronize S) to the multi-phase clock Φ ₀ ~Φ _n, the second column FF
It is provided only for transmitting a stable signal to the group 75.

Following the rising edge of the beam detection signal, the first column FF group 74 is set in the order of clock phases starting from a flip-flop having a clock phase as the first rising edge as an input. Then, the output of the first column FF group 74 is delayed by one clock and the second column FF group 75 is output.
Is transmitted to.

Here, the clock Φ ₀ is defined as a reference clock phase in the pixel clock control unit 1, and the second column F
The output of the flip-flop having the reference clock phase (Φ ₀ ) as an input in the F group 75 becomes a provisional beam synchronization signal (f in FIG. 6) synchronized with the reference clock phase.

(C): Next, the output of the second column FF group 75 is connected to the third column FF group 76, and the clock input of the third column FF group 76 is supplied to the data input side (D terminal side). The output of the flip-flop having a clock input delayed by two phases is connected to the flip-flop.

The output of the third column FF group 76 is the AND
The AND circuit group 77 specifies a clock phase in which the rising edge of the beam detection signal is first captured, and one of the corresponding AND circuits outputs a logic “1”, and the subsequent correction is performed. Through the amount calculation circuit 58,
The number of clock phase differences between the clock phase and the reference clock phase is calculated, and the correction amount necessary for synchronizing with the beam signal is output to the correction amount 1 storage means 60.

(D): The correction amount is loaded into the counter of the correction amount 1 storage means 60 by a load signal output from the horizontal synchronization signal detection circuit 4, and the correction amount 1 storage means 60
Outputs the compression instruction 1 during the period from the load signal to the completion of counting the pixel clocks for the correction amount.

(E): The correction amount based on the write-out correction information set in the correction amount setting register 59 is also loaded into the counter of the correction amount 2 storage means 61 by the load signal. The decompression instruction 1 is output during the period from the load signal to the completion of counting the pixel clocks for the correction amount.

(F): FIGS. 7 and 8 are timing charts showing synchronization with the beam detection signal by the four-phase clock. As described above, the beam detection signal (BD
S) is for BD by the FF 73 of the horizontal synchronization signal detection circuit 4
Is converted into an S hold signal, and 1 and 2 of the reference clock Φ ₀
And outputs a beam synchronization signal (see d in FIGS. 7 and 8).

The BDS hold signal includes clocks Φ _{0 to} Φ ₃
1 and 2 are transmitted to the first column FF group 74 and the second column FF group 75, and the third column FF group 76 is set according to the output change of the second column FF group 75. In the third column FF group 76, two flip-flops to which the phase of the beam detection signal is detected first and the clock of the next phase are set are set, and the inverter 78 and the AND circuit group 77 at the subsequent stage first set the beam. Only the phase where the detection signal is detected is extracted.

First, when the BS hold signal is detected with the clock φ ₁ , the clock phase φ ₁ is extracted, and the phase difference 3 from the reference clock phase is output as the correction amount (BD synchronization) by the correction amount calculating circuit 58. .

(G): 4 counting from the beam synchronization signal
The output is started as the pixel clock Φ _X from the fifth reference clock Φ ₀ (see c in FIGS. 7 and 8). (h): In the example of FIG. 7, the output load signal (see e) with 2 fall of the pixel clock [Phi _X, the correction amount to the counter of the correction amount 1 storage unit 60 (BD synchronization) inverse of 3 "C "
(15-3) is loaded (see f and g), and a compression instruction 1 is output (see h and i) over four pixel clocks. Also,
The reciprocal "F" (15-0) of the correction amount (write) 0 is loaded (see j and k) into the counter of the correction amount 2 storage means 61 by the load signal (see j and k), and the expansion instruction 1 is issued over one pixel clock.
(See m and n).

The compression instruction 1 and the decompression instruction 1 are input to the pixel clock modulating means 64, and the three compression instructions passed through the exclusive OR circuits (EOR67, EOR68) are used as phase advance instructions for clock phase control. Input to the circuit 69. The pixel clock modulating means 64 outputs the pixel clock Φ _X
First, 5 to 10 of the clock Φ ₀ are output, and then, the clock phase control circuit 69 receives three phase advance instructions, and the phase of Φ ₃ whose phase is advanced by one sequentially from the current clock phase. 11, 12 of [Phi _2, changed 3 times riding the clock phase to [Phi ₁ of 13, a clock phase transfer for the first beam detection signal synchronization was reached clock phase [Phi ₁ that has detected the BDS hold signal is completed Clock phase Φ ₁
Locks the phase (PLL control).

In FIG. 7, the clock phase emphasized by a bold line in the four-phase clocks Φ _{0 to} Φ ₃ is the pixel clock Φ.
Show what is selected as _X. To highlight the portion of the normal clock cycle by bold lines in the pixel clock [Phi _X waveforms, 3/4 shows an example in which the periodic modulation (compressed pixel positions) to the clock period.

(I): The example of FIG. 8 shows a case where the BDS hold signal (see a) is detected in the clock phase Φ ₃ and the write-out correction information is 3. In this case, compression instruction 1 (see i)
Is “1” and the decompression instruction 1 (see n) is “3”,
Two expansion instructions are input to the clock phase control circuit 69 as delay instructions. When the phase is delayed, the clock phase control circuit 69 outputs the logical sum of the old clock phase and the new clock phase as the pixel clock Φ _X (see c) at the time of the clock phase change.

In FIG. 8, the logical OR of Φ ₀ and Φ ₁ 11 and Φ ₁ and Φ ₂ 12 emphasized by the bold line in the four-phase clock Φ _{0 to} Φ ₃ waveforms is the bold line of the pixel clock Φ _X. The example corresponds to the emphasized 7 and 8 and is periodically modulated (extended the pixel position) to 5/4 cycle with respect to the normal clock cycle.

(J): In FIG. 9, in region A, clock synchronization with the beam detection signal and pixel clock modulation for correcting the write start position are performed. In the drawing area of the area B, pixel pitch correction information (compression instruction 2 and expansion instruction 2) corresponding to the pixel clock number in advance is used in order to correct the characteristics of the optical system, obtain an unbiased image, and obtain a desired image width. ) Is created and stored in the correction data memory 52 (see FIG. 2). At the time of drawing reads the correction data for each [Phi _X of the pixel clock, performs pixel clock modulation by said correction data.

(K): In FIG. 9, pixel pitch correction start
Information, laser modulation start information, and laser modulation end information
The case where it is set to 12, 17, and 56, respectively is shown. Pixel black
The counter 20 counts at the rising edge of the beam synchronization signal.
Cleared, pixel clock Φ _XContinue counting up every time
I can.

As a result, when the count is “12”, the comparison circuit 2
1 is turned on, the comparison circuit 22 is turned on when the count is “17”, and the pixel pitch correction data read start signal and the image data read start signal are set (read start state). Further, at the count “56”, the comparison circuit 23 is turned on, and the pixel pitch correction data read start signal and the image data read start signal are simultaneously reset (read prohibited state).

(L): Upon receiving the pixel pitch correction data read start signal, the correction data in the correction data memory 52 is loaded in parallel to the correction information storage means 16 composed of a shift register every N pixel clocks. Data parallel loading is converted to serial data by the pixel clock [Phi _X, 2 bits of the compressed instruction 2 and expansion instruction 2 is output.

The logical sum (the logical sum by the OR circuit 65 and the OR circuit 66) of the two bits and the previous compression instructions 1 and 2 is input to the pixel clock modulating means 64, and the exclusive OR circuits (EOR67 and EOR68) are provided. ) fast instruction through discrimination by, or slow instruction is input to the clock phase control circuit 69 to obtain a pixel clock [Phi _X that is periodically modulated by the clock phase transfer.

(M): In response to the image data read start signal, the image data in the image data memory 53 (see FIG. 2) is converted to a P / S composed of a shift register every N pixel clocks.
The data is parallel loaded into the conversion circuit 9. Data parallel loading is converted to serial data by the pixel clock [Phi _X, is output to the laser drive circuit as a laser modulation output (circuit in the optical scanning unit 54), a photoreceptor (e.g., a photosensitive drum 41) on Perform exposure recording.

§7: Other explanations (1): The image recording apparatus directly performs exposure drawing by laser light modulation on a plate material coated with a photosensitive agent, and develops and etches a non-exposed portion. The present invention is applicable to a direct plate-making apparatus that creates a printing plate, or another image recording apparatus (printer, printing apparatus) or the like.

(2): In the prior art, in the case of a relatively low-speed image forming apparatus, a multi-phase pixel clock based on an N-fold clock is generated and the pixel clock is switched to detect a beam. Synchronization with signals and correction of fθ characteristics have been realized.

However, the present invention uses a multi-phase clock having the same cycle as the laser modulation frequency and immediately selects the clock phase in which the beam detection signal is first detected, instead of using the pixel phase as the pixel clock. The specific clock phase in the above is used as the reference clock phase, and the phase difference between the reference clock phase and the first detected clock phase is measured, so that the pixel clock output first is always the reference clock phase.
By performing shift control of the pixel clock phase so that the previously measured phase difference becomes “0”, synchronization with the beam detection signal (BD synchronization) is performed.

For image quality correction including the optical system such as the fθ characteristic, image quality correction data (including pixel pitch correction data) is stored in advance in the correction data memory 52 (see FIG. 2) and synchronized with the pixel clock. And read it out. Then, the data read from the correction data memory 52 is used as an instruction to advance or delay the pixel clock phase, and the phase shift control of the pixel clock is performed to correct the image quality.

That is, the present invention realizes PLL synchronization with a BD (beam detection signal), which is an external signal, by a multiphase clock, and PLL control for performing a phase shift control of a pixel clock by an image quality correction factor.

[0130]

As described above, the present invention has the following effects. (1): Conventionally, a single-phase clock having a frequency N times the pixel clock is used as an input clock, and the increase / decrease control of the frequency division value is performed. In the present invention, the same frequency as the pixel clock is used. The number of polyphase clocks corresponding to the frequency division value of the input clock is used as the input clock, and synchronization with the laser beam detection signal, correction of the writing start position, and optimization of the pixel position in the beam scanning area are all performed only by changing the clock phase. realizable. For this reason, it is not necessary to use a circuit using an ultra-high-speed ECL element as in the related art, so that fine pixel positioning control can be realized at low cost.

[0131] (2): In the image recording apparatus, the speed of image recording and higher resolution, more diversified print (color, etc. artwork output) amid progresses, a fast pixel clock exceeding frequency = 300MH _Z In order to realize the pixel clock fine adjustment function for each pixel, it is necessary to satisfy all of the following conditions (1) to (4).

Synchronizing the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. : Variation in the mounting position of the laser light detector is 1 / N
Correct in pixel units.

Correction of the mounting position of the laser light detector between the recording units is corrected in 1 / N pixel units. : Correcting an image shift due to characteristics of the optical scanning system (surface tilt, fθ characteristics, mirror rotation speed, focal depth) in 1 / N pixel units for each pixel.

The compression / expansion of the print width in 1 / N pixel units. : To be able to respond to a high-speed pixel clock.
However, in the present invention, a high-speed multi-phase clock in which each clock overlaps can be used, and thereby, a high-speed pixel clock and a pixel clock fine adjustment function for each pixel clock can be realized. Further, the output of the laser light detector and the pixel clock can be synchronized in units of 1 / N (N: an arbitrary integer) pixels. Therefore, all of the above conditions can be satisfied. As a result, an inexpensive and stable pixel clock control means that can sufficiently cope with an increase in speed and resolution of the image recording apparatus can be realized.

(3) According to the present invention, fine pixel positioning control by a conventional high-frequency clock oscillator or a pixel clock control circuit using an ultra-high-speed ECL element can be realized at low cost. That is, in the conventional example, a single-phase clock having a frequency N times the pixel clock is used as an input clock and the increase / decrease control of the frequency division value is performed. However, in the device according to the present invention,
With the same frequency as the pixel clock and the number of multi-phase clocks equivalent to the frequency division value of the conventional example as the input clock, synchronization with the beam signal, correction of the writing start position, and optimization of the pixel position in the beam scanning area are performed. All are realized only by changing the clock phase. Therefore, in the present invention, fine pixel positioning control can be realized at low cost without using an expensive ECL element or the like.

In addition to the above effects, the following effects are provided corresponding to each claim. (4) In the first aspect, the multi-phase clock generating means generates a multi-phase clock in which the respective clocks overlap each other, and the first correction amount storage means stores the multi-phase clock generated by the multi-phase clock generating means. The phase difference between a specific reference clock phase of the clock and the clock phase in which the beam detection signal is detected first is defined as the number of phase shifts from the reference clock, and this phase shift number is stored as a correction amount.

The pixel clock modulating means selects one of the N multi-phase clocks generated by the multi-phase clock generating means as a pixel clock, and switches every 1 / N clock every time switching to an adjacent phase. And outputs the compressed and expanded pixel clock.

As described above, the beam detection signal is sampled, and the clock phase in which the beam detection signal is first detected is used as a reference pixel clock. In this case, during the period from the beam detection to the start of laser modulation by the pixel data, the selection of the clock phase is switched stepwise from the reference clock phase via the pixel clock modulation means based on the correction amount. Is obtained.

In this way, a high-speed multi-phase clock in which the respective clocks overlap can be used, thereby realizing a high-speed pixel clock and a pixel clock fine adjustment function for each pixel clock. Further, the output of the laser light detector and the pixel clock can be synchronized in units of 1 / N (N: an arbitrary integer) pixels. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording.

(5): In the second aspect, the second correction amount storage means stores a specific reference as a correction amount for performing fine adjustment of a recording start position at which laser modulation is started based on pixel data from beam detection. The phase difference from the clock is stored as the number of phase shifts. Then, during the period from the beam detection to the start of the laser modulation based on the pixel data, based on the correction amount stored in the second correction amount storage unit, the clock phase detected first through the pixel clock modulation unit is used. The recording start position is adjusted in 1 / N pixel units by switching stepwise to a clock phase corresponding to the correction amount.

This makes it possible to respond to a high-speed pixel clock, and synchronize the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. Further, it is possible to correct the image shift due to the characteristics of the optical scanning system in units of 1 / N pixel for each pixel. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording.

(6): In claim 3, when the correction amounts are stored in the first and second correction amount storage means, the correction amount of the first correction amount storage means and the correction amount of the second correction amount storage means are stored. One is stored as the compression amount and the other is stored as the expansion amount so that the polarities of the correction amounts are opposite.

This makes it possible to respond to a high-speed pixel clock, and synchronize the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. Further, it is possible to correct the image shift due to the characteristics of the optical scanning system in units of 1 / N pixel for each pixel. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording. (7) According to claim 4, when the pixel clock is modulated by the pixel clock modulating means, the correction amount is read out from the first and second correction amount storage means at the same timing in synchronization with the pixel clock, and one of the two is read out. The correction amount is sent to the pixel clock modulating means as a compression instruction and the other correction amount as an expansion instruction. In the pixel clock modulating means, an exclusive OR circuit takes an exclusive OR of the compression instruction and the decompression instruction, and modulates the pixel clock according to the result.

This makes it possible to cope with a high-speed pixel clock, and synchronize the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. Further, it is possible to correct the image shift due to the characteristics of the optical scanning system in units of 1 / N pixel for each pixel. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording.

(8) In claim 5, the correction information storage means stores pixel pitch correction data for instructing a dynamic correction of each pixel pitch in the effective scanning area of the laser beam. The correction data reading means reads the correction data from the correction information storage means in synchronization with the pixel clock after the pixel clock modulation by the pixel clock modulation means is completed.

The pixel pitch correction data read from the correction information storage means by the correction data reading means is input to the pixel clock modulation means, and based on the pixel pitch correction data, the pixel clock modulation is performed within the effective scanning area of the laser beam. I do. Further, laser modulation based on pixel data is performed in a part of the effective scanning area.

This makes it possible to cope with a high-speed pixel clock, and synchronize the output of the laser light detector with the high-speed pixel clock in 1 / N pixel units. Further, it is possible to correct the image shift due to the characteristics of the optical scanning system in units of 1 / N pixel for each pixel. Therefore, it is possible to sufficiently cope with high-speed and high-resolution image recording.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an image recording apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of an image recording unit according to the embodiment.

FIG. 3 is a block diagram of a pixel clock control unit according to the embodiment.

FIG. 4 is a configuration example of a horizontal synchronization signal detection circuit according to the embodiment;

FIG. 5 is an explanatory diagram of a multiphase clock according to the embodiment.

FIG. 6 is a timing chart of a beam detection signal, a beam synchronization signal, and a pixel clock in the embodiment.

FIG. 7 is a timing chart 1 of synchronization with a beam detection signal in the embodiment.

FIG. 8 is a timing chart 2 of synchronization with a beam detection signal in the embodiment.

FIG. 9 is a correction timing chart based on pixel pitch correction data in the embodiment.

FIG. 10 is a block diagram of a conventional pixel clock control unit.

FIG. 11 is a timing chart of FIG.

[Explanation of symbols]

 Reference Signs List 1 pixel clock control unit 2 ECL oscillator 3 laser light detector 4 horizontal synchronizing signal detection circuit 5 pulse width setting register 7 cycle counter 8 pulse width setting counter 9 P / S conversion circuit (parallel / serial conversion circuit) 12, 13 cycle setting Register 14 Selector 15 Adder 16 Correction information storage means 17, 18, 19 Pixel clock number setting register 20 Pixel clock count counter 21, 22, 23 Comparison circuit 31 Hopper 32 Stacker 33 Endless belt 35, 36, 37, 38 Image recording unit Reference Signs List 39 optical unit 40 fixing unit 41 photosensitive drum 42 developing unit 45 CPU (central processing unit) 46 multi-phase clock generation circuit 47 reception control unit 49 image data memory R / W arbitration unit 50 recording control unit 52 correction data memory 53 image data memory 5 Optical scanning unit 58 Correction amount calculation circuit 59 Correction amount setting register 60 Correction amount 1 storage unit 61 Correction amount 2 storage unit 64 Pixel clock modulation unit 69 Clock phase control circuit 71 Delay element 74 First column FF group (First column flip-flop) Group) 75 2nd column FF group (2nd column flip-flop group) 76 3rd column FF group (3rd column flip-flop group) 77 AND circuit group (AND circuit group)

Claims (5)

[Claims] An optical scanning unit for scanning a laser beam;
Equipped with a laser light detector that detects the scanning start position of the laser light and outputs a beam detection signal, and scans the laser light modulated using pixel data and pixel clock to perform exposure recording on the photoreceptor and image A multi-phase clock generating means for generating a multi-phase clock for determining a modulation period of pixel data; and detecting a beam detection signal first with a specific reference clock phase of the multi-phase clock. A first correction amount storing means for storing a phase difference from the reference clock phase as a phase shift number from the reference clock, and storing the phase shift number as a correction amount; and one of the N multi-phase clocks A pixel clock modulating means for selecting a pixel clock and outputting a compressed / expanded pixel clock in 1 / N clock units every time a transition is made to an adjacent phase; The sampling phase of the beam detection signal is sampled, and the clock phase at which the beam detection signal is first detected is used as a reference pixel clock, and the correction amount is used during the period from the beam detection to the start of laser modulation by pixel data. An image recording apparatus, wherein the reference pixel clock is obtained by switching the selection of the clock phase stepwise from the reference clock phase via the pixel clock modulation means. 2. A second method for storing a phase difference from a specific reference clock as a phase shift number as a correction amount for finely adjusting a recording start position at which laser modulation is started by pixel data from the beam detection. The pixel clock modulation means is provided based on the correction amount stored in the second correction amount storage means during a period from the beam detection to the start of laser modulation by pixel data. 2. The recording start position can be adjusted in 1 / N pixel units by switching stepwise from a first detected clock phase to a clock phase corresponding to the correction amount. The image recording apparatus as described in the above. 3. The method according to claim 1, wherein the polarity of the correction amount of said first correction amount storage means is opposite to the polarity of the correction amount of said second correction amount storage means.
3. The image recording apparatus according to claim 2, wherein one is stored as a compression amount and the other is stored as an expansion amount. 4. A method for reading a correction amount from the first and second correction amount storage means at the same timing in synchronization with a pixel clock, and setting one of the correction amounts as a compression instruction and the other correction amount as an expansion instruction. The pixel clock modulating means is provided with an exclusive OR circuit, and the exclusive OR circuit takes an exclusive OR of the compression instruction and the decompression instruction, and 3. The image recording apparatus according to claim 2, wherein the pixel clock is modulated according to the result. 5. A correction information storage means for storing pixel pitch correction data for instructing a dynamic correction of an individual pixel pitch in an effective scanning area of a laser beam, and after the pixel clock modulation by the pixel clock modulation means is completed, Correction data readout means for reading out the correction data of the correction information storage means in synchronization with a pixel clock, wherein the pixel pitch correction data read from the correction information storage means by the correction data readout means is sent to the pixel clock modulation means. The apparatus according to claim 1, wherein pixel clock modulation is performed within an effective scanning area of the laser beam based on the input and pixel pitch correction data, and laser modulation based on pixel data is performed in a part of the effective scanning area. 2. The image recording apparatus according to 2.